Searched refs:ITATBCTR0 (Results 1 - 10 of 10) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A D	core_cm4.h	1065 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ member 1159 /** \brief TPIU ITATBCTR0 Register Definitions */ 1160 #define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ 1161 #define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ 1163 #define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ 1164 #define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */
H A D	core_sc300.h	983 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ member 1077 /** \brief TPIU ITATBCTR0 Register Definitions */ 1078 #define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ 1079 #define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ 1081 #define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ 1082 #define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */
H A D	core_cm3.h	1000 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ member 1094 /** \brief TPIU ITATBCTR0 Register Definitions */ 1095 #define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ 1096 #define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ 1098 #define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ 1099 #define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */
H A D	core_cm23.h	694 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ member 802 #define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ 803 #define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ 805 #define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ 806 #define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ 808 #define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ 809 #define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ 811 #define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ 812 #define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */
H A D	core_cm35p.h	1288 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ member 1396 #define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ 1397 #define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ 1399 #define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ 1400 #define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ 1402 #define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ 1403 #define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ 1405 #define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ 1406 #define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */
H A D	core_cm33.h	1288 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ member 1396 #define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ 1397 #define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ 1399 #define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ 1400 #define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ 1402 #define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ 1403 #define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ 1405 #define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ 1406 #define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */
H A D	core_cm7.h	1284 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ member 1378 /** \brief TPIU ITATBCTR0 Register Definitions */ 1379 #define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */ 1380 #define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */ 1382 #define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */ 1383 #define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */
H A D	core_starmc1.h	1385 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ member 1493 #define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ 1494 #define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ 1496 #define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ 1497 #define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ 1499 #define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ 1500 #define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ 1502 #define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ 1503 #define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */
H A D	core_cm85.h	1960 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ member 2068 #define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ 2069 #define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ 2071 #define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ 2072 #define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ 2074 #define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ 2075 #define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ 2077 #define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ 2078 #define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */
H A D	core_cm55.h	1936 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ member 2044 #define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ 2045 #define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ 2047 #define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ 2048 #define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ 2050 #define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ 2051 #define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ 2053 #define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ 2054 #define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */

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Indexes created Thu Nov 07 10:32:03 CST 2024