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Help
Searched
refs:ICTR
(Results
1 - 9
of
9
) sorted by relevance
/third_party/cmsis/CMSIS/Core/Include/
H
A
D
core_cm4.h
737
__IM uint32_t
ICTR
; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
member
742
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!<
ICTR
: INTLINESNUM Position */
743
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!<
ICTR
: INTLINESNUM Mask */
H
A
D
core_sc300.h
661
__IM uint32_t
ICTR
; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
member
666
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!<
ICTR
: INTLINESNUM Position */
667
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!<
ICTR
: INTLINESNUM Mask */
H
A
D
core_cm3.h
666
__IM uint32_t
ICTR
; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
member
675
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!<
ICTR
: INTLINESNUM Position */
676
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!<
ICTR
: INTLINESNUM Mask */
H
A
D
core_cm35p.h
960
__IM uint32_t
ICTR
; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
member
966
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!<
ICTR
: INTLINESNUM Position */
967
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!<
ICTR
: INTLINESNUM Mask */
H
A
D
core_cm33.h
960
__IM uint32_t
ICTR
; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
member
966
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!<
ICTR
: INTLINESNUM Position */
967
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!<
ICTR
: INTLINESNUM Mask */
H
A
D
core_cm7.h
938
__IM uint32_t
ICTR
; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
member
943
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!<
ICTR
: INTLINESNUM Position */
944
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!<
ICTR
: INTLINESNUM Mask */
H
A
D
core_starmc1.h
1021
__IM uint32_t
ICTR
; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
member
1027
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!<
ICTR
: INTLINESNUM Position */
1028
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!<
ICTR
: INTLINESNUM Mask */
H
A
D
core_cm85.h
1042
__IM uint32_t
ICTR
; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
member
1070
#define ICB_ICTR_INTLINESNUM_Pos 0U /*!<
ICTR
: INTLINESNUM Position */
1071
#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!<
ICTR
: INTLINESNUM Mask */
H
A
D
core_cm55.h
1021
__IM uint32_t
ICTR
; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
member
1070
#define ICB_ICTR_INTLINESNUM_Pos 0U /*!<
ICTR
: INTLINESNUM Position */
1071
#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!<
ICTR
: INTLINESNUM Mask */
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