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Help
Searched
refs:ICER
(Results
1 - 14
of
14
) sorted by relevance
/third_party/cmsis/CMSIS/Core/Include/
H
A
D
core_sc000.h
330
__IOM uint32_t
ICER
[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
808
NVIC->
ICER
[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
H
A
D
core_cm1.h
319
__IOM uint32_t
ICER
[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
702
NVIC->
ICER
[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
H
A
D
core_cm0.h
319
__IOM uint32_t
ICER
[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
675
NVIC->
ICER
[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
H
A
D
core_cm0plus.h
333
__IOM uint32_t
ICER
[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
793
NVIC->
ICER
[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
H
A
D
core_cm23.h
356
__IOM uint32_t
ICER
[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
1413
NVIC->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
1764
NVIC_NS->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in TZ_NVIC_DisableIRQ_NS()
H
A
D
core_cm4.h
423
__IOM uint32_t
ICER
[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
1735
NVIC->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
H
A
D
core_sc300.h
350
__IOM uint32_t
ICER
[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
1536
NVIC->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
H
A
D
core_cm3.h
350
__IOM uint32_t
ICER
[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
1553
NVIC->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
H
A
D
core_cm35p.h
489
__IOM uint32_t
ICER
[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
2267
NVIC->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
2642
NVIC_NS->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in TZ_NVIC_DisableIRQ_NS()
H
A
D
core_cm33.h
489
__IOM uint32_t
ICER
[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
2267
NVIC->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
2642
NVIC_NS->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in TZ_NVIC_DisableIRQ_NS()
H
A
D
core_starmc1.h
500
__IOM uint32_t
ICER
[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
2365
NVIC->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
2761
NVIC_NS->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in TZ_NVIC_DisableIRQ_NS()
H
A
D
core_cm7.h
438
__IOM uint32_t
ICER
[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
1954
NVIC->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
H
A
D
core_cm85.h
520
__IOM uint32_t
ICER
[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
3800
NVIC->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
4175
NVIC_NS->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in TZ_NVIC_DisableIRQ_NS()
H
A
D
core_cm55.h
499
__IOM uint32_t
ICER
[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
member
3776
NVIC->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in __NVIC_DisableIRQ()
4151
NVIC_NS->
ICER
[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
in TZ_NVIC_DisableIRQ_NS()
Completed in 79 milliseconds