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Searched refs:FPU_MVFR0_FPSP_Pos (Results 1 - 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_cm4.h1381 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ macro
1382 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
H A Dcore_cm35p.h1750 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ macro
1751 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
H A Dcore_cm33.h1750 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ macro
1751 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
H A Dcore_cm7.h1600 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ macro
1601 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
H A Dcore_starmc1.h1844 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ macro
1845 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
H A Dcore_cm85.h3226 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ macro
3227 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
H A Dcore_cm55.h3202 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ macro
3203 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */

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