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Searched refs:FPU_MVFR0_FPDP_Pos (Results 1 - 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_cm4.h1378 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ macro
1379 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
H A Dcore_cm35p.h1747 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ macro
1748 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
H A Dcore_cm33.h1747 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ macro
1748 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
H A Dcore_cm7.h1597 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ macro
1598 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
H A Dcore_starmc1.h1841 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ macro
1842 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
H A Dcore_cm85.h3223 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ macro
3224 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
H A Dcore_cm55.h3199 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ macro
3200 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */

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