Searched refs:FPCCR (Results 1 - 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A D	core_cm4.h	1309 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ member 1318 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 1319 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 1321 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 1322 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 1324 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 1325 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 1327 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 1328 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 1330 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR [all...]
H A D	core_cm35p.h	1654 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ member 1663 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 1664 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 1666 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 1667 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 1669 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ 1670 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ 1672 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ 1673 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ 1675 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR [all...]
H A D	core_cm33.h	1654 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ member 1663 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 1664 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 1666 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 1667 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 1669 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ 1670 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ 1672 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ 1673 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ 1675 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR [all...]
H A D	core_cm7.h	1528 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ member 1537 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 1538 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 1540 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 1541 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 1543 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 1544 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 1546 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 1547 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 1549 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR [all...]
H A D	core_starmc1.h	1748 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ member 1757 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 1758 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 1760 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 1761 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 1763 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ 1764 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ 1766 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ 1767 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ 1769 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR [all...]
H A D	core_cm85.h	3130 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ member 3139 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 3140 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 3142 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 3143 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 3145 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ 3146 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ 3148 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ 3149 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ 3151 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR [all...]
H A D	core_cm55.h	3106 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ member 3115 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 3116 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 3118 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 3119 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 3121 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ 3122 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ 3124 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ 3125 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ 3127 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR [all...]

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Indexes created Thu Nov 07 10:32:03 CST 2024