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Searched refs:CCR (Results 1 - 22 of 22) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A Darmv7m_cachel1.h58 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
65 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
81 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
146 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
167 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
195 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_starmc1.h539 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
691 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
692 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
694 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
695 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
697 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
698 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
700 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
701 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
703 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR
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H A Dcore_sc000.h360 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
443 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
446 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
H A Dcore_cm1.h349 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
426 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
427 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
429 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
430 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
H A Dcore_cm0.h349 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
426 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
427 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
429 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
430 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
H A Dcore_cm0plus.h367 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
450 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
451 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
453 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
454 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
H A Dcore_cm4.h460 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
564 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
565 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
567 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
568 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
570 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
571 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
573 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
574 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
576 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR
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H A Dcore_sc300.h387 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
494 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
495 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
497 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
498 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
500 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
501 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
503 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
504 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
506 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR
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H A Dcore_cm3.h387 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
499 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
500 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
502 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
503 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
505 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
506 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
508 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
509 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
511 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR
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H A Dcore_cm23.h393 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
500 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
501 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
503 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
504 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
506 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
507 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
509 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
510 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
512 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR
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H A Dcore_cm35p.h528 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
673 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
674 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
676 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
677 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
679 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
680 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
682 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
683 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
685 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR
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H A Dcore_cm33.h528 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
673 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
674 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
676 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
677 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
679 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
680 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
682 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
683 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
685 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR
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H A Dcore_cm7.h475 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
607 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
608 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
610 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
611 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
613 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
614 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
616 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
617 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
619 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR
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H A Dcore_cm85.h559 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
708 #define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
709 #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
711 #define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
712 #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
714 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
715 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
717 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
718 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
720 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR
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H A Dcore_cm55.h538 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
687 #define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
688 #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
690 #define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
691 #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
693 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
694 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
696 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
697 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
699 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR
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/third_party/node/deps/openssl/openssl/crypto/bn/asm/
H A Dvis3-mont.pl284 subcc %g0, $ovf, %g0 ! move upmost overflow to CCR.xcc
298 subcc $num, 8, $cnt ! cnt=num-1 and clear CCR.xcc
H A Dsparct4-mont.pl872 subcc %g0, $ovf, %g0 ! move upmost overflow to CCR.xcc
886 subcc $num, 8, $cnt ! cnt=num-1 and clear CCR.xcc
1124 subcc %g0, $ovf, %g0 ! move upmost overflow to CCR.xcc
1138 subcc $num, 8, $cnt ! cnt=num-1 and clear CCR.xcc
/third_party/openssl/crypto/bn/asm/
H A Dvis3-mont.pl284 subcc %g0, $ovf, %g0 ! move upmost overflow to CCR.xcc
298 subcc $num, 8, $cnt ! cnt=num-1 and clear CCR.xcc
H A Dsparct4-mont.pl872 subcc %g0, $ovf, %g0 ! move upmost overflow to CCR.xcc
886 subcc $num, 8, $cnt ! cnt=num-1 and clear CCR.xcc
1124 subcc %g0, $ovf, %g0 ! move upmost overflow to CCR.xcc
1138 subcc $num, 8, $cnt ! cnt=num-1 and clear CCR.xcc
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4474 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO() local
4482 ARMcc, CCR, OverflowCmp); in LowerSignedALUO()
4594 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT() local
4597 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR, in LowerSELECT()
4629 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
4632 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG); in LowerSELECT()
4698 SDValue TrueVal, SDValue ARMcc, SDValue CCR, in getCMOV()
4712 ARMcc, CCR, Cmp); in getCMOV()
4714 ARMcc, CCR, duplicateCmp(Cmp, DAG)); in getCMOV()
4718 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR, in getCMOV()
4697 getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, SDValue ARMcc, SDValue CCR, SDValue Cmp, SelectionDAG &DAG) const getCMOV() argument
5046 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); LowerSELECT_CC() local
5081 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); LowerSELECT_CC() local
5188 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); OptimizeVFPBrcond() local
5237 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); LowerBRCOND() local
5291 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); LowerBR_CC() local
5300 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); LowerBR_CC() local
5317 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); LowerBR_CC() local
5855 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); LowerShiftRightParts() local
5899 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); LowerShiftLeftParts() local
6415 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); LowerSETCCCARRY() local
9275 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); LowerFSETCC() local
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H A DARMISelLowering.h818 SDValue ARMcc, SDValue CCR, SDValue Cmp,
/third_party/libunwind/libunwind/src/ptrace/
H A D_UPT_reg_offset.c471 [UNW_PPC32_CCR] = UNW_PPC_PT(CCR)

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