| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_mca.c | 77 struct amdgpu_mca_ras_block *ras; in amdgpu_mca_mp0_ras_sw_init() local
79 if (!adev->mca.mp0.ras) in amdgpu_mca_mp0_ras_sw_init()
82 ras = adev->mca.mp0.ras; in amdgpu_mca_mp0_ras_sw_init()
84 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mca_mp0_ras_sw_init()
86 dev_err(adev->dev, "Failed to register mca.mp0 ras block!\n"); in amdgpu_mca_mp0_ras_sw_init()
90 strcpy(ras->ras_block.ras_comm.name, "mca.mp0"); in amdgpu_mca_mp0_ras_sw_init()
91 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mp0_ras_sw_init()
92 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mca_mp0_ras_sw_init()
93 adev->mca.mp0.ras_if = &ras in amdgpu_mca_mp0_ras_sw_init()
101 struct amdgpu_mca_ras_block *ras; amdgpu_mca_mp1_ras_sw_init() local
125 struct amdgpu_mca_ras_block *ras; amdgpu_mca_mpio_ras_sw_init() local
[all...] |
| H A D | amdgpu_umc.c | 91 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
92 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_do_page_retirement()
93 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
95 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
96 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_do_page_retirement()
112 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
115 if (adev->umc.ras && in amdgpu_umc_do_page_retirement()
116 adev->umc.ras in amdgpu_umc_do_page_retirement()
218 struct amdgpu_umc_ras *ras; amdgpu_umc_ras_sw_init() local
[all...] |
| H A D | amdgpu_mmhub.c | 27 struct amdgpu_mmhub_ras *ras; in amdgpu_mmhub_ras_sw_init() local
29 if (!adev->mmhub.ras) in amdgpu_mmhub_ras_sw_init()
32 ras = adev->mmhub.ras; in amdgpu_mmhub_ras_sw_init()
33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
35 dev_err(adev->dev, "Failed to register mmhub ras block!\n"); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras in amdgpu_mmhub_ras_sw_init()
[all...] |
| H A D | amdgpu_hdp.c | 29 struct amdgpu_hdp_ras *ras; in amdgpu_hdp_ras_sw_init() local
31 if (!adev->hdp.ras) in amdgpu_hdp_ras_sw_init()
34 ras = adev->hdp.ras; in amdgpu_hdp_ras_sw_init()
35 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_hdp_ras_sw_init()
37 dev_err(adev->dev, "Failed to register hdp ras block!\n"); in amdgpu_hdp_ras_sw_init()
41 strcpy(ras->ras_block.ras_comm.name, "hdp"); in amdgpu_hdp_ras_sw_init()
42 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__HDP; in amdgpu_hdp_ras_sw_init()
43 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_hdp_ras_sw_init()
44 adev->hdp.ras_if = &ras in amdgpu_hdp_ras_sw_init()
[all...] |
| H A D | amdgpu_nbio.c | 28 struct amdgpu_nbio_ras *ras; in amdgpu_nbio_ras_sw_init() local
30 if (!adev->nbio.ras) in amdgpu_nbio_ras_sw_init()
33 ras = adev->nbio.ras; in amdgpu_nbio_ras_sw_init()
34 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_nbio_ras_sw_init()
36 dev_err(adev->dev, "Failed to register pcie_bif ras block!\n"); in amdgpu_nbio_ras_sw_init()
40 strcpy(ras->ras_block.ras_comm.name, "pcie_bif"); in amdgpu_nbio_ras_sw_init()
41 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF; in amdgpu_nbio_ras_sw_init()
42 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_nbio_ras_sw_init()
43 adev->nbio.ras_if = &ras in amdgpu_nbio_ras_sw_init()
[all...] |
| H A D | amdgpu_sdma.c | 316 struct amdgpu_sdma_ras *ras = NULL; in amdgpu_sdma_ras_sw_init() local
318 /* adev->sdma.ras is NULL, which means sdma does not in amdgpu_sdma_ras_sw_init()
319 * support ras function, then do nothing here. in amdgpu_sdma_ras_sw_init()
321 if (!adev->sdma.ras) in amdgpu_sdma_ras_sw_init()
324 ras = adev->sdma.ras; in amdgpu_sdma_ras_sw_init()
326 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_sdma_ras_sw_init()
328 dev_err(adev->dev, "Failed to register sdma ras block!\n"); in amdgpu_sdma_ras_sw_init()
332 strcpy(ras->ras_block.ras_comm.name, "sdma"); in amdgpu_sdma_ras_sw_init()
333 ras in amdgpu_sdma_ras_sw_init()
[all...] |
| H A D | amdgpu_jpeg.c | 277 struct amdgpu_jpeg_ras *ras; in amdgpu_jpeg_ras_sw_init() local
279 if (!adev->jpeg.ras) in amdgpu_jpeg_ras_sw_init()
282 ras = adev->jpeg.ras; in amdgpu_jpeg_ras_sw_init()
283 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_jpeg_ras_sw_init()
285 dev_err(adev->dev, "Failed to register jpeg ras block!\n"); in amdgpu_jpeg_ras_sw_init()
289 strcpy(ras->ras_block.ras_comm.name, "jpeg"); in amdgpu_jpeg_ras_sw_init()
290 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in amdgpu_jpeg_ras_sw_init()
291 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_jpeg_ras_sw_init()
292 adev->jpeg.ras_if = &ras in amdgpu_jpeg_ras_sw_init()
[all...] |
| H A D | amdgpu_ras.c | 47 static const char *RAS_FS_NAME = "ras";
85 /* ras block link */
185 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); in amdgpu_reserve_page_direct()
413 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
414 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
415 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
438 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
439 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
440 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
444 * To check disable/enable, see "ras" feature
987 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_get_ecc_info() local
2022 struct amdgpu_ras *ras = amdgpu_ras_do_recovery() local
2983 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_global_ras_isr() local
3142 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_is_supported() local
3169 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_reset_gpu() local
[all...] |
| H A D | amdgpu_ras_eeprom.c | 322 DRM_ERROR("Failed to alloc buf to write table ras info\n"); in __write_table_ras_info()
337 DRM_ERROR("Failed to write EEPROM table ras info:%d", res); in __write_table_ras_info()
426 if (adev->umc.ras && in amdgpu_ras_eeprom_reset_table()
427 adev->umc.ras->set_eeprom_table_version) in amdgpu_ras_eeprom_reset_table()
428 adev->umc.ras->set_eeprom_table_version(hdr); in amdgpu_ras_eeprom_reset_table()
720 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_eeprom_update_header() local
728 control->ras_num_recs >= ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
731 control->ras_num_recs, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_update_header()
780 control->ras_num_recs < ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_update_header()
781 control->tbl_rai.health_percent = ((ras in amdgpu_ras_eeprom_update_header()
1003 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_debugfs_eeprom_size_read() local
1060 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, amdgpu_ras_debugfs_set_ret_size() local
1072 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_debugfs_table_read() local
1187 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_debugfs_eeprom_table_read() local
1311 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_eeprom_init() local
[all...] |
| H A D | umc_v6_7.c | 101 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_correctable_error_count() local
109 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_correctable_error_count()
116 if (ras->umc_ecc.record_ce_addr_supported) { in umc_v6_7_ecc_info_query_correctable_error_count()
121 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr; in umc_v6_7_ecc_info_query_correctable_error_count()
143 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_querry_uncorrectable_error_count() local
150 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
228 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_error_address() local
232 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_error_address()
244 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v6_7_ecc_info_query_error_address()
|
| H A D | amdgpu_gfx.c | 821 struct amdgpu_gfx_ras *ras = NULL; in amdgpu_gfx_ras_sw_init() local
823 /* adev->gfx.ras is NULL, which means gfx does not in amdgpu_gfx_ras_sw_init()
824 * support ras function, then do nothing here. in amdgpu_gfx_ras_sw_init()
826 if (!adev->gfx.ras) in amdgpu_gfx_ras_sw_init()
829 ras = adev->gfx.ras; in amdgpu_gfx_ras_sw_init()
831 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_gfx_ras_sw_init()
833 dev_err(adev->dev, "Failed to register gfx ras block!\n"); in amdgpu_gfx_ras_sw_init()
837 strcpy(ras->ras_block.ras_comm.name, "gfx"); in amdgpu_gfx_ras_sw_init()
838 ras in amdgpu_gfx_ras_sw_init()
[all...] |
| H A D | aldebaran.c | 365 if (tmp_adev->sdma.ras && in aldebaran_mode2_restore_hwcontext()
366 tmp_adev->sdma.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
367 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
368 &tmp_adev->sdma.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
375 if (tmp_adev->gfx.ras && in aldebaran_mode2_restore_hwcontext()
376 tmp_adev->gfx.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
377 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
378 &tmp_adev->gfx.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
|
| H A D | umc_v8_10.c | 341 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_correctable_error_count() local
349 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_correctable_error_count()
362 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_uncorrectable_error_count() local
370 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_uncorrectable_error_count()
410 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_error_address() local
417 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_error_address()
430 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_10_ecc_info_query_error_address()
|
| H A D | umc_v8_7.c | 56 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_correctable_error_count() local
63 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_correctable_error_count()
75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_querry_uncorrectable_error_count() local
80 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
137 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_error_address() local
140 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_error_address()
152 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_7_ecc_info_query_error_address()
|
| H A D | amdgpu_xgmi.c | 891 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_xgmi_ras_late_init()
1057 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_xgmi_query_ras_error_count()
1107 struct amdgpu_xgmi_ras *ras; in amdgpu_xgmi_ras_sw_init() local
1109 if (!adev->gmc.xgmi.ras) in amdgpu_xgmi_ras_sw_init()
1112 ras = adev->gmc.xgmi.ras; in amdgpu_xgmi_ras_sw_init()
1113 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_xgmi_ras_sw_init()
1115 dev_err(adev->dev, "Failed to register xgmi_wafl_pcs ras block!\n"); in amdgpu_xgmi_ras_sw_init()
1119 strcpy(ras->ras_block.ras_comm.name, "xgmi_wafl"); in amdgpu_xgmi_ras_sw_init()
1120 ras in amdgpu_xgmi_ras_sw_init()
[all...] |
| H A D | gfx_v11_0_3.c | 60 dev_err(adev->dev, "Gfx or sdma ras block not initialized, rlc_status0:0x%x.\n", in gfx_v11_0_3_rlc_gc_fed_irq()
94 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in gfx_v11_0_3_poison_consumption_handler() local
96 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET; in gfx_v11_0_3_poison_consumption_handler()
|
| H A D | gmc_v9_0.c | 1468 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1477 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1487 adev->umc.ras = &umc_v6_7_ras; in gmc_v9_0_set_umc_funcs()
1520 adev->mmhub.ras = &mmhub_v1_0_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1523 adev->mmhub.ras = &mmhub_v9_4_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1526 adev->mmhub.ras = &mmhub_v1_7_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1529 adev->mmhub.ras = &mmhub_v1_8_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1532 /* mmhub ras is not available */ in gmc_v9_0_set_mmhub_ras_funcs()
1547 adev->hdp.ras = &hdp_v4_0_ras; in gmc_v9_0_set_hdp_ras_funcs()
1558 mca->mp0.ras in gmc_v9_0_set_mca_ras_funcs()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_ras.h | 315 /* ras infrastructure */
316 /* for ras itself. */
318 /* for IP to check its ras ability. */
347 /* disable ras error count harvest in recovery */
399 /* ras block link */
467 * 1: ras feature enable (enabled by default)
469 * 2: ras framework init (in ip_init)
479 #define amdgpu_ras_get_context(adev) ((adev)->psp.ras.ras)
480 #define amdgpu_ras_set_context(adev, ras_con) ((adev)->psp.ras
486 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_is_supported() local
513 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_reset_gpu() local
[all...] |
| H A D | amdgpu_psp.c | 919 // ras begin
926 * physical) for ras ta <-> Driver in psp_ras_init_shared_buf()
930 &psp->ras.ras_shared_bo, in psp_ras_init_shared_buf()
931 &psp->ras.ras_shared_mc_addr, in psp_ras_init_shared_buf()
932 &psp->ras.ras_shared_buf); in psp_ras_init_shared_buf()
959 psp->ras.ras_shared_mc_addr, in psp_ras_load()
965 ras_cmd = (struct ta_ras_shared_memory*)psp->ras.ras_shared_buf; in psp_ras_load()
968 psp->ras.session_id = cmd->resp.session_id; in psp_ras_load()
971 psp->ras.ras_initialized = true; in psp_ras_load()
999 psp_prep_ta_unload_cmd_buf(cmd, psp->ras in psp_ras_unload()
1900 struct amdgpu_ras *ras = psp->ras.ras; psp_load_smu_fw() local
[all...] |
| /kernel/linux/linux-5.10/drivers/ras/ |
| H A D | ras.c | 10 #include <linux/ras.h>
14 #define TRACE_INCLUDE_PATH ../../include/ras
15 #include <ras/ras_event.h>
55 __setup("ras", parse_ras_param);
|
| /kernel/linux/linux-6.6/drivers/ras/ |
| H A D | ras.c | 10 #include <linux/ras.h>
14 #define TRACE_INCLUDE_PATH ../../include/ras
15 #include <ras/ras_event.h>
55 __setup("ras", parse_ras_param);
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega20_baco.c | 77 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in vega20_baco_set_state() local
88 if (!ras || !ras->supported) { in vega20_baco_set_state()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega20_baco.c | 76 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in vega20_baco_set_state() local
87 if (!ras || !adev->ras_enabled) { in vega20_baco_set_state()
|
| /kernel/linux/linux-5.10/drivers/edac/ |
| H A D | i5100_edac.c | 438 unsigned ras, in i5100_handle_ce()
445 "bank %u, cas %u, ras %u\n", in i5100_handle_ce()
446 bank, cas, ras); in i5100_handle_ce()
460 unsigned ras, in i5100_handle_ue()
467 "bank %u, cas %u, ras %u\n", in i5100_handle_ue()
468 bank, cas, ras); in i5100_handle_ue()
488 unsigned ras; in i5100_read_log() local
508 ras = i5100_recmemb_ras(dw2); in i5100_read_log()
517 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
530 ras in i5100_read_log()
432 i5100_handle_ce(struct mem_ctl_info *mci, int chan, unsigned bank, unsigned rank, unsigned long syndrome, unsigned cas, unsigned ras, const char *msg) i5100_handle_ce() argument
454 i5100_handle_ue(struct mem_ctl_info *mci, int chan, unsigned bank, unsigned rank, unsigned long syndrome, unsigned cas, unsigned ras, const char *msg) i5100_handle_ue() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/edac/ |
| H A D | i5100_edac.c | 433 unsigned ras, in i5100_handle_ce()
440 "bank %u, cas %u, ras %u\n", in i5100_handle_ce()
441 bank, cas, ras); in i5100_handle_ce()
455 unsigned ras, in i5100_handle_ue()
462 "bank %u, cas %u, ras %u\n", in i5100_handle_ue()
463 bank, cas, ras); in i5100_handle_ue()
483 unsigned ras; in i5100_read_log() local
503 ras = i5100_recmemb_ras(dw2); in i5100_read_log()
512 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
525 ras in i5100_read_log()
427 i5100_handle_ce(struct mem_ctl_info *mci, int chan, unsigned bank, unsigned rank, unsigned long syndrome, unsigned cas, unsigned ras, const char *msg) i5100_handle_ce() argument
449 i5100_handle_ue(struct mem_ctl_info *mci, int chan, unsigned bank, unsigned rank, unsigned long syndrome, unsigned cas, unsigned ras, const char *msg) i5100_handle_ue() argument
[all...] |