Home
last modified time | relevance | path

Searched refs:mux_pll_src_3plls_p (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/rockchip/
H A Dclk-rk3036.c119 PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; variable
209 COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
261 COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
267 COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
271 COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
274 COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
277 COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
306 COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
319 COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
330 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p,
[all...]
H A Dclk-rk3128.c138 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" }; variable
342 COMPOSITE(DCLK_EBC, "dclk_ebc", mux_pll_src_3plls_p, 0,
356 COMPOSITE(0, "i2s0_src", mux_pll_src_3plls_p, 0,
366 COMPOSITE(0, "i2s1_src", mux_pll_src_3plls_p, 0,
379 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_3plls_p, 0,
403 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0,
432 COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0,
446 COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_3plls_p, 0,
450 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
H A Dclk-rk3228.c141 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; variable
324 COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,
/kernel/linux/linux-6.6/drivers/clk/rockchip/
H A Dclk-rk3036.c120 PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; variable
211 COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
263 COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_3plls_p, 0,
269 COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
273 COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
276 COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
279 COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
308 COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
321 COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
332 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p,
[all...]
H A Dclk-rk3128.c139 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" }; variable
337 COMPOSITE(DCLK_EBC, "dclk_ebc", mux_pll_src_3plls_p, 0,
351 COMPOSITE(0, "i2s0_src", mux_pll_src_3plls_p, 0,
361 COMPOSITE(0, "i2s1_src", mux_pll_src_3plls_p, 0,
374 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_3plls_p, 0,
398 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0,
427 COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0,
441 COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_3plls_p, 0,
445 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
H A Dclk-rk3228.c142 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; variable
325 COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,

Completed in 5 milliseconds