Home
last modified time | relevance | path

Searched refs:clk_rate (Results 1 - 25 of 295) sorted by relevance

12345678910>>...12

/kernel/linux/linux-5.10/drivers/memory/
H A Dti-aemif.c115 * @clk_rate: clock's rate in kHz
123 unsigned long clk_rate; member
179 unsigned long clk_rate = aemif->clk_rate; in aemif_config_abus() local
185 ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); in aemif_config_abus()
186 rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); in aemif_config_abus()
187 rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX); in aemif_config_abus()
188 rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX); in aemif_config_abus()
189 whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); in aemif_config_abus()
190 wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MA in aemif_config_abus()
217 aemif_cycles_to_nsec(int val, unsigned long clk_rate) aemif_cycles_to_nsec() argument
235 unsigned long clk_rate = aemif->clk_rate; aemif_get_hw_params() local
[all...]
/kernel/linux/linux-6.6/drivers/memory/
H A Dti-aemif.c115 * @clk_rate: clock's rate in kHz
123 unsigned long clk_rate; member
179 unsigned long clk_rate = aemif->clk_rate; in aemif_config_abus() local
185 ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); in aemif_config_abus()
186 rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); in aemif_config_abus()
187 rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX); in aemif_config_abus()
188 rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX); in aemif_config_abus()
189 whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); in aemif_config_abus()
190 wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MA in aemif_config_abus()
217 aemif_cycles_to_nsec(int val, unsigned long clk_rate) aemif_cycles_to_nsec() argument
235 unsigned long clk_rate = aemif->clk_rate; aemif_get_hw_params() local
[all...]
/kernel/linux/linux-5.10/drivers/clocksource/
H A Dtimer-oxnas-rps.c130 ulong clk_rate = clk_get_rate(rps->clk); in oxnas_rps_clockevent_init() local
135 rps->timer_period = DIV_ROUND_UP(clk_rate, HZ); in oxnas_rps_clockevent_init()
136 timer_rate = clk_rate; in oxnas_rps_clockevent_init()
140 timer_rate = clk_rate / 16; in oxnas_rps_clockevent_init()
145 timer_rate = clk_rate / 256; in oxnas_rps_clockevent_init()
167 clk_rate, in oxnas_rps_clockevent_init()
185 ulong clk_rate = clk_get_rate(rps->clk); in oxnas_rps_clocksource_init() local
189 clk_rate = clk_rate / 16; in oxnas_rps_clocksource_init()
197 TIMER_BITS, clk_rate); in oxnas_rps_clocksource_init()
[all...]
H A Dtimer-microchip-pit64b.c190 static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate, in mchp_pit64b_pres_compute() argument
196 tmp = clk_rate / (*pres + 1); in mchp_pit64b_pres_compute()
297 u32 clk_rate) in mchp_pit64b_init_clksrc()
305 ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate, in mchp_pit64b_init_clksrc()
317 sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate); in mchp_pit64b_init_clksrc()
323 u32 clk_rate, u32 irq) in mchp_pit64b_init_clkevt()
332 mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ); in mchp_pit64b_init_clkevt()
357 clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX); in mchp_pit64b_init_clkevt()
367 unsigned long clk_rate; in mchp_pit64b_dt_init_timer() local
406 clk_rate in mchp_pit64b_dt_init_timer()
296 mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, u32 clk_rate) mchp_pit64b_init_clksrc() argument
322 mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer, u32 clk_rate, u32 irq) mchp_pit64b_init_clkevt() argument
[all...]
/kernel/linux/linux-6.6/drivers/ufs/host/
H A Dufs-mediatek-trace.h32 TP_PROTO(const char *name, bool scale_up, unsigned long clk_rate),
33 TP_ARGS(name, scale_up, clk_rate),
38 __field(unsigned long, clk_rate)
44 __entry->clk_rate = clk_rate;
50 __entry->clk_rate)
/kernel/linux/linux-5.10/drivers/watchdog/
H A Dloongson1_wdt.c23 unsigned long clk_rate; member
45 counts = drvdata->clk_rate * min(timeout, max_hw_heartbeat); in ls1x_wdt_set_timeout()
92 unsigned long clk_rate; in ls1x_wdt_probe() local
117 clk_rate = clk_get_rate(drvdata->clk); in ls1x_wdt_probe()
118 if (!clk_rate) in ls1x_wdt_probe()
120 drvdata->clk_rate = clk_rate; in ls1x_wdt_probe()
127 ls1x_wdt->max_hw_heartbeat_ms = U32_MAX / clk_rate * 1000; in ls1x_wdt_probe()
H A Dimgpdc_wdt.c116 unsigned long clk_rate = clk_get_rate(wdt->wdt_clk); in __pdc_wdt_set_timeout() local
120 val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1; in __pdc_wdt_set_timeout()
188 unsigned long clk_rate; in pdc_wdt_probe() local
232 clk_rate = clk_get_rate(pdc_wdt->wdt_clk); in pdc_wdt_probe()
233 if (clk_rate == 0) { in pdc_wdt_probe()
238 if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) { in pdc_wdt_probe()
243 if (order_base_2(clk_rate) == 0) in pdc_wdt_probe()
252 do_div(div, clk_rate); in pdc_wdt_probe()
H A Dtangox_wdt.c43 unsigned long clk_rate; member
60 ticks = 1 + wdt->timeout * dev->clk_rate; in tangox_wdt_start()
85 return (count - 1) / dev->clk_rate; in tangox_wdt_get_timeleft()
142 dev->clk_rate = clk_get_rate(dev->clk); in tangox_wdt_probe()
143 if (!dev->clk_rate) in tangox_wdt_probe()
151 dev->wdt.max_hw_heartbeat_ms = (U32_MAX - 1) / dev->clk_rate; in tangox_wdt_probe()
/kernel/linux/linux-5.10/drivers/char/hw_random/
H A Dks-sa-rng.c93 static unsigned int cycles_to_ns(unsigned long clk_rate, unsigned int cycles) in cycles_to_ns() argument
96 cycles, clk_rate); in cycles_to_ns()
99 static unsigned int startup_delay_ns(unsigned long clk_rate) in startup_delay_ns() argument
102 return cycles_to_ns(clk_rate, BIT(24)); in startup_delay_ns()
103 return cycles_to_ns(clk_rate, 256 * TRNG_DEF_STARTUP_CYCLES); in startup_delay_ns()
106 static unsigned int refill_delay_ns(unsigned long clk_rate) in refill_delay_ns() argument
109 return cycles_to_ns(clk_rate, BIT(24)); in refill_delay_ns()
110 return cycles_to_ns(clk_rate, 256 * TRNG_DEF_MAX_REFILL_CYCLES); in refill_delay_ns()
118 unsigned long clk_rate = clk_get_rate(ks_sa_rng->clk); in ks_sa_rng_init() local
147 ks_sa_rng->refill_delay_ns = refill_delay_ns(clk_rate); in ks_sa_rng_init()
[all...]
/kernel/linux/linux-6.6/drivers/char/hw_random/
H A Dks-sa-rng.c93 static unsigned int cycles_to_ns(unsigned long clk_rate, unsigned int cycles) in cycles_to_ns() argument
96 cycles, clk_rate); in cycles_to_ns()
99 static unsigned int startup_delay_ns(unsigned long clk_rate) in startup_delay_ns() argument
102 return cycles_to_ns(clk_rate, BIT(24)); in startup_delay_ns()
103 return cycles_to_ns(clk_rate, 256 * TRNG_DEF_STARTUP_CYCLES); in startup_delay_ns()
106 static unsigned int refill_delay_ns(unsigned long clk_rate) in refill_delay_ns() argument
109 return cycles_to_ns(clk_rate, BIT(24)); in refill_delay_ns()
110 return cycles_to_ns(clk_rate, 256 * TRNG_DEF_MAX_REFILL_CYCLES); in refill_delay_ns()
118 unsigned long clk_rate = clk_get_rate(ks_sa_rng->clk); in ks_sa_rng_init() local
147 ks_sa_rng->refill_delay_ns = refill_delay_ns(clk_rate); in ks_sa_rng_init()
[all...]
/kernel/linux/linux-5.10/drivers/pwm/
H A Dpwm-omap-dmtimer.c80 * @clk_rate: pwm timer clock rate
85 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns) in pwm_omap_dmtimer_get_clock_cycles() argument
87 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC); in pwm_omap_dmtimer_get_clock_cycles()
158 unsigned long clk_rate; in pwm_omap_dmtimer_config() local
174 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
175 if (!clk_rate) { in pwm_omap_dmtimer_config()
180 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate); in pwm_omap_dmtimer_config()
198 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns); in pwm_omap_dmtimer_config()
199 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns); in pwm_omap_dmtimer_config()
204 period_ns, clk_rate); in pwm_omap_dmtimer_config()
[all...]
/kernel/linux/linux-6.6/drivers/pwm/
H A Dpwm-omap-dmtimer.c80 * @clk_rate: pwm timer clock rate
85 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns) in pwm_omap_dmtimer_get_clock_cycles() argument
87 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC); in pwm_omap_dmtimer_get_clock_cycles()
158 unsigned long clk_rate; in pwm_omap_dmtimer_config() local
174 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
175 if (!clk_rate) { in pwm_omap_dmtimer_config()
180 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate); in pwm_omap_dmtimer_config()
198 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns); in pwm_omap_dmtimer_config()
199 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns); in pwm_omap_dmtimer_config()
204 period_ns, clk_rate); in pwm_omap_dmtimer_config()
[all...]
H A Dpwm-sunplus.c61 u64 clk_rate; in sunplus_pwm_apply() local
78 clk_rate = clk_get_rate(priv->clk); in sunplus_pwm_apply()
85 if (clk_rate > (u64)SP7021_PWM_FREQ_SCALER * NSEC_PER_SEC) in sunplus_pwm_apply()
89 * With clk_rate limited above we have dd_freq <= state->period, in sunplus_pwm_apply()
92 dd_freq = mul_u64_u64_div_u64(clk_rate, state->period, (u64)SP7021_PWM_FREQ_SCALER in sunplus_pwm_apply()
115 * duty_ns <= period_ns 27 bits, clk_rate 28 bits, won't overflow. in sunplus_pwm_apply()
117 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, in sunplus_pwm_apply()
133 u64 clk_rate; in sunplus_pwm_get_state() local
138 clk_rate = clk_get_rate(priv->clk); in sunplus_pwm_get_state()
147 * NSEC_PER_SEC, clk_rate); in sunplus_pwm_get_state()
[all...]
H A Dpwm-keembay.c97 unsigned long clk_rate; in keembay_pwm_get_state() local
100 clk_rate = clk_get_rate(priv->clk); in keembay_pwm_get_state()
113 state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate); in keembay_pwm_get_state()
114 state->period = DIV_ROUND_UP_ULL(high + low, clk_rate); in keembay_pwm_get_state()
126 unsigned long clk_rate; in keembay_pwm_apply() local
154 clk_rate = clk_get_rate(priv->clk); in keembay_pwm_apply()
155 div = clk_rate * state->duty_cycle; in keembay_pwm_apply()
161 div = clk_rate * state->period; in keembay_pwm_apply()
H A Dpwm-sun4i.c115 u64 clk_rate, tmp; in sun4i_pwm_get_state() local
119 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_get_state()
120 if (!clk_rate) in sun4i_pwm_get_state()
132 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); in sun4i_pwm_get_state()
162 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
165 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
175 u64 clk_rate, div = 0; in sun4i_pwm_calculate() local
178 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_calculate()
182 (state->period * clk_rate >= NSEC_PER_SEC) && in sun4i_pwm_calculate()
183 (state->period * clk_rate < in sun4i_pwm_calculate()
[all...]
/kernel/linux/linux-6.6/drivers/mfd/
H A Dintel-lpss-acpi.c32 .clk_rate = 120000000,
46 .clk_rate = 120000000,
62 .clk_rate = 120000000,
77 .clk_rate = 100000000,
93 .clk_rate = 133000000,
109 .clk_rate = 133000000,
123 .clk_rate = 120000000,
128 .clk_rate = 216000000,
/kernel/linux/linux-6.6/drivers/watchdog/
H A Dloongson1_wdt.c29 unsigned long clk_rate; member
51 counts = drvdata->clk_rate * min(timeout, max_hw_heartbeat); in ls1x_wdt_set_timeout()
106 unsigned long clk_rate; in ls1x_wdt_probe() local
121 clk_rate = clk_get_rate(drvdata->clk); in ls1x_wdt_probe()
122 if (!clk_rate) in ls1x_wdt_probe()
124 drvdata->clk_rate = clk_rate; in ls1x_wdt_probe()
131 ls1x_wdt->max_hw_heartbeat_ms = U32_MAX / clk_rate * 1000; in ls1x_wdt_probe()
H A Dimgpdc_wdt.c116 unsigned long clk_rate = clk_get_rate(wdt->wdt_clk); in __pdc_wdt_set_timeout() local
120 val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1; in __pdc_wdt_set_timeout()
183 unsigned long clk_rate; in pdc_wdt_probe() local
207 clk_rate = clk_get_rate(pdc_wdt->wdt_clk); in pdc_wdt_probe()
208 if (clk_rate == 0) { in pdc_wdt_probe()
213 if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) { in pdc_wdt_probe()
218 if (order_base_2(clk_rate) == 0) in pdc_wdt_probe()
227 do_div(div, clk_rate); in pdc_wdt_probe()
H A Dapple_wdt.c59 unsigned long clk_rate; member
100 writel_relaxed(wdt->clk_rate * s, wdt->regs + APPLE_WDT_WD1_BITE_TIME); in apple_wdt_set_timeout()
115 return (reset_time - cur_time) / wdt->clk_rate; in apple_wdt_get_timeleft()
172 wdt->clk_rate = clk_get_rate(clk); in apple_wdt_probe()
173 if (!wdt->clk_rate) in apple_wdt_probe()
178 wdt->wdd.max_timeout = U32_MAX / wdt->clk_rate; in apple_wdt_probe()
/kernel/linux/linux-6.6/drivers/clocksource/
H A Dtimer-microchip-pit64b.c239 static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate, in mchp_pit64b_pres_compute() argument
245 tmp = clk_rate / (*pres + 1); in mchp_pit64b_pres_compute()
348 u32 clk_rate) in mchp_pit64b_init_clksrc()
374 ret = clocksource_register_hz(&cs->clksrc, clk_rate); in mchp_pit64b_init_clksrc()
385 sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate); in mchp_pit64b_init_clksrc()
388 mchp_pit64b_dt.freq = clk_rate; in mchp_pit64b_init_clksrc()
395 u32 clk_rate, u32 irq) in mchp_pit64b_init_clkevt()
404 mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ); in mchp_pit64b_init_clkevt()
428 clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX); in mchp_pit64b_init_clkevt()
437 unsigned long clk_rate; in mchp_pit64b_dt_init_timer() local
347 mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, u32 clk_rate) mchp_pit64b_init_clksrc() argument
394 mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer, u32 clk_rate, u32 irq) mchp_pit64b_init_clkevt() argument
[all...]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
H A Dmcfclk.h35 #define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
39 .rate = clk_rate, \
46 #define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
49 .rate = clk_rate, \
/kernel/linux/linux-6.6/arch/m68k/include/asm/
H A Dmcfclk.h32 #define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
35 .rate = clk_rate, \
42 #define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
44 .rate = clk_rate, \
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_core_perf.c138 "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n", in _dpu_core_perf_calc_crtc()
302 u64 clk_rate = kms->perf.perf_tune.min_core_clk; in _dpu_core_perf_get_core_clk_rate() local
309 clk_rate = max(dpu_cstate->new_perf.core_clk_rate, in _dpu_core_perf_get_core_clk_rate()
310 clk_rate); in _dpu_core_perf_get_core_clk_rate()
311 clk_rate = clk_round_rate(kms->perf.core_clk->clk, in _dpu_core_perf_get_core_clk_rate()
312 clk_rate); in _dpu_core_perf_get_core_clk_rate()
317 clk_rate = kms->perf.fix_core_clk_rate; in _dpu_core_perf_get_core_clk_rate()
319 DPU_DEBUG("clk:%llu\n", clk_rate); in _dpu_core_perf_get_core_clk_rate()
321 return clk_rate; in _dpu_core_perf_get_core_clk_rate()
329 u64 clk_rate in dpu_core_perf_crtc_update() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_core_perf.c138 "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n", in _dpu_core_perf_calc_crtc()
282 u64 clk_rate; in _dpu_core_perf_get_core_clk_rate() local
292 clk_rate = 0; in _dpu_core_perf_get_core_clk_rate()
296 clk_rate = max(dpu_cstate->new_perf.core_clk_rate, in _dpu_core_perf_get_core_clk_rate()
297 clk_rate); in _dpu_core_perf_get_core_clk_rate()
301 return clk_rate; in _dpu_core_perf_get_core_clk_rate()
309 u64 clk_rate = 0; in dpu_core_perf_crtc_update() local
380 clk_rate = _dpu_core_perf_get_core_clk_rate(kms); in dpu_core_perf_crtc_update()
382 DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate); in dpu_core_perf_crtc_update()
384 trace_dpu_core_perf_update_clk(kms->dev, !crtc->enabled, clk_rate); in dpu_core_perf_crtc_update()
[all...]
/kernel/linux/linux-5.10/drivers/mfd/
H A Dintel-lpss-acpi.c22 .clk_rate = 120000000,
31 .clk_rate = 120000000,
43 .clk_rate = 120000000,
49 .clk_rate = 100000000,
60 .clk_rate = 133000000,
72 .clk_rate = 133000000,

Completed in 11 milliseconds

12345678910>>...12