Lines Matching refs:clk_rate
80 * @clk_rate: pwm timer clock rate
85 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
87 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
158 unsigned long clk_rate;
174 clk_rate = clk_get_rate(fclk);
175 if (!clk_rate) {
180 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
198 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
199 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
204 period_ns, clk_rate);
211 duty_ns, clk_rate);
217 duty_ns, period_ns, clk_rate);
224 clk_rate),
226 clk_rate));