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/kernel/linux/linux-5.10/arch/ia64/kernel/
H A Dperfmon_itanium.h12 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
13 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NUL
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H A Dperfmon_generic.h11 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
12 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NUL
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H A Dperfmon_mckinley.h12 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
13 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NUL
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/kernel/linux/linux-6.6/arch/ia64/kernel/
H A Dperfmon_itanium.h12 /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
13 /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NUL
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/kernel/linux/linux-5.10/arch/sparc/include/asm/
H A Dchafsr.h21 #define CHAFSR_TL1 (1UL << 63UL) /* n/a */
26 #define CHPAFSR_DTO (1UL << 59UL) /* ch+ */
31 #define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */
34 #define CHPAFSR_THCE (1UL << 57UL) /* ch+ */
36 #define JPAFSR_JETO (1UL << 57UL) /* j
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/kernel/linux/linux-6.6/arch/sparc/include/asm/
H A Dchafsr.h21 #define CHAFSR_TL1 (1UL << 63UL) /* n/a */
26 #define CHPAFSR_DTO (1UL << 59UL) /* ch+ */
31 #define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */
34 #define CHPAFSR_THCE (1UL << 57UL) /* ch+ */
36 #define JPAFSR_JETO (1UL << 57UL) /* j
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/kernel/linux/linux-5.10/sound/pci/aw2/
H A Dsaa7146.h46 #define ME (1UL << 11)
47 #define LIMIT (1UL << 4)
48 #define PV (1UL << 3)
51 #define PPEF (1UL << 31)
52 #define PABO (1UL << 30)
53 #define IIC_S (1UL << 17)
54 #define IIC_E (1UL << 16)
55 #define A2_in (1UL << 15)
56 #define A2_out (1UL << 14)
57 #define A1_in (1UL << 1
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/kernel/linux/linux-6.6/sound/pci/aw2/
H A Dsaa7146.h46 #define ME (1UL << 11)
47 #define LIMIT (1UL << 4)
48 #define PV (1UL << 3)
51 #define PPEF (1UL << 31)
52 #define PABO (1UL << 30)
53 #define IIC_S (1UL << 17)
54 #define IIC_E (1UL << 16)
55 #define A2_in (1UL << 15)
56 #define A2_out (1UL << 14)
57 #define A1_in (1UL << 1
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/kernel/linux/linux-5.10/arch/sparc/include/uapi/asm/
H A Dpstate.h18 #define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals. */
19 #define PSTATE_MCDE _AC(0x0000000000000800,UL) /* MCD Enable */
20 #define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */
21 #define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/
22 #define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian. */
23 #define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */
24 #define PSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder */
25 #define PSTATE_PSO _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */
26 #define PSTATE_RMO _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
27 #define PSTATE_RED _AC(0x0000000000000020,UL) /* Rese
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/kernel/linux/linux-6.6/arch/sparc/include/uapi/asm/
H A Dpstate.h18 #define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals. */
19 #define PSTATE_MCDE _AC(0x0000000000000800,UL) /* MCD Enable */
20 #define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */
21 #define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/
22 #define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian. */
23 #define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */
24 #define PSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder */
25 #define PSTATE_PSO _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */
26 #define PSTATE_RMO _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
27 #define PSTATE_RED _AC(0x0000000000000020,UL) /* Rese
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/kernel/linux/linux-5.10/drivers/clk/tegra/
H A Dclk-tegra124-dfll-fcpu.c33 [0] = 2014500000UL,
34 [1] = 2320500000UL,
35 [2] = 2116500000UL,
36 [3] = 2524500000UL,
48 { 204000000UL, { 1112619, -29295, 402 } },
49 { 306000000UL, { 1150460, -30585, 402 } },
50 { 408000000UL, { 1190122, -31865, 402 } },
51 { 510000000UL, { 1231606, -33155, 402 } },
52 { 612000000UL, { 1274912, -34435, 402 } },
53 { 714000000UL, { 132004
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/kernel/linux/linux-6.6/drivers/clk/tegra/
H A Dclk-tegra124-dfll-fcpu.c33 [0] = 2014500000UL,
34 [1] = 2320500000UL,
35 [2] = 2116500000UL,
36 [3] = 2524500000UL,
48 { 204000000UL, { 1112619, -29295, 402 } },
49 { 306000000UL, { 1150460, -30585, 402 } },
50 { 408000000UL, { 1190122, -31865, 402 } },
51 { 510000000UL, { 1231606, -33155, 402 } },
52 { 612000000UL, { 1274912, -34435, 402 } },
53 { 714000000UL, { 132004
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/kernel/linux/linux-5.10/drivers/infiniband/hw/hns/
H A Dhns_roce_hw_v1.h209 (((1UL << 2) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S)
213 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQN_S)
217 (((1UL << 17) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S)
221 (((1UL << 4) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S)
225 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_12_CEQN_S)
229 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S)
233 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S)
237 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S)
241 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S)
251 (((1UL << 1
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/kernel/linux/linux-6.6/arch/arm64/include/asm/
H A Dkvm_arm.h17 #define HCR_TID5 (UL(1) << 58)
18 #define HCR_DCT (UL(1) << 57)
20 #define HCR_ATA (UL(1) << HCR_ATA_SHIFT)
21 #define HCR_TTLBOS (UL(1) << 55)
22 #define HCR_TTLBIS (UL(1) << 54)
23 #define HCR_ENSCXT (UL(1) << 53)
24 #define HCR_TOCU (UL(1) << 52)
25 #define HCR_AMVOFFEN (UL(1) << 51)
26 #define HCR_TICAB (UL(1) << 50)
27 #define HCR_TID4 (UL(
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H A Desr.h73 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
77 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
86 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
90 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
92 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
94 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
95 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
96 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
97 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
98 #define ESR_ELx_AET_CE (UL(
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H A Dpgtable-hwdef.h50 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
60 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
70 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
190 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
192 #define TTBR_CNP_BIT (UL(1) << 0)
199 #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
200 #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
203 #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
204 #define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
207 #define TCR_EPD0_MASK (UL(
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/kernel/linux/linux-5.10/arch/arm64/include/asm/
H A Dpgtable-hwdef.h50 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
60 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
70 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
78 #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
173 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
175 #define TTBR_CNP_BIT (UL(1) << 0)
182 #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
183 #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
186 #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
187 #define TCR_T1SZ_MASK (((UL(
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H A Dkvm_arm.h15 #define HCR_ATA (UL(1) << 56)
16 #define HCR_FWB (UL(1) << 46)
17 #define HCR_API (UL(1) << 41)
18 #define HCR_APK (UL(1) << 40)
19 #define HCR_TEA (UL(1) << 37)
20 #define HCR_TERR (UL(1) << 36)
21 #define HCR_TLOR (UL(1) << 35)
22 #define HCR_E2H (UL(1) << 34)
23 #define HCR_ID (UL(1) << 33)
24 #define HCR_CD (UL(
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/kernel/linux/linux-5.10/arch/alpha/include/uapi/asm/
H A Dfpu.h9 #define FPCR_DNOD (1UL<<47) /* denorm INV trap disable */
10 #define FPCR_DNZ (1UL<<48) /* denorms to zero */
11 #define FPCR_INVD (1UL<<49) /* invalid op disable (opt.) */
12 #define FPCR_DZED (1UL<<50) /* division by zero disable (opt.) */
13 #define FPCR_OVFD (1UL<<51) /* overflow disable (optional) */
14 #define FPCR_INV (1UL<<52) /* invalid operation */
15 #define FPCR_DZE (1UL<<53) /* division by zero */
16 #define FPCR_OVF (1UL<<54) /* overflow */
17 #define FPCR_UNF (1UL<<55) /* underflow */
18 #define FPCR_INE (1UL<<5
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/kernel/linux/linux-6.6/arch/alpha/include/uapi/asm/
H A Dfpu.h9 #define FPCR_DNOD (1UL<<47) /* denorm INV trap disable */
10 #define FPCR_DNZ (1UL<<48) /* denorms to zero */
11 #define FPCR_INVD (1UL<<49) /* invalid op disable (opt.) */
12 #define FPCR_DZED (1UL<<50) /* division by zero disable (opt.) */
13 #define FPCR_OVFD (1UL<<51) /* overflow disable (optional) */
14 #define FPCR_INV (1UL<<52) /* invalid operation */
15 #define FPCR_DZE (1UL<<53) /* division by zero */
16 #define FPCR_OVF (1UL<<54) /* overflow */
17 #define FPCR_UNF (1UL<<55) /* underflow */
18 #define FPCR_INE (1UL<<5
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/kernel/linux/linux-5.10/include/uapi/rdma/hfi/
H A Dhfi1_user.h93 #define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */
94 #define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */
95 #define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */
96 #define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */
97 #define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */
98 #define HFI1_CAP_TID_RDMA (1UL << 5) /* Enable TID RDMA operations */
99 #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */
100 #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/
101 #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */
102 #define HFI1_CAP_NODROP_EGR_FULL (1UL <<
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/kernel/linux/linux-6.6/include/uapi/rdma/hfi/
H A Dhfi1_user.h93 #define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */
94 #define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */
95 #define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */
96 #define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */
97 #define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */
98 #define HFI1_CAP_TID_RDMA (1UL << 5) /* Enable TID RDMA operations */
99 #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */
100 #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/
101 #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */
102 #define HFI1_CAP_NODROP_EGR_FULL (1UL <<
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/kernel/linux/patches/linux-5.10/prebuilts/usr/include/rdma/hfi/
H A Dhfi1_user.h26 #define HFI1_CAP_DMA_RTAIL (1UL << 0)
27 #define HFI1_CAP_SDMA (1UL << 1)
28 #define HFI1_CAP_SDMA_AHG (1UL << 2)
29 #define HFI1_CAP_EXTENDED_PSN (1UL << 3)
30 #define HFI1_CAP_HDRSUPP (1UL << 4)
31 #define HFI1_CAP_TID_RDMA (1UL << 5)
32 #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6)
33 #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7)
34 #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8)
35 #define HFI1_CAP_NODROP_EGR_FULL (1UL <<
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/kernel/linux/patches/linux-6.6/prebuilts/usr/include/rdma/hfi/
H A Dhfi1_user.h26 #define HFI1_CAP_DMA_RTAIL (1UL << 0)
27 #define HFI1_CAP_SDMA (1UL << 1)
28 #define HFI1_CAP_SDMA_AHG (1UL << 2)
29 #define HFI1_CAP_EXTENDED_PSN (1UL << 3)
30 #define HFI1_CAP_HDRSUPP (1UL << 4)
31 #define HFI1_CAP_TID_RDMA (1UL << 5)
32 #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6)
33 #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7)
34 #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8)
35 #define HFI1_CAP_NODROP_EGR_FULL (1UL <<
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/kernel/linux/linux-6.6/include/linux/
H A Dnfs4.h394 #define FATTR4_WORD0_SUPPORTED_ATTRS (1UL << 0)
395 #define FATTR4_WORD0_TYPE (1UL << 1)
396 #define FATTR4_WORD0_FH_EXPIRE_TYPE (1UL << 2)
397 #define FATTR4_WORD0_CHANGE (1UL << 3)
398 #define FATTR4_WORD0_SIZE (1UL << 4)
399 #define FATTR4_WORD0_LINK_SUPPORT (1UL << 5)
400 #define FATTR4_WORD0_SYMLINK_SUPPORT (1UL << 6)
401 #define FATTR4_WORD0_NAMED_ATTR (1UL << 7)
402 #define FATTR4_WORD0_FSID (1UL << 8)
403 #define FATTR4_WORD0_UNIQUE_HANDLES (1UL <<
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12345678910>>...151