Lines Matching refs:UL
73 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
77 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
86 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
90 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
92 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
94 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
95 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
96 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
97 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
98 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
102 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
104 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
106 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
108 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
132 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
134 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
136 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
138 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
140 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
142 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
144 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
148 #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT)
150 #define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT)
152 #define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT)
154 #define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT)
156 #define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT)
161 #define ESR_ELx_CV (UL(1) << 24)
163 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
164 #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
165 #define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
166 #define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
167 #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
168 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
169 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
170 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
172 #define DISR_EL1_IDS (UL(1) << 24)
190 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
196 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
198 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
200 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
202 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
204 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
206 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
303 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
313 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
315 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
317 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
319 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
321 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
339 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
342 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
345 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
347 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
377 #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)
378 #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18)
379 #define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17)
380 #define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16)
381 #define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10)
382 #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
383 #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)