Lines Matching refs:UL
50 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
60 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
70 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
190 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
192 #define TTBR_CNP_BIT (UL(1) << 0)
199 #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
200 #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
203 #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
204 #define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
207 #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
209 #define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
210 #define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
211 #define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
212 #define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
213 #define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
216 #define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT)
218 #define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
219 #define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
220 #define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
221 #define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT)
222 #define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT)
232 #define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
233 #define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
234 #define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
235 #define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
236 #define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
239 #define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT)
240 #define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT)
241 #define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
242 #define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT)
243 #define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT)
252 #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
253 #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
256 #define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT)
257 #define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT)
261 #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
262 #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
263 #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
264 #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
267 #define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
268 #define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
269 #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
270 #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
273 #define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
274 #define TCR_A1 (UL(1) << 22)
275 #define TCR_ASID16 (UL(1) << 36)
276 #define TCR_TBI0 (UL(1) << 37)
277 #define TCR_TBI1 (UL(1) << 38)
278 #define TCR_HA (UL(1) << 39)
279 #define TCR_HD (UL(1) << 40)
280 #define TCR_TBID1 (UL(1) << 52)
281 #define TCR_NFD0 (UL(1) << 53)
282 #define TCR_NFD1 (UL(1) << 54)
283 #define TCR_E0PD0 (UL(1) << 55)
284 #define TCR_E0PD1 (UL(1) << 56)
285 #define TCR_TCMA0 (UL(1) << 57)
286 #define TCR_TCMA1 (UL(1) << 58)
300 #define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \
301 (UL(1) << (48 - PGDIR_SHIFT))) * 8)