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Searched refs:PACKET3 (Results 1 - 25 of 62) sorted by relevance

123

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c1807 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1829 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1840 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1843 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1852 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v6_0_ring_emit_fence()
1872 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_ib()
1877 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v6_0_ring_emit_ib()
1879 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v6_0_ring_emit_ib()
1922 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib()
2032 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZ in gfx_v6_0_cp_gfx_start()
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H A Dgfx_v7_0.c2102 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2149 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2162 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2166 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2188 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2200 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2229 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in gfx_v7_0_ring_emit_fence_compute()
2266 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_ib_gfx()
2271 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v7_0_ring_emit_ib_gfx()
2273 header = PACKET3(PACKET3_INDIRECT_BUFFE in gfx_v7_0_ring_emit_ib_gfx()
[all...]
H A Dgfx_v8_0.c853 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
896 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v8_0_ring_test_ib()
1255 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1258 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_get_csb_buffer()
1266 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v8_0_get_csb_buffer()
1277 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_get_csb_buffer()
1283 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1286 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_get_csb_buffer()
1575 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1581 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_RE in gfx_v8_0_do_edc_gpr_workarounds()
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H A Dgfx_v9_0.c815 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
838 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_0_kiq_map_queues()
868 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx_v9_0_kiq_unmap_queues()
895 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); in gfx_v9_0_kiq_query_status()
914 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in gfx_v9_0_kiq_invalidate_tlbs()
1008 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg()
1022 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
1056 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v9_0_ring_test_ring()
1099 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v9_0_ring_test_ib()
1724 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNT in gfx_v9_0_get_csb_buffer()
[all...]
H A Dsi_enums.h168 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
171 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dnvd.h48 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
52 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dsoc15d.h50 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dcikd.h223 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
227 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c1780 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1799 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1810 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1813 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1822 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v6_0_ring_emit_fence()
1842 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_ib()
1847 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v6_0_ring_emit_ib()
1849 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v6_0_ring_emit_ib()
1887 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib()
1995 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZ in gfx_v6_0_cp_gfx_start()
[all...]
H A Dgfx_v7_0.c2039 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2082 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2095 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2099 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2123 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2135 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2166 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in gfx_v7_0_ring_emit_fence_compute()
2205 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_ib_gfx()
2210 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v7_0_ring_emit_ib_gfx()
2212 header = PACKET3(PACKET3_INDIRECT_BUFFE in gfx_v7_0_ring_emit_ib_gfx()
[all...]
H A Dgfx_v8_0.c850 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
891 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v8_0_ring_test_ib()
1222 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1225 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_get_csb_buffer()
1233 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v8_0_get_csb_buffer()
1244 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_get_csb_buffer()
1250 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1253 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_get_csb_buffer()
1543 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1549 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_RE in gfx_v8_0_do_edc_gpr_workarounds()
[all...]
H A Dgfx_v9_0.c771 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
793 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_0_kiq_map_queues()
823 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx_v9_0_kiq_unmap_queues()
851 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); in gfx_v9_0_kiq_query_status()
870 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in gfx_v9_0_kiq_invalidate_tlbs()
963 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg()
977 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
1007 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v9_0_ring_test_ring()
1047 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v9_0_ring_test_ib()
1449 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNT in gfx_v9_0_get_csb_buffer()
[all...]
H A Dgfx_v11_0.c137 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx11_kiq_set_resources()
172 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx11_kiq_map_queues()
204 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx11_kiq_unmap_queues()
231 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); in gfx11_kiq_query_status()
291 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v11_0_write_data_to_reg()
304 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v11_0_wait_reg_mem()
340 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v11_0_ring_test_ring()
408 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v11_0_ring_test_ib()
626 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_get_csb_buffer()
629 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTRO in gfx_v11_0_get_csb_buffer()
[all...]
H A Dsi_enums.h168 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
171 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dnvd.h48 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
52 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dsoc15d.h50 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dgfx_v9_4_3.c63 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_4_3_kiq_set_resources()
86 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_4_3_kiq_map_queues()
116 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); in gfx_v9_4_3_kiq_unmap_queues()
143 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); in gfx_v9_4_3_kiq_query_status()
162 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in gfx_v9_4_3_kiq_invalidate_tlbs()
216 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_4_3_write_data_to_reg()
230 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_4_3_wait_reg_mem()
264 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v9_4_3_ring_test_ring()
304 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v9_4_3_ring_test_ib()
2526 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_RE in gfx_v9_4_3_ring_emit_ib_compute()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dni.c1411 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1417 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1433 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1438 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
1444 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in cayman_ring_ib_execute()
1454 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute()
1560 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start()
1578 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1584 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1588 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STAT in cayman_cp_start()
[all...]
H A Dsi.c3381 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_fence_ring_emit()
3384 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit()
3393 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in si_fence_ring_emit()
3412 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in si_ring_ib_execute()
3415 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in si_ring_ib_execute()
3420 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3426 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_ring_ib_execute()
3433 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in si_ring_ib_execute()
3447 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3450 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYN in si_ring_ib_execute()
[all...]
H A Dcik.c3474 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3530 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3559 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3571 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3598 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
3629 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
3635 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
3690 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
3737 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
3740 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONS in cik_ring_ib_execute()
[all...]
H A Dr600.c2696 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2841 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2879 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2885 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in r600_fence_ring_emit()
2893 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2898 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2901 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2905 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2936 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2943 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_M in r600_semaphore_ring_emit()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dni.c1398 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1404 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1420 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1425 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
1431 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in cayman_ring_ib_execute()
1441 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute()
1547 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start()
1565 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1571 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1575 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STAT in cayman_cp_start()
[all...]
H A Dsi.c3376 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_fence_ring_emit()
3379 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit()
3388 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in si_fence_ring_emit()
3407 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in si_ring_ib_execute()
3410 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in si_ring_ib_execute()
3415 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3421 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_ring_ib_execute()
3428 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in si_ring_ib_execute()
3442 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3445 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYN in si_ring_ib_execute()
[all...]
H A Dcik.c3464 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3520 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3549 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3561 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3588 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
3619 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
3625 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
3680 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
3727 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
3730 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONS in cik_ring_ib_execute()
[all...]
H A Dr600.c2697 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2842 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2880 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2886 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in r600_fence_ring_emit()
2894 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2899 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2902 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2906 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2937 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2944 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_M in r600_semaphore_ring_emit()
[all...]

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