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Searched refs:HIWORD_UPDATE (Results 1 - 25 of 60) sorted by relevance

123

/kernel/linux/linux-6.6/sound/soc/rockchip/
H A Drockchip_i2s_tdm.h288 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) macro
291 #define PX30_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 13, 12)
292 #define PX30_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 13, 12)
293 #define PX30_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5)
294 #define PX30_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5)
303 #define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2)
304 #define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2)
305 #define RK1808_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 1, 0)
306 #define RK1808_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 1, 0)
315 #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(
[all...]
/kernel/linux/linux-6.6/drivers/soc/rockchip/
H A Dgrf.c14 #define HIWORD_UPDATE(val, mask, shift) \ macro
35 { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
46 { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
57 { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
69 { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
70 { "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
81 { "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
92 { "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
103 { "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
114 { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(
[all...]
/kernel/linux/linux-5.10/drivers/soc/rockchip/
H A Dgrf.c14 #define HIWORD_UPDATE(val, mask, shift) \ macro
35 { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
46 { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
57 { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
69 { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
70 { "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
81 { "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
92 { "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
103 { "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
/kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/
H A Drockchip_lvds.h109 #define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) macro
112 #define PX30_LVDS_TIE_CLKS(val) HIWORD_UPDATE(val, 8, 8)
113 #define PX30_LVDS_INVERT_CLKS(val) HIWORD_UPDATE(val, 9, 9)
114 #define PX30_LVDS_INVERT_DCLK(val) HIWORD_UPDATE(val, 5, 5)
117 #define PX30_LVDS_FORMAT(val) HIWORD_UPDATE(val, 14, 13)
118 #define PX30_LVDS_MODE_EN(val) HIWORD_UPDATE(val, 12, 12)
119 #define PX30_LVDS_MSBSEL(val) HIWORD_UPDATE(val, 11, 11)
120 #define PX30_LVDS_P2S_EN(val) HIWORD_UPDATE(val, 6, 6)
121 #define PX30_LVDS_VOP_SEL(val) HIWORD_UPDATE(val, 1, 1)
H A Ddw_hdmi-rockchip.c53 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
338 HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL | in dw_hdmi_rk3228_setup_hpd()
345 HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK, in dw_hdmi_rk3228_setup_hpd()
360 HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V, in dw_hdmi_rk3328_read_hpd()
365 HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V | in dw_hdmi_rk3328_read_hpd()
379 HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V | in dw_hdmi_rk3328_setup_hpd()
384 HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF | in dw_hdmi_rk3328_setup_hpd()
389 HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK, in dw_hdmi_rk3328_setup_hpd()
419 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
420 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SE
[all...]
H A Ddw-mipi-dsi-rockchip.c175 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
1152 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1153 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1157 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1170 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1171 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1178 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1179 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1190 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1191 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SE
[all...]
H A Danalogix_dp-rockchip.c39 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
453 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
454 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
460 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
461 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
/kernel/linux/linux-6.6/drivers/gpu/drm/rockchip/
H A Drockchip_lvds.h109 #define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) macro
112 #define PX30_LVDS_TIE_CLKS(val) HIWORD_UPDATE(val, 8, 8)
113 #define PX30_LVDS_INVERT_CLKS(val) HIWORD_UPDATE(val, 9, 9)
114 #define PX30_LVDS_INVERT_DCLK(val) HIWORD_UPDATE(val, 5, 5)
117 #define PX30_LVDS_FORMAT(val) HIWORD_UPDATE(val, 14, 13)
118 #define PX30_LVDS_MODE_EN(val) HIWORD_UPDATE(val, 12, 12)
119 #define PX30_LVDS_MSBSEL(val) HIWORD_UPDATE(val, 11, 11)
120 #define PX30_LVDS_P2S_EN(val) HIWORD_UPDATE(val, 6, 6)
121 #define PX30_LVDS_VOP_SEL(val) HIWORD_UPDATE(val, 1, 1)
H A Ddw-mipi-dsi-rockchip.c201 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
1479 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1480 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1484 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1497 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1498 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1505 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1506 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1522 HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0)); in rk3399_dphy_tx1rx1_init()
1524 HIWORD_UPDATE( in rk3399_dphy_tx1rx1_init()
[all...]
H A Ddw_hdmi-rockchip.c58 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
384 HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL | in dw_hdmi_rk3228_setup_hpd()
391 HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK, in dw_hdmi_rk3228_setup_hpd()
406 HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V, in dw_hdmi_rk3328_read_hpd()
411 HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V | in dw_hdmi_rk3328_read_hpd()
425 HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V | in dw_hdmi_rk3328_setup_hpd()
430 HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF | in dw_hdmi_rk3328_setup_hpd()
435 HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK, in dw_hdmi_rk3328_setup_hpd()
465 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
466 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SE
[all...]
H A Danalogix_dp-rockchip.c40 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
462 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
463 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
469 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
470 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
/kernel/linux/linux-6.6/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c23 #define HIWORD_UPDATE(val, mask, shift) \ macro
108 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF, in rockchip_emmc_phy_power()
113 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE, in rockchip_emmc_phy_power()
166 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON, in rockchip_emmc_phy_power()
189 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK, in rockchip_emmc_phy_power()
195 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, in rockchip_emmc_phy_power()
290 HIWORD_UPDATE(rk_phy->drive_impedance, in rockchip_emmc_phy_power_on()
297 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, in rockchip_emmc_phy_power_on()
304 HIWORD_UPDATE(rk_phy->output_tapdelay_select, in rockchip_emmc_phy_power_on()
311 HIWORD_UPDATE(rk_ph in rockchip_emmc_phy_power_on()
[all...]
H A Dphy-rockchip-pcie.c26 #define HIWORD_UPDATE(val, mask, shift) \ macro
104 HIWORD_UPDATE(data, in phy_wr_cfg()
107 HIWORD_UPDATE(addr, in phy_wr_cfg()
112 HIWORD_UPDATE(PHY_CFG_WR_ENABLE, in phy_wr_cfg()
117 HIWORD_UPDATE(PHY_CFG_WR_DISABLE, in phy_wr_cfg()
132 HIWORD_UPDATE(PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
153 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
180 HIWORD_UPDATE(PHY_CFG_PLL_LOCK, in rockchip_pcie_phy_power_on()
186 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_on()
237 HIWORD_UPDATE(PHY_CFG_PLL_LOC in rockchip_pcie_phy_power_on()
[all...]
H A Dphy-rockchip-usb.c28 #define HIWORD_UPDATE(val, mask) \ macro
83 u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ); in rockchip_usb_phy_power()
336 val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N in rockchip_init_usb_uart_common()
346 val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL, in rockchip_init_usb_uart_common()
352 val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING in rockchip_init_usb_uart_common()
384 val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL in rk3188_init_usb_uart()
434 val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL in rk3288_init_usb_uart()
/kernel/linux/linux-5.10/drivers/clk/rockchip/
H A Dclk-pll.c214 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
216 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
220 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
222 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, in rockchip_rk3036_pll_set_params()
224 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, in rockchip_rk3036_pll_set_params()
272 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), in rockchip_rk3036_pll_enable()
283 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, in rockchip_rk3036_pll_disable()
447 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), in rockchip_rk3066_pll_set_params()
451 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_params()
453 HIWORD_UPDATE(rat in rockchip_rk3066_pll_set_params()
[all...]
H A Dclk-cpu.c165 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask, in rockchip_cpuclk_pre_rate_change()
167 HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
173 writel(HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
209 writel(HIWORD_UPDATE(0, reg_data->div_core_mask, in rockchip_cpuclk_post_rate_change()
211 HIWORD_UPDATE(reg_data->mux_core_main, in rockchip_cpuclk_post_rate_change()
/kernel/linux/linux-6.6/drivers/clk/rockchip/
H A Dclk-pll.c214 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
216 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
220 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
222 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, in rockchip_rk3036_pll_set_params()
224 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, in rockchip_rk3036_pll_set_params()
272 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), in rockchip_rk3036_pll_enable()
283 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, in rockchip_rk3036_pll_disable()
447 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), in rockchip_rk3066_pll_set_params()
451 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_params()
453 HIWORD_UPDATE(rat in rockchip_rk3066_pll_set_params()
[all...]
H A Dclk-cpu.c199 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i], in rockchip_cpuclk_pre_rate_change()
209 writel(HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
214 writel(HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
251 writel(HIWORD_UPDATE(reg_data->mux_core_main, in rockchip_cpuclk_post_rate_change()
256 writel(HIWORD_UPDATE(reg_data->mux_core_main, in rockchip_cpuclk_post_rate_change()
265 writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i], in rockchip_cpuclk_post_rate_change()
/kernel/linux/linux-5.10/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c23 #define HIWORD_UPDATE(val, mask, shift) \ macro
100 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF, in rockchip_emmc_phy_power()
105 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE, in rockchip_emmc_phy_power()
158 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON, in rockchip_emmc_phy_power()
181 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK, in rockchip_emmc_phy_power()
187 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, in rockchip_emmc_phy_power()
282 HIWORD_UPDATE(rk_phy->drive_impedance, in rockchip_emmc_phy_power_on()
289 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, in rockchip_emmc_phy_power_on()
296 HIWORD_UPDATE(4, in rockchip_emmc_phy_power_on()
H A Dphy-rockchip-pcie.c26 #define HIWORD_UPDATE(val, mask, shift) \ macro
104 HIWORD_UPDATE(data, in phy_wr_cfg()
107 HIWORD_UPDATE(addr, in phy_wr_cfg()
112 HIWORD_UPDATE(PHY_CFG_WR_ENABLE, in phy_wr_cfg()
117 HIWORD_UPDATE(PHY_CFG_WR_DISABLE, in phy_wr_cfg()
128 HIWORD_UPDATE(addr, in phy_rd_cfg()
147 HIWORD_UPDATE(PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
168 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
195 HIWORD_UPDATE(PHY_CFG_PLL_LOCK, in rockchip_pcie_phy_power_on()
201 HIWORD_UPDATE(!PHY_LANE_IDLE_OF in rockchip_pcie_phy_power_on()
[all...]
H A Dphy-rockchip-usb.c28 #define HIWORD_UPDATE(val, mask) \ macro
83 u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ); in rockchip_usb_phy_power()
336 val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N in rockchip_init_usb_uart_common()
346 val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL, in rockchip_init_usb_uart_common()
352 val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING in rockchip_init_usb_uart_common()
384 val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL in rk3188_init_usb_uart()
434 val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL in rk3288_init_usb_uart()
/kernel/linux/linux-5.10/drivers/pci/controller/
H A Dpcie-rockchip.h21 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) macro
22 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
32 #define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
35 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
37 #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
38 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
42 #define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0)
44 #define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0)
/kernel/linux/linux-6.6/drivers/pci/controller/
H A Dpcie-rockchip.h22 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) macro
23 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
33 #define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
36 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
38 #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
39 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
43 #define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0)
45 #define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0)
/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-rk.c68 #define HIWORD_UPDATE(val, mask, shift) \ macro
144 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
145 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
253 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
254 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
399 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
400 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
491 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
492 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
643 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(va
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-rk.c86 #define HIWORD_UPDATE(val, mask, shift) \ macro
163 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
164 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
272 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
273 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
418 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
419 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
558 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
559 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
710 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(va
[all...]

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