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Searched refs:ENABLE_INTR (Results 1 - 25 of 32) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Diceland_ih.c65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in iceland_ih_enable_interrupts()
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in iceland_ih_disable_interrupts()
H A Dcz_ih.c65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in cz_ih_enable_interrupts()
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in cz_ih_disable_interrupts()
H A Dtonga_ih.c65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts()
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts()
H A Dsi_ih.c40 ih_cntl |= ENABLE_INTR; in si_ih_enable_interrupts()
53 ih_cntl &= ~ENABLE_INTR; in si_ih_disable_interrupts()
H A Dvega10_ih.c52 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in vega10_ih_enable_interrupts()
108 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in vega10_ih_disable_interrupts()
H A Dnavi10_ih.c96 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in navi10_ih_enable_interrupts()
153 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in navi10_ih_disable_interrupts()
H A Dsid.h670 # define ENABLE_INTR (1 << 0) macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Diceland_ih.c65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in iceland_ih_enable_interrupts()
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in iceland_ih_disable_interrupts()
H A Dcz_ih.c65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in cz_ih_enable_interrupts()
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in cz_ih_disable_interrupts()
H A Dsi_ih.c40 ih_cntl |= ENABLE_INTR; in si_ih_enable_interrupts()
53 ih_cntl &= ~ENABLE_INTR; in si_ih_disable_interrupts()
H A Dtonga_ih.c65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts()
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts()
H A Dvega10_ih.c110 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in vega10_ih_toggle_ring_interrupts()
H A Dih_v6_0.c140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in ih_v6_0_toggle_ring_interrupts()
H A Dih_v6_1.c140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in ih_v6_1_toggle_ring_interrupts()
H A Dnavi10_ih.c166 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in navi10_ih_toggle_ring_interrupts()
H A Dvega20_ih.c119 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in vega20_ih_toggle_ring_interrupts()
H A Dsid.h670 # define ENABLE_INTR (1 << 0) macro
/kernel/linux/linux-5.10/drivers/irqchip/
H A Dqcom-pdc.c26 #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) macro
86 enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); in pdc_enable_intr()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dcikd.h817 # define ENABLE_INTR (1 << 0) macro
H A Dsid.h667 # define ENABLE_INTR (1 << 0) macro
H A Dr600.c3598 ih_cntl |= ENABLE_INTR; in r600_enable_interrupts()
3611 ih_cntl &= ~ENABLE_INTR; in r600_disable_interrupts()
H A Devergreend.h1236 # define ENABLE_INTR (1 << 0) macro
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dcikd.h817 # define ENABLE_INTR (1 << 0) macro
H A Dsid.h667 # define ENABLE_INTR (1 << 0) macro
H A Dr600.c3595 ih_cntl |= ENABLE_INTR; in r600_enable_interrupts()
3608 ih_cntl &= ~ENABLE_INTR; in r600_disable_interrupts()

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