Searched refs:DPLL_CTL (Results 1 - 8 of 8) sorted by relevance
| /kernel/linux/linux-5.10/arch/arm/mach-omap1/ |
| H A D | sram.S | 25 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
27 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
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| H A D | reset.c | 34 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); in omap1_restart()
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| H A D | clock_data.c | 817 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", in omap1_clk_init()
818 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), in omap1_clk_init()
832 unsigned pll_ctl_val = omap_readw(DPLL_CTL); in omap1_clk_init()
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| /kernel/linux/linux-6.6/arch/arm/mach-omap1/ |
| H A D | sram.S | 25 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
27 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
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| H A D | reset.c | 33 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); in omap1_restart()
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| H A D | clock_data.c | 731 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", in omap1_clk_init()
732 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), in omap1_clk_init()
746 unsigned pll_ctl_val = omap_readw(DPLL_CTL); in omap1_clk_init()
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| /kernel/linux/linux-6.6/include/linux/soc/ti/ |
| H A D | omap1-io.h | 87 #define DPLL_CTL (0xfffecf00) macro
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| /kernel/linux/linux-5.10/arch/arm/mach-omap1/include/mach/ |
| H A D | hardware.h | 123 #define DPLL_CTL (0xfffecf00) macro
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