Searched refs:DAVINCI_MMCIM (Results 1 - 2 of 2) sorted by relevance
| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| H A D | davinci_mmc.c | 37 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ macro
82 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
381 writel(im_val, host->base + DAVINCI_MMCIM); in mmc_davinci_start_command()
794 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_xfer_done()
822 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_cmd_done()
877 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
901 im_val = readl(host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
902 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
917 writel(im_val, host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
1368 writel(0, host->base + DAVINCI_MMCIM); in davinci_mmcsd_suspend()
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| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| H A D | davinci_mmc.c | 36 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ macro
81 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
380 writel(im_val, host->base + DAVINCI_MMCIM); in mmc_davinci_start_command()
793 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_xfer_done()
821 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_cmd_done()
876 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
900 im_val = readl(host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
901 writel(0, host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
916 writel(im_val, host->base + DAVINCI_MMCIM); in mmc_davinci_irq()
1363 writel(0, host->base + DAVINCI_MMCIM); in davinci_mmcsd_suspend()
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