Lines Matching refs:DAVINCI_MMCIM
36 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */
81 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
380 writel(im_val, host->base + DAVINCI_MMCIM);
793 writel(0, host->base + DAVINCI_MMCIM);
821 writel(0, host->base + DAVINCI_MMCIM);
876 writel(0, host->base + DAVINCI_MMCIM);
900 im_val = readl(host->base + DAVINCI_MMCIM);
901 writel(0, host->base + DAVINCI_MMCIM);
916 writel(im_val, host->base + DAVINCI_MMCIM);
1363 writel(0, host->base + DAVINCI_MMCIM);