Lines Matching refs:DAVINCI_MMCIM
37 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */
82 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
381 writel(im_val, host->base + DAVINCI_MMCIM);
794 writel(0, host->base + DAVINCI_MMCIM);
822 writel(0, host->base + DAVINCI_MMCIM);
877 writel(0, host->base + DAVINCI_MMCIM);
901 im_val = readl(host->base + DAVINCI_MMCIM);
902 writel(0, host->base + DAVINCI_MMCIM);
917 writel(im_val, host->base + DAVINCI_MMCIM);
1368 writel(0, host->base + DAVINCI_MMCIM);