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/kernel/linux/linux-5.10/drivers/scsi/
H A Dqla1280.h18 #define BIT_1 0x2 macro
121 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
135 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
142 #define PCI_INT BIT_1 /* PCI interrupt */
147 #define NV_SELECT BIT_1
159 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
176 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
568 #define RF_FULL BIT_1 /* Full */
966 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
H A Dqla1280.c1124 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1690 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1704 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1708 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1832 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_start_firmware()
1842 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_start_firmware()
1909 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1923 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2143 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_config_bus()
2216 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_ in qla1280_nvram_config()
[all...]
/kernel/linux/linux-6.6/drivers/scsi/
H A Dqla1280.h18 #define BIT_1 0x2 macro
120 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
134 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
141 #define PCI_INT BIT_1 /* PCI interrupt */
146 #define NV_SELECT BIT_1
158 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
175 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
567 #define RF_FULL BIT_1 /* Full */
965 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
H A Dqla1280.c1114 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1680 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1694 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1698 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1822 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_start_firmware()
1832 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_start_firmware()
1899 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1913 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2133 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_config_bus()
2206 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_ in qla1280_nvram_config()
[all...]
/kernel/linux/linux-6.6/drivers/scsi/qla2xxx/
H A Dqla_edif.h20 #define EDIF_SA_CTL_FLG_DEL BIT_1
80 #define SA_FLAG_TX BIT_1 // 1=tx, 0=rx
H A Dqla_fw.h30 #define PDO_FORCE_ADISC BIT_1
45 #define PDF_HARD_ADDR BIT_1
457 #define BD_READ_DATA BIT_1
498 #define CF_READ_DATA BIT_1
540 #define TMF_READ_DATA BIT_1
974 #define TCF_TARGET_RESET BIT_1
1001 #define AOF_NO_RRQ BIT_1 /* Do not send RRQ. */
1195 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1265 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1273 #define GPEX_ENABLE (BIT_1|BIT_
[all...]
H A Dqla_def.h108 #define BIT_1 0x2 macro
230 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
250 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
416 #define SRB_GOT_BUF BIT_1
534 #define SRB_LOGIN_COND_PLOGI BIT_1
584 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
824 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
842 #define NVR_SELECT BIT_1
1099 #define MBX_DMA_OUT BIT_1
1112 #define MBX_DMA_OUT BIT_1
[all...]
H A Dqla_target.h225 #define ATIO_EXEC_READ BIT_1
422 #define EF_NEW_SA BIT_1
483 #define CTIO7_FLAGS_DATA_IN BIT_1 /* data to initiator */
841 TRC_DO_WORK = BIT_1,
967 #define QLA24XX_MGMT_ABORT_IO_ATTR_VALID BIT_1
H A Dqla_nvme.h65 #define CF_READ_DATA BIT_1
H A Dqla_tmpl.h61 #define CAPTURE_FLAG_PHYS_VIRT BIT_1
H A Dqla_init.c4471 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4475 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4485 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
4486 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
4491 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); in qla2x00_update_fw_options()
4493 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4503 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
4504 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
4815 mid_init_cb->options = cpu_to_le16(BIT_1); in qla2x00_init_rings()
5246 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
[all...]
H A Dqla_inline.h387 RESOURCE_EXCH = BIT_1, /* exchange */
H A Dqla_mbx.c794 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1); in qla2x00_execute_fw()
801 (BIT_0 | BIT_1 | BIT_2); in qla2x00_execute_fw()
1896 mcp->mb[1] |= BIT_1; in qla2x00_init_firmware()
2399 mcp->mb[1] = BIT_1; in qla2x00_lip_reset()
2532 if (opt & BIT_1) in qla24xx_login_fabric()
2592 mb[1] |= BIT_1; in qla24xx_login_fabric()
2601 mb[10] |= BIT_1; /* Class 3. */ in qla24xx_login_fabric()
3137 * BIT_1 = mailbox error.
4338 rval = BIT_1; in qla2x00_send_change_request()
4341 rval = BIT_1; in qla2x00_send_change_request()
[all...]
/kernel/linux/linux-5.10/drivers/scsi/qla2xxx/
H A Dqla_fw.h30 #define PDO_FORCE_ADISC BIT_1
45 #define PDF_HARD_ADDR BIT_1
456 #define BD_READ_DATA BIT_1
494 #define CF_READ_DATA BIT_1
536 #define TMF_READ_DATA BIT_1
965 #define TCF_TARGET_RESET BIT_1
1167 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1237 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1245 #define GPEX_ENABLE (BIT_1|BIT_0)
1368 #define MDBS_ID_ACQUIRED BIT_1
[all...]
H A Dqla_def.h82 #define BIT_1 0x2 macro
204 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
224 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
482 #define SRB_LOGIN_COND_PLOGI BIT_1
527 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
714 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
732 #define NVR_SELECT BIT_1
989 #define MBX_DMA_OUT BIT_1
1002 #define MBX_DMA_OUT BIT_1
1124 #define FO1_AE_ALL_LIP_RESET BIT_1
[all...]
H A Dqla_nvme.h60 #define CF_READ_DATA BIT_1
H A Dqla_target.h224 #define ATIO_EXEC_READ BIT_1
469 #define CTIO7_FLAGS_DATA_IN BIT_1 /* data to initiator */
830 TRC_DO_WORK = BIT_1,
956 #define QLA24XX_MGMT_ABORT_IO_ATTR_VALID BIT_1
H A Dqla_tmpl.h61 #define CAPTURE_FLAG_PHYS_VIRT BIT_1
H A Dqla_init.c4001 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4005 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4015 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
4016 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
4021 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); in qla2x00_update_fw_options()
4023 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4033 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
4034 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
4327 mid_init_cb->options = cpu_to_le16(BIT_1); in qla2x00_init_rings()
4751 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
[all...]
H A Dqla_mbx.c758 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1); in qla2x00_execute_fw()
765 (BIT_0 | BIT_1 | BIT_2); in qla2x00_execute_fw()
1846 mcp->mb[1] |= BIT_1; in qla2x00_init_firmware()
2346 mcp->mb[1] = BIT_1; in qla2x00_lip_reset()
2479 if (opt & BIT_1) in qla24xx_login_fabric()
2539 mb[1] |= BIT_1; in qla24xx_login_fabric()
2548 mb[10] |= BIT_1; /* Class 3. */ in qla24xx_login_fabric()
3084 * BIT_1 = mailbox error.
4266 rval = BIT_1; in qla2x00_send_change_request()
4269 rval = BIT_1; in qla2x00_send_change_request()
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hw.h140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
H A Dqlcnic_hdr.h196 #define BIT_1 0x2 macro
493 #define TA_CTL_ENABLE BIT_1
H A Dqlcnic_minidump.c24 #define QLCNIC_DUMP_RWCRB BIT_1
753 if (dma_sts & BIT_1) in qlcnic_start_pex_dma()
/kernel/linux/linux-6.6/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hw.h140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
H A Dqlcnic_hdr.h196 #define BIT_1 0x2 macro
493 #define TA_CTL_ENABLE BIT_1

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