Lines Matching refs:BIT_1
1114 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0;
1680 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb);
1694 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1698 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1822 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
1832 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
1899 BIT_3 | BIT_2 | BIT_1 | BIT_0,
1913 BIT_3 | BIT_2 | BIT_1 | BIT_0,
2133 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
2206 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
2218 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
2224 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2232 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2241 BIT_1 | BIT_0, &mb[0]);
2247 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2261 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2265 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2269 mb[1] = BIT_1; /* Data DMA Channel Burst Enable */
2270 mb[2] = BIT_1; /* Command DMA Channel Burst Enable */
2271 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2275 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2281 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2553 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2607 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
3696 else if (pkt->entry_status & BIT_1)
3716 } else if (pkt->entry_status & BIT_1) { /* FULL flag */
3893 qla1280_mailbox_command(ha, BIT_6 | BIT_3 | BIT_2 | BIT_1 | BIT_0,