Lines Matching refs:BIT_1
1124 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0;
1690 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb);
1704 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1708 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1832 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
1842 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
1909 BIT_3 | BIT_2 | BIT_1 | BIT_0,
1923 BIT_3 | BIT_2 | BIT_1 | BIT_0,
2143 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
2216 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
2228 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
2234 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2242 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2251 BIT_1 | BIT_0, &mb[0]);
2257 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2271 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2275 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2279 mb[1] = BIT_1; /* Data DMA Channel Burst Enable */
2280 mb[2] = BIT_1; /* Command DMA Channel Burst Enable */
2281 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2285 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2291 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2563 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2617 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
3706 else if (pkt->entry_status & BIT_1)
3726 } else if (pkt->entry_status & BIT_1) { /* FULL flag */
3903 qla1280_mailbox_command(ha, BIT_6 | BIT_3 | BIT_2 | BIT_1 | BIT_0,