Searched refs:val (Results 1 - 25 of 20471) sorted by relevance

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/kernel/linux/linux-6.6/arch/alpha/lib/
H A D	fpreg.c	14 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); 16 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); 22 unsigned long val; in alpha_read_fp_reg() local 28 val = current_thread_info()->fp[reg]; in alpha_read_fp_reg() 30 case 0: STT( 0, val); break; in alpha_read_fp_reg() 31 case 1: STT( 1, val); break; in alpha_read_fp_reg() 32 case 2: STT( 2, val); break; in alpha_read_fp_reg() 33 case 3: STT( 3, val); brea in alpha_read_fp_reg() 75 alpha_write_fp_reg(unsigned long reg, unsigned long val) alpha_write_fp_reg() argument 131 unsigned long val; alpha_read_fp_reg_s() local 186 alpha_write_fp_reg_s(unsigned long reg, unsigned long val) alpha_write_fp_reg_s() argument [all...]
/kernel/linux/linux-5.10/arch/alpha/lib/
H A D	fpreg.c	12 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); 14 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); 20 unsigned long val; in alpha_read_fp_reg() local 23 case 0: STT( 0, val); break; in alpha_read_fp_reg() 24 case 1: STT( 1, val); break; in alpha_read_fp_reg() 25 case 2: STT( 2, val); break; in alpha_read_fp_reg() 26 case 3: STT( 3, val); break; in alpha_read_fp_reg() 27 case 4: STT( 4, val); brea in alpha_read_fp_reg() 68 alpha_write_fp_reg(unsigned long reg, unsigned long val) alpha_write_fp_reg() argument 116 unsigned long val; alpha_read_fp_reg_s() local 164 alpha_write_fp_reg_s(unsigned long reg, unsigned long val) alpha_write_fp_reg_s() argument [all...]
/kernel/liteos_a/arch/arm/arm/include/
H A D	arm.h	41 UINT32 val; in OsArmReadSctlr() local 42 __asm__ volatile("mrc p15, 0, %0, c1,c0,0" : "=r"(val)); in OsArmReadSctlr() 43 return val; in OsArmReadSctlr() 46 STATIC INLINE VOID OsArmWriteSctlr(UINT32 val) in OsArmWriteSctlr() argument 48 __asm__ volatile("mcr p15, 0, %0, c1,c0,0" ::"r"(val)); in OsArmWriteSctlr() 54 UINT32 val; in OsArmReadActlr() local 55 __asm__ volatile("mrc p15, 0, %0, c1,c0,1" : "=r"(val)); in OsArmReadActlr() 56 return val; in OsArmReadActlr() 59 STATIC INLINE VOID OsArmWriteActlr(UINT32 val) in OsArmWriteActlr() argument 61 __asm__ volatile("mcr p15, 0, %0, c1,c0,1" ::"r"(val)); in OsArmWriteActlr() 67 UINT32 val; OsArmReadCpacr() local 72 OsArmWriteCpacr(UINT32 val) OsArmWriteCpacr() argument 80 UINT32 val; OsArmReadTtbr() local 85 OsArmWriteTtbr(UINT32 val) OsArmWriteTtbr() argument 93 UINT32 val; OsArmReadTtbr0() local 98 OsArmWriteTtbr0(UINT32 val) OsArmWriteTtbr0() argument 106 UINT32 val; OsArmReadTtbr1() local 111 OsArmWriteTtbr1(UINT32 val) OsArmWriteTtbr1() argument 119 UINT32 val; OsArmReadTtbcr() local 124 OsArmWriteTtbcr(UINT32 val) OsArmWriteTtbcr() argument 132 UINT32 val; OsArmReadDacr() local 137 OsArmWriteDacr(UINT32 val) OsArmWriteDacr() argument 145 UINT32 val; OsArmReadDfsr() local 150 OsArmWriteDfsr(UINT32 val) OsArmWriteDfsr() argument 158 UINT32 val; OsArmReadIfsr() local 163 OsArmWriteIfsr(UINT32 val) OsArmWriteIfsr() argument 171 UINT32 val; OsArmReadDfar() local 176 OsArmWriteDfar(UINT32 val) OsArmWriteDfar() argument 184 UINT32 val; OsArmReadWfar() local 189 OsArmWriteWfar(UINT32 val) OsArmWriteWfar() argument 197 UINT32 val; OsArmReadIfar() local 202 OsArmWriteIfar(UINT32 val) OsArmWriteIfar() argument 210 UINT32 val; OsArmReadFcseidr() local 215 OsArmWriteFcseidr(UINT32 val) OsArmWriteFcseidr() argument 223 UINT32 val; OsArmReadContextidr() local 228 OsArmWriteContextidr(UINT32 val) OsArmWriteContextidr() argument 236 UINT32 val; OsArmReadTpidrurw() local 241 OsArmWriteTpidrurw(UINT32 val) OsArmWriteTpidrurw() argument 249 UINT32 val; OsArmReadTpidruro() local 254 OsArmWriteTpidruro(UINT32 val) OsArmWriteTpidruro() argument 262 UINT32 val; OsArmReadTpidrprw() local 267 OsArmWriteTpidrprw(UINT32 val) OsArmWriteTpidrprw() argument 275 UINT32 val; OsArmReadMidr() local 280 OsArmWriteMidr(UINT32 val) OsArmWriteMidr() argument 288 UINT32 val; OsArmReadMpidr() local 293 OsArmWriteMpidr(UINT32 val) OsArmWriteMpidr() argument 301 UINT32 val; OsArmReadVbar() local 306 OsArmWriteVbar(UINT32 val) OsArmWriteVbar() argument 314 UINT32 val; OsArmReadCbar() local 319 OsArmWriteCbar(UINT32 val) OsArmWriteCbar() argument 327 UINT32 val; OsArmReadAts1cpr() local 332 OsArmWriteAts1cpr(UINT32 val) OsArmWriteAts1cpr() argument 340 UINT32 val; OsArmReadAts1cpw() local 345 OsArmWriteAts1cpw(UINT32 val) OsArmWriteAts1cpw() argument 353 UINT32 val; OsArmReadAts1cur() local 358 OsArmWriteAts1cur(UINT32 val) OsArmWriteAts1cur() argument 366 UINT32 val; OsArmReadAts1cuw() local 371 OsArmWriteAts1cuw(UINT32 val) OsArmWriteAts1cuw() argument 379 UINT32 val; OsArmReadAts12nsopr() local 384 OsArmWriteAts12nsopr(UINT32 val) OsArmWriteAts12nsopr() argument 392 UINT32 val; OsArmReadAts12nsopw() local 397 OsArmWriteAts12nsopw(UINT32 val) OsArmWriteAts12nsopw() argument 405 UINT32 val; OsArmReadAts12nsour() local 410 OsArmWriteAts12nsour(UINT32 val) OsArmWriteAts12nsour() argument 418 UINT32 val; OsArmReadAts12nsouw() local 423 OsArmWriteAts12nsouw(UINT32 val) OsArmWriteAts12nsouw() argument 431 UINT32 val; OsArmReadPar() local 436 OsArmWritePar(UINT32 val) OsArmWritePar() argument 444 UINT32 val; OsArmReadBpiall() local 449 OsArmWriteBpiall(UINT32 val) OsArmWriteBpiall() argument 457 UINT32 val; OsArmReadBpimva() local 462 OsArmWriteBpimva(UINT32 val) OsArmWriteBpimva() argument 470 UINT32 val; OsArmReadBpiallis() local 475 OsArmWriteBpiallis(UINT32 val) OsArmWriteBpiallis() argument 483 UINT32 val; OsArmReadTlbiallis() local 488 OsArmWriteTlbiallis(UINT32 val) OsArmWriteTlbiallis() argument 496 UINT32 val; OsArmReadTlbimvais() local 501 OsArmWriteTlbimvais(UINT32 val) OsArmWriteTlbimvais() argument 509 UINT32 val; OsArmReadTlbiasidis() local 514 OsArmWriteTlbiasidis(UINT32 val) OsArmWriteTlbiasidis() argument 522 UINT32 val; OsArmReadTlbimvaais() local 527 OsArmWriteTlbimvaais(UINT32 val) OsArmWriteTlbimvaais() argument 535 UINT32 val; OsArmReadItlbiall() local 540 OsArmWriteItlbiall(UINT32 val) OsArmWriteItlbiall() argument 548 UINT32 val; OsArmReadItlbimva() local 553 OsArmWriteItlbimva(UINT32 val) OsArmWriteItlbimva() argument 561 UINT32 val; OsArmReadItlbiasid() local 566 OsArmWriteItlbiasid(UINT32 val) OsArmWriteItlbiasid() argument 574 UINT32 val; OsArmReadDtlbiall() local 579 OsArmWriteDtlbiall(UINT32 val) OsArmWriteDtlbiall() argument 587 UINT32 val; OsArmReadDtlbimva() local 592 OsArmWriteDtlbimva(UINT32 val) OsArmWriteDtlbimva() argument 600 UINT32 val; OsArmReadDtlbiasid() local 605 OsArmWriteDtlbiasid(UINT32 val) OsArmWriteDtlbiasid() argument 613 UINT32 val; OsArmReadTlbiall() local 618 OsArmWriteTlbiall(UINT32 val) OsArmWriteTlbiall() argument 626 UINT32 val; OsArmReadTlbimva() local 631 OsArmWriteTlbimva(UINT32 val) OsArmWriteTlbimva() argument 639 UINT32 val; OsArmReadTlbiasid() local 644 OsArmWriteTlbiasid(UINT32 val) OsArmWriteTlbiasid() argument 652 UINT32 val; OsArmReadTlbimvaa() local 657 OsArmWriteTlbimvaa(UINT32 val) OsArmWriteTlbimvaa() argument 665 UINT32 val; OsArmReadL2ctlr() local 670 OsArmWriteL2ctlr(UINT32 val) OsArmWriteL2ctlr() argument 678 UINT32 val; OsArmReadL2ectlr() local 683 OsArmWriteL2ectlr(UINT32 val) OsArmWriteL2ectlr() argument 691 UINT32 val; OsArmReadDbddidr() local 696 OsArmWriteDbddidr(UINT32 val) OsArmWriteDbddidr() argument 704 UINT32 val; OsArmReadDbgdrar() local 709 OsArmWriteDbgdrar(UINT32 val) OsArmWriteDbgdrar() argument 717 UINT32 val; OsArmReadDbgdsar() local 722 OsArmWriteDbgdsar(UINT32 val) OsArmWriteDbgdsar() argument 730 UINT32 val; OsArmReadDbgdscr() local 735 OsArmWriteDbgdscr(UINT32 val) OsArmWriteDbgdscr() argument 743 UINT32 val; OsArmReadDbgdtrtxint() local 748 OsArmWriteDbgdtrtxint(UINT32 val) OsArmWriteDbgdtrtxint() argument 756 UINT32 val; OsArmReadDbgdtrrxint() local 761 OsArmWriteDbgdtrrxint(UINT32 val) OsArmWriteDbgdtrrxint() argument 769 UINT32 val; OsArmReadDbgwfar() local 774 OsArmWriteDbgwfar(UINT32 val) OsArmWriteDbgwfar() argument 782 UINT32 val; OsArmReadDbgvcr() local 787 OsArmWriteDbgvcr(UINT32 val) OsArmWriteDbgvcr() argument 795 UINT32 val; OsArmReadDbgecr() local 800 OsArmWriteDbgecr(UINT32 val) OsArmWriteDbgecr() argument 808 UINT32 val; OsArmReadDbgdsccr() local 813 OsArmWriteDbgdsccr(UINT32 val) OsArmWriteDbgdsccr() argument 821 UINT32 val; OsArmReadDbgdsmcr() local 826 OsArmWriteDbgdsmcr(UINT32 val) OsArmWriteDbgdsmcr() argument 834 UINT32 val; OsArmReadDbgdtrrxext() local 839 OsArmWriteDbgdtrrxext(UINT32 val) OsArmWriteDbgdtrrxext() argument 847 UINT32 val; OsArmReadDbgdscrext() local 852 OsArmWriteDbgdscrext(UINT32 val) OsArmWriteDbgdscrext() argument 860 UINT32 val; OsArmReadDbgdtrtxext() local 865 OsArmWriteDbgdtrtxext(UINT32 val) OsArmWriteDbgdtrtxext() argument 873 UINT32 val; OsArmReadDbgdrcr() local 878 OsArmWriteDbgdrcr(UINT32 val) OsArmWriteDbgdrcr() argument 886 UINT32 val; OsArmReadDbgvr0() local 891 OsArmWriteDbgvr0(UINT32 val) OsArmWriteDbgvr0() argument 899 UINT32 val; OsArmReadDbgvr1() local 904 OsArmWriteDbgvr1(UINT32 val) OsArmWriteDbgvr1() argument 912 UINT32 val; OsArmReadDbgvr2() local 917 OsArmWriteDbgvr2(UINT32 val) OsArmWriteDbgvr2() argument 925 UINT32 val; OsArmReadDbgbcr0() local 930 OsArmWriteDbgbcr0(UINT32 val) OsArmWriteDbgbcr0() argument 938 UINT32 val; OsArmReadDbgbcr1() local 943 OsArmWriteDbgbcr1(UINT32 val) OsArmWriteDbgbcr1() argument 951 UINT32 val; OsArmReadDbgbcr2() local 956 OsArmWriteDbgbcr2(UINT32 val) OsArmWriteDbgbcr2() argument 964 UINT32 val; OsArmReadDbgwvr0() local 969 OsArmWriteDbgwvr0(UINT32 val) OsArmWriteDbgwvr0() argument 977 UINT32 val; OsArmReadDbgwvr1() local 982 OsArmWriteDbgwvr1(UINT32 val) OsArmWriteDbgwvr1() argument 990 UINT32 val; OsArmReadDbgwcr0() local 995 OsArmWriteDbgwcr0(UINT32 val) OsArmWriteDbgwcr0() argument 1003 UINT32 val; OsArmReadDbgwcr1() local 1008 OsArmWriteDbgwcr1(UINT32 val) OsArmWriteDbgwcr1() argument 1016 UINT32 val; OsArmReadDbgoslar() local 1021 OsArmWriteDbgoslar(UINT32 val) OsArmWriteDbgoslar() argument 1029 UINT32 val; OsArmReadDbgoslsr() local 1034 OsArmWriteDbgoslsr(UINT32 val) OsArmWriteDbgoslsr() argument 1042 UINT32 val; OsArmReadDbgossrr() local 1047 OsArmWriteDbgossrr(UINT32 val) OsArmWriteDbgossrr() argument 1055 UINT32 val; OsArmReadDbgprcr() local 1060 OsArmWriteDbgprcr(UINT32 val) OsArmWriteDbgprcr() argument 1068 UINT32 val; OsArmReadDbgprsr() local 1073 OsArmWriteDbgprsr(UINT32 val) OsArmWriteDbgprsr() argument 1081 UINT32 val; OsArmReadDbgclaimset() local 1086 OsArmWriteDbgclaimset(UINT32 val) OsArmWriteDbgclaimset() argument 1094 UINT32 val; OsArmReadDbgclaimclr() local 1099 OsArmWriteDbgclaimclr(UINT32 val) OsArmWriteDbgclaimclr() argument 1107 UINT32 val; OsArmReadDbgauthstatus() local 1112 OsArmWriteDbgauthstatus(UINT32 val) OsArmWriteDbgauthstatus() argument 1120 UINT32 val; OsArmReadDbgdevid() local 1125 OsArmWriteDbgdevid(UINT32 val) OsArmWriteDbgdevid() argument [all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/neterion/vxge/
H A D	vxge-reg.h	23 * vxge_vBIT(val, loc, sz) - set bits at offset 25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) 26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) 54 #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4) 55 #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4) 56 #define VXGE_EPROM_IMG_FIX(val) (u3 [all...]
/kernel/linux/linux-5.10/drivers/media/tuners/
H A D	tda18271-maps.c	19 u8 val; member 190 { .rfmax = 62000, .val = 0x00 }, 191 { .rfmax = 84000, .val = 0x01 }, 192 { .rfmax = 100000, .val = 0x02 }, 193 { .rfmax = 140000, .val = 0x03 }, 194 { .rfmax = 170000, .val = 0x04 }, 195 { .rfmax = 180000, .val = 0x05 }, 196 { .rfmax = 865000, .val = 0x06 }, 197 { .rfmax = 0, .val = 0x00 }, /* end */ 201 { .rfmax = 61100, .val 924 int val, i = 0; tda18271_lookup_thermometer() local 1102 tda18271_lookup_map(struct dvb_frontend *fe, enum tda18271_map_type map_type, u32 *freq, u8 *val) tda18271_lookup_map() argument [all...]
/kernel/linux/linux-6.6/drivers/media/tuners/
H A D	tda18271-maps.c	19 u8 val; member 190 { .rfmax = 62000, .val = 0x00 }, 191 { .rfmax = 84000, .val = 0x01 }, 192 { .rfmax = 100000, .val = 0x02 }, 193 { .rfmax = 140000, .val = 0x03 }, 194 { .rfmax = 170000, .val = 0x04 }, 195 { .rfmax = 180000, .val = 0x05 }, 196 { .rfmax = 865000, .val = 0x06 }, 197 { .rfmax = 0, .val = 0x00 }, /* end */ 201 { .rfmax = 61100, .val 924 int val, i = 0; tda18271_lookup_thermometer() local 1102 tda18271_lookup_map(struct dvb_frontend *fe, enum tda18271_map_type map_type, u32 *freq, u8 *val) tda18271_lookup_map() argument [all...]
/kernel/linux/linux-5.10/arch/arm/include/asm/hardware/
H A D	cp14.h	12 #define dbg_write(val, reg) WCP14_##reg(val) 14 #define etm_write(val, reg) WCP14_##reg(val) 19 u32 val; \ 20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \ 21 val; \ 24 #define MCR14(val, op1, crn, crm, op2) \ 26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\ 152 #define WCP14_DBGDTRTXint(val) MCR1 [all...]
/kernel/linux/linux-6.6/arch/arm/include/asm/hardware/
H A D	cp14.h	12 #define dbg_write(val, reg) WCP14_##reg(val) 14 #define etm_write(val, reg) WCP14_##reg(val) 19 u32 val; \ 20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \ 21 val; \ 24 #define MCR14(val, op1, crn, crm, op2) \ 26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\ 152 #define WCP14_DBGDTRTXint(val) MCR1 [all...]
/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
H A D	coresight-etm-cp14.c	15 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument 19 *val = etm_read(ETMCR); in etm_readl_cp14() 22 *val = etm_read(ETMCCR); in etm_readl_cp14() 25 *val = etm_read(ETMTRIGGER); in etm_readl_cp14() 28 *val = etm_read(ETMSR); in etm_readl_cp14() 31 *val = etm_read(ETMSCR); in etm_readl_cp14() 34 *val = etm_read(ETMTSSCR); in etm_readl_cp14() 37 *val = etm_read(ETMTEEVR); in etm_readl_cp14() 40 *val = etm_read(ETMTECR1); in etm_readl_cp14() 43 *val in etm_readl_cp14() 306 etm_writel_cp14(u32 reg, u32 val) etm_writel_cp14() argument [all...]
/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
H A D	coresight-etm-cp14.c	15 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument 19 *val = etm_read(ETMCR); in etm_readl_cp14() 22 *val = etm_read(ETMCCR); in etm_readl_cp14() 25 *val = etm_read(ETMTRIGGER); in etm_readl_cp14() 28 *val = etm_read(ETMSR); in etm_readl_cp14() 31 *val = etm_read(ETMSCR); in etm_readl_cp14() 34 *val = etm_read(ETMTSSCR); in etm_readl_cp14() 37 *val = etm_read(ETMTEEVR); in etm_readl_cp14() 40 *val = etm_read(ETMTECR1); in etm_readl_cp14() 43 *val in etm_readl_cp14() 306 etm_writel_cp14(u32 reg, u32 val) etm_writel_cp14() argument [all...]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A D	types.h	133 #define CONF_HAS(config, val) ((config) & (1 << (val))) 138 #define CONF_IS(config, val) ((config) == (1 << (val))) 139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) 140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) 141 #define CONF_LT(config, val) ((config) & ((1 << (val)) [all...]
/kernel/linux/linux-6.6/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A D	types.h	133 #define CONF_HAS(config, val) ((config) & (1 << (val))) 138 #define CONF_IS(config, val) ((config) == (1 << (val))) 139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) 140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) 141 #define CONF_LT(config, val) ((config) & ((1 << (val)) [all...]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw89/
H A D	fw.h	341 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_IDX() argument 343 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_SEC_IDX() 346 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_OFFSET() argument 348 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_SEC_OFFSET() 351 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_LEN() argument 353 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_SEC_LEN() 356 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_TYPE() argument 358 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); in RTW89_SET_FWCMD_SEC_TYPE() 361 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_EXT_KEY() argument 363 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BI in RTW89_SET_FWCMD_SEC_EXT_KEY() 366 RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) RTW89_SET_FWCMD_SEC_SPP_MODE() argument 371 RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) RTW89_SET_FWCMD_SEC_KEY0() argument 376 RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) RTW89_SET_FWCMD_SEC_KEY1() argument 381 RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) RTW89_SET_FWCMD_SEC_KEY2() argument 386 RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) RTW89_SET_FWCMD_SEC_KEY3() argument 391 RTW89_SET_EDCA_SEL(void *cmd, u32 val) RTW89_SET_EDCA_SEL() argument 396 RTW89_SET_EDCA_BAND(void *cmd, u32 val) RTW89_SET_EDCA_BAND() argument 401 RTW89_SET_EDCA_WMM(void *cmd, u32 val) RTW89_SET_EDCA_WMM() argument 406 RTW89_SET_EDCA_AC(void *cmd, u32 val) RTW89_SET_EDCA_AC() argument 411 RTW89_SET_EDCA_PARAM(void *cmd, u32 val) RTW89_SET_EDCA_PARAM() argument 526 SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) SET_FW_HDR_PART_SIZE() argument 531 SET_CTRL_INFO_MACID(void *table, u32 val) SET_CTRL_INFO_MACID() argument 536 SET_CTRL_INFO_OPERATION(void *table, u32 val) SET_CTRL_INFO_OPERATION() argument 541 SET_CMC_TBL_DATARATE(void *table, u32 val) SET_CMC_TBL_DATARATE() argument 548 SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) SET_CMC_TBL_FORCE_TXOP() argument 555 SET_CMC_TBL_DATA_BW(void *table, u32 val) SET_CMC_TBL_DATA_BW() argument 562 SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) SET_CMC_TBL_DATA_GI_LTF() argument 569 SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) SET_CMC_TBL_DARF_TC_INDEX() argument 576 SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) SET_CMC_TBL_ARFR_CTRL() argument 583 SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) SET_CMC_TBL_ACQ_RPT_EN() argument 590 SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) SET_CMC_TBL_MGQ_RPT_EN() argument 597 SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) SET_CMC_TBL_ULQ_RPT_EN() argument 604 SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) SET_CMC_TBL_TWTQ_RPT_EN() argument 611 SET_CMC_TBL_DISRTSFB(void *table, u32 val) SET_CMC_TBL_DISRTSFB() argument 618 SET_CMC_TBL_DISDATAFB(void *table, u32 val) SET_CMC_TBL_DISDATAFB() argument 625 SET_CMC_TBL_TRYRATE(void *table, u32 val) SET_CMC_TBL_TRYRATE() argument 632 SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) SET_CMC_TBL_AMPDU_DENSITY() argument 639 SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) SET_CMC_TBL_DATA_RTY_LOWEST_RATE() argument 646 SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) SET_CMC_TBL_AMPDU_TIME_SEL() argument 653 SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) SET_CMC_TBL_AMPDU_LEN_SEL() argument 660 SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) SET_CMC_TBL_RTS_TXCNT_LMT_SEL() argument 667 SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) SET_CMC_TBL_RTS_TXCNT_LMT() argument 674 SET_CMC_TBL_RTSRATE(void *table, u32 val) SET_CMC_TBL_RTSRATE() argument 681 SET_CMC_TBL_VCS_STBC(void *table, u32 val) SET_CMC_TBL_VCS_STBC() argument 688 SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) SET_CMC_TBL_RTS_RTY_LOWEST_RATE() argument 695 SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) SET_CMC_TBL_DATA_TX_CNT_LMT() argument 702 SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) SET_CMC_TBL_DATA_TXCNT_LMT_SEL() argument 709 SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) SET_CMC_TBL_MAX_AGG_NUM_SEL() argument 716 SET_CMC_TBL_RTS_EN(void *table, u32 val) SET_CMC_TBL_RTS_EN() argument 723 SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) SET_CMC_TBL_CTS2SELF_EN() argument 730 SET_CMC_TBL_CCA_RTS(void *table, u32 val) SET_CMC_TBL_CCA_RTS() argument 737 SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) SET_CMC_TBL_HW_RTS_EN() argument 744 SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) SET_CMC_TBL_RTS_DROP_DATA_MODE() argument 751 SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) SET_CMC_TBL_AMPDU_MAX_LEN() argument 758 SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) SET_CMC_TBL_UL_MU_DIS() argument 765 SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) SET_CMC_TBL_AMPDU_MAX_TIME() argument 772 SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) SET_CMC_TBL_MAX_AGG_NUM() argument 779 SET_CMC_TBL_BA_BMAP(void *table, u32 val) SET_CMC_TBL_BA_BMAP() argument 786 SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) SET_CMC_TBL_VO_LFTIME_SEL() argument 793 SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) SET_CMC_TBL_VI_LFTIME_SEL() argument 800 SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) SET_CMC_TBL_BE_LFTIME_SEL() argument 807 SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) SET_CMC_TBL_BK_LFTIME_SEL() argument 814 SET_CMC_TBL_SECTYPE(void *table, u32 val) SET_CMC_TBL_SECTYPE() argument 821 SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) SET_CMC_TBL_MULTI_PORT_ID() argument 828 SET_CMC_TBL_BMC(void *table, u32 val) SET_CMC_TBL_BMC() argument 835 SET_CMC_TBL_MBSSID(void *table, u32 val) SET_CMC_TBL_MBSSID() argument 842 SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) SET_CMC_TBL_NAVUSEHDR() argument 849 SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) SET_CMC_TBL_TXPWR_MODE() argument 856 SET_CMC_TBL_DATA_DCM(void *table, u32 val) SET_CMC_TBL_DATA_DCM() argument 863 SET_CMC_TBL_DATA_ER(void *table, u32 val) SET_CMC_TBL_DATA_ER() argument 870 SET_CMC_TBL_DATA_LDPC(void *table, u32 val) SET_CMC_TBL_DATA_LDPC() argument 877 SET_CMC_TBL_DATA_STBC(void *table, u32 val) SET_CMC_TBL_DATA_STBC() argument 884 SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) SET_CMC_TBL_A_CTRL_BQR() argument 891 SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) SET_CMC_TBL_A_CTRL_UPH() argument 898 SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) SET_CMC_TBL_A_CTRL_BSR() argument 905 SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) SET_CMC_TBL_A_CTRL_CAS() argument 912 SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) SET_CMC_TBL_DATA_BW_ER() argument 919 SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) SET_CMC_TBL_LSIG_TXOP_EN() argument 926 SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) SET_CMC_TBL_CTRL_CNT_VLD() argument 933 SET_CMC_TBL_CTRL_CNT(void *table, u32 val) SET_CMC_TBL_CTRL_CNT() argument 940 SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) SET_CMC_TBL_RESP_REF_RATE() argument 947 SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) SET_CMC_TBL_ALL_ACK_SUPPORT() argument 954 SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT() argument 961 SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) SET_CMC_TBL_NTX_PATH_EN() argument 968 SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) SET_CMC_TBL_PATH_MAP_A() argument 975 SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) SET_CMC_TBL_PATH_MAP_B() argument 982 SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) SET_CMC_TBL_PATH_MAP_C() argument 989 SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) SET_CMC_TBL_PATH_MAP_D() argument 996 SET_CMC_TBL_ANTSEL_A(void *table, u32 val) SET_CMC_TBL_ANTSEL_A() argument 1003 SET_CMC_TBL_ANTSEL_B(void *table, u32 val) SET_CMC_TBL_ANTSEL_B() argument 1010 SET_CMC_TBL_ANTSEL_C(void *table, u32 val) SET_CMC_TBL_ANTSEL_C() argument 1017 SET_CMC_TBL_ANTSEL_D(void *table, u32 val) SET_CMC_TBL_ANTSEL_D() argument 1025 SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) SET_CMC_TBL_NOMINAL_PKT_PADDING_V1() argument 1032 SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1() argument 1039 SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1() argument 1046 SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1() argument 1054 SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) SET_CMC_TBL_ADDR_CAM_INDEX() argument 1061 SET_CMC_TBL_PAID(void *table, u32 val) SET_CMC_TBL_PAID() argument 1068 SET_CMC_TBL_ULDL(void *table, u32 val) SET_CMC_TBL_ULDL() argument 1075 SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) SET_CMC_TBL_DOPPLER_CTRL() argument 1081 SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) SET_CMC_TBL_NOMINAL_PKT_PADDING() argument 1088 SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) SET_CMC_TBL_NOMINAL_PKT_PADDING40() argument 1095 SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) SET_CMC_TBL_TXPWR_TOLERENCE() argument 1102 SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) SET_CMC_TBL_NOMINAL_PKT_PADDING80() argument 1109 SET_CMC_TBL_NC(void *table, u32 val) SET_CMC_TBL_NC() argument 1116 SET_CMC_TBL_NR(void *table, u32 val) SET_CMC_TBL_NR() argument 1123 SET_CMC_TBL_NG(void *table, u32 val) SET_CMC_TBL_NG() argument 1130 SET_CMC_TBL_CB(void *table, u32 val) SET_CMC_TBL_CB() argument 1137 SET_CMC_TBL_CS(void *table, u32 val) SET_CMC_TBL_CS() argument 1144 SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) SET_CMC_TBL_CSI_TXBF_EN() argument 1151 SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) SET_CMC_TBL_CSI_STBC_EN() argument 1158 SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) SET_CMC_TBL_CSI_LDPC_EN() argument 1165 SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) SET_CMC_TBL_CSI_PARA_EN() argument 1172 SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) SET_CMC_TBL_CSI_FIX_RATE() argument 1179 SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) SET_CMC_TBL_CSI_GI_LTF() argument 1186 SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) SET_CMC_TBL_NOMINAL_PKT_PADDING160() argument 1194 SET_CMC_TBL_CSI_BW(void *table, u32 val) SET_CMC_TBL_CSI_BW() argument 1201 SET_DCTL_MACID_V1(void *table, u32 val) SET_DCTL_MACID_V1() argument 1206 SET_DCTL_OPERATION_V1(void *table, u32 val) SET_DCTL_OPERATION_V1() argument 1212 SET_DCTL_QOS_FIELD_V1(void *table, u32 val) SET_DCTL_QOS_FIELD_V1() argument 1220 SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val) SET_DCTL_HW_EXSEQ_MACID_V1() argument 1228 SET_DCTL_QOS_DATA_V1(void *table, u32 val) SET_DCTL_QOS_DATA_V1() argument 1236 SET_DCTL_AES_IV_L_V1(void *table, u32 val) SET_DCTL_AES_IV_L_V1() argument 1244 SET_DCTL_AES_IV_H_V1(void *table, u32 val) SET_DCTL_AES_IV_H_V1() argument 1252 SET_DCTL_SEQ0_V1(void *table, u32 val) SET_DCTL_SEQ0_V1() argument 1260 SET_DCTL_SEQ1_V1(void *table, u32 val) SET_DCTL_SEQ1_V1() argument 1268 SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val) SET_DCTL_AMSDU_MAX_LEN_V1() argument 1276 SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val) SET_DCTL_STA_AMSDU_EN_V1() argument 1284 SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val) SET_DCTL_CHKSUM_OFLD_EN_V1() argument 1292 SET_DCTL_WITH_LLC_V1(void *table, u32 val) SET_DCTL_WITH_LLC_V1() argument 1300 SET_DCTL_SEQ2_V1(void *table, u32 val) SET_DCTL_SEQ2_V1() argument 1308 SET_DCTL_SEQ3_V1(void *table, u32 val) SET_DCTL_SEQ3_V1() argument 1316 SET_DCTL_TGT_IND_V1(void *table, u32 val) SET_DCTL_TGT_IND_V1() argument 1324 SET_DCTL_TGT_IND_EN_V1(void *table, u32 val) SET_DCTL_TGT_IND_EN_V1() argument 1332 SET_DCTL_HTC_LB_V1(void *table, u32 val) SET_DCTL_HTC_LB_V1() argument 1340 SET_DCTL_MHDR_LEN_V1(void *table, u32 val) SET_DCTL_MHDR_LEN_V1() argument 1348 SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val) SET_DCTL_VLAN_TAG_VALID_V1() argument 1356 SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val) SET_DCTL_VLAN_TAG_SEL_V1() argument 1364 SET_DCTL_HTC_ORDER_V1(void *table, u32 val) SET_DCTL_HTC_ORDER_V1() argument 1372 SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val) SET_DCTL_SEC_KEY_ID_V1() argument 1380 SET_DCTL_WAPI_V1(void *table, u32 val) SET_DCTL_WAPI_V1() argument 1388 SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val) SET_DCTL_SEC_ENT_MODE_V1() argument 1396 SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val) SET_DCTL_SEC_ENT0_KEYID_V1() argument 1403 SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val) SET_DCTL_SEC_ENT1_KEYID_V1() argument 1410 SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val) SET_DCTL_SEC_ENT2_KEYID_V1() argument 1417 SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val) SET_DCTL_SEC_ENT3_KEYID_V1() argument 1424 SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val) SET_DCTL_SEC_ENT4_KEYID_V1() argument 1431 SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val) SET_DCTL_SEC_ENT5_KEYID_V1() argument 1438 SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val) SET_DCTL_SEC_ENT6_KEYID_V1() argument 1446 SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val) SET_DCTL_SEC_ENT_VALID_V1() argument 1454 SET_DCTL_SEC_ENT0_V1(void *table, u32 val) SET_DCTL_SEC_ENT0_V1() argument 1461 SET_DCTL_SEC_ENT1_V1(void *table, u32 val) SET_DCTL_SEC_ENT1_V1() argument 1468 SET_DCTL_SEC_ENT2_V1(void *table, u32 val) SET_DCTL_SEC_ENT2_V1() argument 1475 SET_DCTL_SEC_ENT3_V1(void *table, u32 val) SET_DCTL_SEC_ENT3_V1() argument 1482 SET_DCTL_SEC_ENT4_V1(void *table, u32 val) SET_DCTL_SEC_ENT4_V1() argument 1489 SET_DCTL_SEC_ENT5_V1(void *table, u32 val) SET_DCTL_SEC_ENT5_V1() argument 1496 SET_DCTL_SEC_ENT6_V1(void *table, u32 val) SET_DCTL_SEC_ENT6_V1() argument 1503 SET_BCN_UPD_PORT(void *h2c, u32 val) SET_BCN_UPD_PORT() argument 1508 SET_BCN_UPD_MBSSID(void *h2c, u32 val) SET_BCN_UPD_MBSSID() argument 1513 SET_BCN_UPD_BAND(void *h2c, u32 val) SET_BCN_UPD_BAND() argument 1518 SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val) SET_BCN_UPD_GRP_IE_OFST() argument 1523 SET_BCN_UPD_MACID(void *h2c, u32 val) SET_BCN_UPD_MACID() argument 1528 SET_BCN_UPD_SSN_SEL(void *h2c, u32 val) SET_BCN_UPD_SSN_SEL() argument 1533 SET_BCN_UPD_SSN_MODE(void *h2c, u32 val) SET_BCN_UPD_SSN_MODE() argument 1538 SET_BCN_UPD_RATE(void *h2c, u32 val) SET_BCN_UPD_RATE() argument 1543 SET_BCN_UPD_TXPWR(void *h2c, u32 val) SET_BCN_UPD_TXPWR() argument 1548 SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val) SET_BCN_UPD_TXINFO_CTRL_EN() argument 1553 SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val) SET_BCN_UPD_NTX_PATH_EN() argument 1558 SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val) SET_BCN_UPD_PATH_MAP_A() argument 1563 SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val) SET_BCN_UPD_PATH_MAP_B() argument 1568 SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val) SET_BCN_UPD_PATH_MAP_C() argument 1573 SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val) SET_BCN_UPD_PATH_MAP_D() argument 1578 SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val) SET_BCN_UPD_PATH_ANTSEL_A() argument 1583 SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val) SET_BCN_UPD_PATH_ANTSEL_B() argument 1588 SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val) SET_BCN_UPD_PATH_ANTSEL_C() argument 1593 SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val) SET_BCN_UPD_PATH_ANTSEL_D() argument 1598 SET_BCN_UPD_CSA_OFST(void *h2c, u32 val) SET_BCN_UPD_CSA_OFST() argument 1603 SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) SET_FWROLE_MAINTAIN_MACID() argument 1608 SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) SET_FWROLE_MAINTAIN_SELF_ROLE() argument 1613 SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) SET_FWROLE_MAINTAIN_UPD_MODE() argument 1618 SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) SET_FWROLE_MAINTAIN_WIFI_ROLE() argument 1623 SET_JOININFO_MACID(void *h2c, u32 val) SET_JOININFO_MACID() argument 1628 SET_JOININFO_OP(void *h2c, u32 val) SET_JOININFO_OP() argument 1633 SET_JOININFO_BAND(void *h2c, u32 val) SET_JOININFO_BAND() argument 1638 SET_JOININFO_WMM(void *h2c, u32 val) SET_JOININFO_WMM() argument 1643 SET_JOININFO_TGR(void *h2c, u32 val) SET_JOININFO_TGR() argument 1648 SET_JOININFO_ISHESTA(void *h2c, u32 val) SET_JOININFO_ISHESTA() argument 1653 SET_JOININFO_DLBW(void *h2c, u32 val) SET_JOININFO_DLBW() argument 1658 SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val) SET_JOININFO_TF_MAC_PAD() argument 1663 SET_JOININFO_DL_T_PE(void *h2c, u32 val) SET_JOININFO_DL_T_PE() argument 1668 SET_JOININFO_PORT_ID(void *h2c, u32 val) SET_JOININFO_PORT_ID() argument 1673 SET_JOININFO_NET_TYPE(void *h2c, u32 val) SET_JOININFO_NET_TYPE() argument 1678 SET_JOININFO_WIFI_ROLE(void *h2c, u32 val) SET_JOININFO_WIFI_ROLE() argument 1683 SET_JOININFO_SELF_ROLE(void *h2c, u32 val) SET_JOININFO_SELF_ROLE() argument 1688 SET_GENERAL_PKT_MACID(void *h2c, u32 val) SET_GENERAL_PKT_MACID() argument 1693 SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) SET_GENERAL_PKT_PROBRSP_ID() argument 1698 SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) SET_GENERAL_PKT_PSPOLL_ID() argument 1703 SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) SET_GENERAL_PKT_NULL_ID() argument 1708 SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) SET_GENERAL_PKT_QOS_NULL_ID() argument 1713 SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) SET_GENERAL_PKT_CTS2SELF_ID() argument 1718 SET_LOG_CFG_LEVEL(void *h2c, u32 val) SET_LOG_CFG_LEVEL() argument 1723 SET_LOG_CFG_PATH(void *h2c, u32 val) SET_LOG_CFG_PATH() argument 1728 SET_LOG_CFG_COMP(void *h2c, u32 val) SET_LOG_CFG_COMP() argument 1733 SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) SET_LOG_CFG_COMP_EXT() argument 1738 SET_BA_CAM_VALID(void *h2c, u32 val) SET_BA_CAM_VALID() argument 1743 SET_BA_CAM_INIT_REQ(void *h2c, u32 val) SET_BA_CAM_INIT_REQ() argument 1748 SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val) SET_BA_CAM_ENTRY_IDX() argument 1753 SET_BA_CAM_TID(void *h2c, u32 val) SET_BA_CAM_TID() argument 1758 SET_BA_CAM_MACID(void *h2c, u32 val) SET_BA_CAM_MACID() argument 1763 SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val) SET_BA_CAM_BMAP_SIZE() argument 1768 SET_BA_CAM_SSN(void *h2c, u32 val) SET_BA_CAM_SSN() argument 1773 SET_BA_CAM_UID(void *h2c, u32 val) SET_BA_CAM_UID() argument 1778 SET_BA_CAM_STD_EN(void *h2c, u32 val) SET_BA_CAM_STD_EN() argument 1783 SET_BA_CAM_BAND(void *h2c, u32 val) SET_BA_CAM_BAND() argument 1788 SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val) SET_BA_CAM_ENTRY_IDX_V1() argument 1793 SET_LPS_PARM_MACID(void *h2c, u32 val) SET_LPS_PARM_MACID() argument 1798 SET_LPS_PARM_PSMODE(void *h2c, u32 val) SET_LPS_PARM_PSMODE() argument 1803 SET_LPS_PARM_RLBM(void *h2c, u32 val) SET_LPS_PARM_RLBM() argument 1808 SET_LPS_PARM_SMARTPS(void *h2c, u32 val) SET_LPS_PARM_SMARTPS() argument 1813 SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) SET_LPS_PARM_AWAKEINTERVAL() argument 1818 SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) SET_LPS_PARM_VOUAPSD() argument 1823 SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) SET_LPS_PARM_VIUAPSD() argument 1828 SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) SET_LPS_PARM_BEUAPSD() argument 1833 SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) SET_LPS_PARM_BKUAPSD() argument 1838 SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) SET_LPS_PARM_LASTRPWM() argument 1843 RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val) RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE() argument 1848 RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val) RTW89_SET_FWCMD_PKT_DROP_SEL() argument 1853 RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val) RTW89_SET_FWCMD_PKT_DROP_MACID() argument 1858 RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val) RTW89_SET_FWCMD_PKT_DROP_BAND() argument 1863 RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val) RTW89_SET_FWCMD_PKT_DROP_PORT() argument 1868 RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val) RTW89_SET_FWCMD_PKT_DROP_MBSSID() argument 1873 RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val) RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS() argument 1878 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val) RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0() argument 1883 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val) RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1() argument 1888 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val) RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2() argument 1893 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val) RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3() argument 1898 RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val) RTW89_SET_KEEP_ALIVE_ENABLE() argument 1903 RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val) RTW89_SET_KEEP_ALIVE_PKT_NULL_ID() argument 1908 RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val) RTW89_SET_KEEP_ALIVE_PERIOD() argument 1913 RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val) RTW89_SET_KEEP_ALIVE_MACID() argument 1918 RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val) RTW89_SET_DISCONNECT_DETECT_ENABLE() argument 1923 RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val) RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN() argument 1928 RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val) RTW89_SET_DISCONNECT_DETECT_DISCONNECT() argument 1933 RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val) RTW89_SET_DISCONNECT_DETECT_MAC_ID() argument 1938 RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val) RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD() argument 1943 RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val) RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT() argument 1948 RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val) RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT() argument 1953 RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val) RTW89_SET_WOW_GLOBAL_ENABLE() argument 1958 RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val) RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT() argument 1963 RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val) RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE() argument 1968 RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val) RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED() argument 1973 RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val) RTW89_SET_WOW_GLOBAL_MAC_ID() argument 1978 RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val) RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO() argument 1983 RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val) RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO() argument 1988 RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val) RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT() argument 1993 RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val) RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE() argument 1998 RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val) RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE() argument 2003 RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val) RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE() argument 2008 RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val) RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE() argument 2013 RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val) RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE() argument 2018 RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val) RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE() argument 2023 RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val) RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE() argument 2028 RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val) RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE() argument 2033 RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val) RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID() argument 2038 RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_R_W() argument 2043 RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_IDX() argument 2048 RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_WKFM1() argument 2053 RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_WKFM2() argument 2058 RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_WKFM3() argument 2063 RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_WKFM4() argument 2068 RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_CRC() argument 2073 RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH() argument 2078 RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR() argument 2083 RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_UC() argument 2088 RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_MC() argument 2093 RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_BC() argument 2098 RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val) RTW89_SET_WOW_CAM_UPD_VALID() argument 2152 RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) RTW89_SET_FWCMD_CXHDR_TYPE() argument 2157 RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) RTW89_SET_FWCMD_CXHDR_LEN() argument 2201 RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) RTW89_SET_FWCMD_CXROLE_CONNECT_CNT() argument 2206 RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) RTW89_SET_FWCMD_CXROLE_LINK_MODE() argument 2211 RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_NONE() argument 2216 RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_STA() argument 2221 RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_AP() argument 2226 RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_VAP() argument 2231 RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC() argument 2236 RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER() argument 2241 RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_MESH() argument 2246 RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR() argument 2251 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV() argument 2256 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC() argument 2261 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO() argument 2266 RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) RTW89_SET_FWCMD_CXROLE_ROLE_NAN() argument 2271 RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED() argument 2276 RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_PID() argument 2281 RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_PHY() argument 2286 RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_NOA() argument 2291 RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_BAND() argument 2296 RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS() argument 2301 RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_BW() argument 2306 RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_ROLE() argument 2311 RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_CH() argument 2316 RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL() argument 2321 RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL() argument 2326 RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE() argument 2331 RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE() argument 2336 RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR() argument 2341 RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2() argument 2346 RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_PID_V2() argument 2351 RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2() argument 2356 RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2() argument 2361 RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2() argument 2366 RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2() argument 2371 RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_BW_V2() argument 2376 RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2() argument 2381 RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_CH_V2() argument 2386 RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset) RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2() argument 2391 RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) RTW89_SET_FWCMD_CXROLE_MROLE_TYPE() argument 2396 RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) RTW89_SET_FWCMD_CXROLE_MROLE_NOA() argument 2401 RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) RTW89_SET_FWCMD_CXROLE_DBCC_EN() argument 2406 RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) RTW89_SET_FWCMD_CXROLE_DBCC_CHG() argument 2411 RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY() argument 2416 RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG() argument 2421 RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) RTW89_SET_FWCMD_CXCTRL_MANUAL() argument 2426 RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) RTW89_SET_FWCMD_CXCTRL_IGNORE_BT() argument 2431 RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN() argument 2436 RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) RTW89_SET_FWCMD_CXCTRL_TRACE_STEP() argument 2441 RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val) RTW89_SET_FWCMD_CXTRX_TXLV() argument 2446 RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val) RTW89_SET_FWCMD_CXTRX_RXLV() argument 2451 RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val) RTW89_SET_FWCMD_CXTRX_WLRSSI() argument 2456 RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val) RTW89_SET_FWCMD_CXTRX_BTRSSI() argument 2461 RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val) RTW89_SET_FWCMD_CXTRX_TXPWR() argument 2466 RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val) RTW89_SET_FWCMD_CXTRX_RXGAIN() argument 2471 RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val) RTW89_SET_FWCMD_CXTRX_BTTXPWR() argument 2476 RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val) RTW89_SET_FWCMD_CXTRX_BTRXGAIN() argument 2481 RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val) RTW89_SET_FWCMD_CXTRX_CN() argument 2486 RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val) RTW89_SET_FWCMD_CXTRX_NHM() argument 2491 RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val) RTW89_SET_FWCMD_CXTRX_BTPROFILE() argument 2496 RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val) RTW89_SET_FWCMD_CXTRX_RSVD2() argument 2501 RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val) RTW89_SET_FWCMD_CXTRX_TXRATE() argument 2506 RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val) RTW89_SET_FWCMD_CXTRX_RXRATE() argument 2511 RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val) RTW89_SET_FWCMD_CXTRX_TXTP() argument 2516 RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val) RTW89_SET_FWCMD_CXTRX_RXTP() argument 2521 RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val) RTW89_SET_FWCMD_CXTRX_RXERRRA() argument 2526 RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) RTW89_SET_FWCMD_CXRFK_STATE() argument 2531 RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) RTW89_SET_FWCMD_CXRFK_PATH_MAP() argument 2536 RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) RTW89_SET_FWCMD_CXRFK_PHY_MAP() argument 2541 RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) RTW89_SET_FWCMD_CXRFK_BAND() argument 2546 RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) RTW89_SET_FWCMD_CXRFK_TYPE() argument 2551 RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX() argument 2556 RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP() argument 2561 RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH() argument 2566 RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val) RTW89_SET_FWCMD_SCANOFLD_CH_NUM() argument 2571 RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val) RTW89_SET_FWCMD_SCANOFLD_CH_SIZE() argument 2576 RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PERIOD() argument 2581 RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_DWELL() argument 2586 RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_CENTER_CH() argument 2591 RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PRI_CH() argument 2596 RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_BW() argument 2601 RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_ACTION() argument 2606 RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_NUM_PKT() argument 2611 RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_TX() argument 2616 RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PAUSE_DATA() argument 2621 RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_BAND() argument 2626 RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PKT_ID() argument 2631 RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_DFS() argument 2636 RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_TX_NULL() argument 2641 RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_RANDOM() argument 2646 RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_CFG_TX() argument 2651 RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PKT0() argument 2656 RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PKT1() argument 2661 RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PKT2() argument 2666 RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PKT3() argument 2671 RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PKT4() argument 2676 RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PKT5() argument 2681 RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PKT6() argument 2686 RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_PKT7() argument 2691 RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val) RTW89_SET_FWCMD_CHINFO_POWER_IDX() argument 2723 RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val) RTW89_SET_FWCMD_P2P_MACID() argument 2728 RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val) RTW89_SET_FWCMD_P2P_P2PID() argument 2733 RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val) RTW89_SET_FWCMD_P2P_NOAID() argument 2738 RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val) RTW89_SET_FWCMD_P2P_ACT() argument 2743 RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val) RTW89_SET_FWCMD_P2P_TYPE() argument 2748 RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val) RTW89_SET_FWCMD_P2P_ALL_SLEP() argument 2753 RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val) RTW89_SET_FWCMD_NOA_START_TIME() argument 2758 RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val) RTW89_SET_FWCMD_NOA_INTERVAL() argument 2763 RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val) RTW89_SET_FWCMD_NOA_DURATION() argument 2768 RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val) RTW89_SET_FWCMD_NOA_COUNT() argument 2773 RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val) RTW89_SET_FWCMD_NOA_CTWINDOW() argument 2783 RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val) RTW89_SET_FWCMD_TSF32_TOGL_BAND() argument 2788 RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val) RTW89_SET_FWCMD_TSF32_TOGL_EN() argument 2793 RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val) RTW89_SET_FWCMD_TSF32_TOGL_PORT() argument 2798 RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val) RTW89_SET_FWCMD_TSF32_TOGL_EARLY() argument 2834 RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_MACID() argument 2839 RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0() argument 2844 RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1() argument 2849 RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH() argument 2854 RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH() argument 2859 RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_GROUP() argument 2864 RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_C2H_RPT() argument 2869 RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL() argument 2874 RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY() argument 2879 RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH() argument 2884 RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT() argument 2889 RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY() argument 2894 RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G() argument 2899 RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_PTA_EN() argument 2904 RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS() argument 2909 RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE() argument 2914 RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_DURATION() argument 2919 RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN() argument 2924 RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM() argument 2929 RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val) RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET() argument 2949 RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_START_MCC_GROUP() argument 2954 RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP() argument 2959 RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val) RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION() argument 2964 RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_START_MCC_OLD_GROUP() argument 2969 RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val) RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT() argument 2974 RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val) RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN() argument 2979 RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val) RTW89_SET_FWCMD_START_MCC_MACID() argument 2984 RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val) RTW89_SET_FWCMD_START_MCC_TSF_LOW() argument 2989 RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val) RTW89_SET_FWCMD_START_MCC_TSF_HIGH() argument 2994 RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val) RTW89_SET_FWCMD_STOP_MCC_MACID() argument 2999 RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_STOP_MCC_GROUP() argument 3004 RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val) RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS() argument 3009 RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP() argument 3014 RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val) RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS() argument 3019 RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP() argument 3032 RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP() argument 3037 RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X() argument 3042 RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y() argument 3047 RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP() argument 3052 RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID() argument 3057 RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH() argument 3068 RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SYNC_GROUP() argument 3073 RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE() argument 3078 RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET() argument 3083 RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET() argument 3101 RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP() argument 3107 RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP() argument 3113 RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID() argument 3118 RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X() argument 3123 RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y() argument 3129 RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW() argument 3135 RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH() argument 3141 RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X() argument 3147 RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val) RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y() argument [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/
H A D	adreno_pm4.xml.h	526 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument 528 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF() 532 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument 534 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC() 538 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument 540 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK() 544 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument 546 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT() 552 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument 554 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIF in CP_LOAD_STATE_1_STATE_TYPE() 558 CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) CP_LOAD_STATE_1_EXT_SRC_ADDR() argument 566 CP_LOAD_STATE4_0_DST_OFF(uint32_t val) CP_LOAD_STATE4_0_DST_OFF() argument 572 CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) CP_LOAD_STATE4_0_STATE_SRC() argument 578 CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) CP_LOAD_STATE4_0_STATE_BLOCK() argument 584 CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) CP_LOAD_STATE4_0_NUM_UNIT() argument 592 CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) CP_LOAD_STATE4_1_STATE_TYPE() argument 598 CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) CP_LOAD_STATE4_1_EXT_SRC_ADDR() argument 606 CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val) CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI() argument 614 CP_LOAD_STATE6_0_DST_OFF(uint32_t val) CP_LOAD_STATE6_0_DST_OFF() argument 620 CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val) CP_LOAD_STATE6_0_STATE_TYPE() argument 626 CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val) CP_LOAD_STATE6_0_STATE_SRC() argument 632 CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val) CP_LOAD_STATE6_0_STATE_BLOCK() argument 638 CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) CP_LOAD_STATE6_0_NUM_UNIT() argument 646 CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) CP_LOAD_STATE6_1_EXT_SRC_ADDR() argument 654 CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val) CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI() argument 664 CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) CP_DRAW_INDX_0_VIZ_QUERY() argument 672 CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) CP_DRAW_INDX_1_PRIM_TYPE() argument 678 CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) CP_DRAW_INDX_1_SOURCE_SELECT() argument 684 CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) CP_DRAW_INDX_1_VIS_CULL() argument 690 CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) CP_DRAW_INDX_1_INDEX_SIZE() argument 699 CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) CP_DRAW_INDX_1_NUM_INSTANCES() argument 707 CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) CP_DRAW_INDX_2_NUM_INDICES() argument 715 CP_DRAW_INDX_3_INDX_BASE(uint32_t val) CP_DRAW_INDX_3_INDX_BASE() argument 723 CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) CP_DRAW_INDX_4_INDX_SIZE() argument 731 CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) CP_DRAW_INDX_2_0_VIZ_QUERY() argument 739 CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) CP_DRAW_INDX_2_1_PRIM_TYPE() argument 745 CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) CP_DRAW_INDX_2_1_SOURCE_SELECT() argument 751 CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) CP_DRAW_INDX_2_1_VIS_CULL() argument 757 CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) CP_DRAW_INDX_2_1_INDEX_SIZE() argument 766 CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) CP_DRAW_INDX_2_1_NUM_INSTANCES() argument 774 CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) CP_DRAW_INDX_2_2_NUM_INDICES() argument 782 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) CP_DRAW_INDX_OFFSET_0_PRIM_TYPE() argument 788 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT() argument 794 CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) CP_DRAW_INDX_OFFSET_0_VIS_CULL() argument 800 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) CP_DRAW_INDX_OFFSET_0_INDEX_SIZE() argument 806 CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val) CP_DRAW_INDX_OFFSET_0_PATCH_TYPE() argument 816 CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES() argument 824 CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) CP_DRAW_INDX_OFFSET_2_NUM_INDICES() argument 832 CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val) CP_DRAW_INDX_OFFSET_3_FIRST_INDX() argument 841 CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val) CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO() argument 849 CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val) CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI() argument 859 CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val) CP_DRAW_INDX_OFFSET_6_MAX_INDICES() argument 867 CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) CP_DRAW_INDX_OFFSET_4_INDX_BASE() argument 875 CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) CP_DRAW_INDX_OFFSET_5_INDX_SIZE() argument 883 A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE() argument 889 A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT() argument 895 A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) A4XX_CP_DRAW_INDIRECT_0_VIS_CULL() argument 901 A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE() argument 907 A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE() argument 918 A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) A4XX_CP_DRAW_INDIRECT_1_INDIRECT() argument 927 A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val) A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO() argument 935 A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI() argument 945 A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE() argument 951 A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT() argument 957 A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL() argument 963 A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE() argument 969 A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE() argument 980 A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val) A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE() argument 988 A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val) A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE() argument 996 A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT() argument 1005 A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO() argument 1013 A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI() argument 1023 A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES() argument 1031 A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO() argument 1039 A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI() argument 1049 A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val) A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE() argument 1055 A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val) A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT() argument 1061 A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val) A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL() argument 1067 A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val) A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE() argument 1073 A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val) A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE() argument 1083 A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val) A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE() argument 1089 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val) A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF() argument 1137 CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val) CP_DRAW_PRED_SET_0_SRC() argument 1143 CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val) CP_DRAW_PRED_SET_0_TEST() argument 1155 CP_SET_DRAW_STATE__0_COUNT(uint32_t val) CP_SET_DRAW_STATE__0_COUNT() argument 1168 CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) CP_SET_DRAW_STATE__0_GROUP_ID() argument 1176 CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) CP_SET_DRAW_STATE__1_ADDR_LO() argument 1184 CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) CP_SET_DRAW_STATE__2_ADDR_HI() argument 1194 CP_SET_BIN_1_X1(uint32_t val) CP_SET_BIN_1_X1() argument 1200 CP_SET_BIN_1_Y1(uint32_t val) CP_SET_BIN_1_Y1() argument 1208 CP_SET_BIN_2_X2(uint32_t val) CP_SET_BIN_2_X2() argument 1214 CP_SET_BIN_2_Y2(uint32_t val) CP_SET_BIN_2_Y2() argument 1222 CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) CP_SET_BIN_DATA_0_BIN_DATA_ADDR() argument 1230 CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS() argument 1238 CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val) CP_SET_BIN_DATA5_0_VSC_SIZE() argument 1244 CP_SET_BIN_DATA5_0_VSC_N(uint32_t val) CP_SET_BIN_DATA5_0_VSC_N() argument 1252 CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val) CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO() argument 1260 CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val) CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI() argument 1268 CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val) CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO() argument 1276 CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val) CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI() argument 1284 CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val) CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO() argument 1292 CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val) CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI() argument 1304 CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val) CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE() argument 1310 CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val) CP_SET_BIN_DATA5_OFFSET_0_VSC_N() argument 1318 CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val) CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET() argument 1326 CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val) CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET() argument 1334 CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val) CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET() argument 1342 CP_REG_RMW_0_DST_REG(uint32_t val) CP_REG_RMW_0_DST_REG() argument 1348 CP_REG_RMW_0_ROTATE(uint32_t val) CP_REG_RMW_0_ROTATE() argument 1359 CP_REG_RMW_1_SRC0(uint32_t val) CP_REG_RMW_1_SRC0() argument 1367 CP_REG_RMW_2_SRC1(uint32_t val) CP_REG_RMW_2_SRC1() argument 1375 CP_REG_TO_MEM_0_REG(uint32_t val) CP_REG_TO_MEM_0_REG() argument 1381 CP_REG_TO_MEM_0_CNT(uint32_t val) CP_REG_TO_MEM_0_CNT() argument 1391 CP_REG_TO_MEM_1_DEST(uint32_t val) CP_REG_TO_MEM_1_DEST() argument 1399 CP_REG_TO_MEM_2_DEST_HI(uint32_t val) CP_REG_TO_MEM_2_DEST_HI() argument 1407 CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val) CP_REG_TO_MEM_OFFSET_REG_0_REG() argument 1413 CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val) CP_REG_TO_MEM_OFFSET_REG_0_CNT() argument 1423 CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val) CP_REG_TO_MEM_OFFSET_REG_1_DEST() argument 1431 CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val) CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI() argument 1439 CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val) CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0() argument 1448 CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_0_REG() argument 1454 CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_0_CNT() argument 1464 CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_1_DEST() argument 1472 CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI() argument 1480 CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO() argument 1488 CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI() argument 1496 CP_MEM_TO_REG_0_REG(uint32_t val) CP_MEM_TO_REG_0_REG() argument 1502 CP_MEM_TO_REG_0_CNT(uint32_t val) CP_MEM_TO_REG_0_CNT() argument 1512 CP_MEM_TO_REG_1_SRC(uint32_t val) CP_MEM_TO_REG_1_SRC() argument 1520 CP_MEM_TO_REG_2_SRC_HI(uint32_t val) CP_MEM_TO_REG_2_SRC_HI() argument 1536 CP_MEMCPY_0_DWORDS(uint32_t val) CP_MEMCPY_0_DWORDS() argument 1544 CP_MEMCPY_1_SRC_LO(uint32_t val) CP_MEMCPY_1_SRC_LO() argument 1552 CP_MEMCPY_2_SRC_HI(uint32_t val) CP_MEMCPY_2_SRC_HI() argument 1560 CP_MEMCPY_3_DST_LO(uint32_t val) CP_MEMCPY_3_DST_LO() argument 1568 CP_MEMCPY_4_DST_HI(uint32_t val) CP_MEMCPY_4_DST_HI() argument 1576 CP_REG_TO_SCRATCH_0_REG(uint32_t val) CP_REG_TO_SCRATCH_0_REG() argument 1582 CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val) CP_REG_TO_SCRATCH_0_SCRATCH() argument 1588 CP_REG_TO_SCRATCH_0_CNT(uint32_t val) CP_REG_TO_SCRATCH_0_CNT() argument 1596 CP_SCRATCH_TO_REG_0_REG(uint32_t val) CP_SCRATCH_TO_REG_0_REG() argument 1603 CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val) CP_SCRATCH_TO_REG_0_SCRATCH() argument 1609 CP_SCRATCH_TO_REG_0_CNT(uint32_t val) CP_SCRATCH_TO_REG_0_CNT() argument 1617 CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val) CP_SCRATCH_WRITE_0_SCRATCH() argument 1625 CP_MEM_WRITE_0_ADDR_LO(uint32_t val) CP_MEM_WRITE_0_ADDR_LO() argument 1633 CP_MEM_WRITE_1_ADDR_HI(uint32_t val) CP_MEM_WRITE_1_ADDR_HI() argument 1641 CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val) CP_COND_WRITE_0_FUNCTION() argument 1651 CP_COND_WRITE_1_POLL_ADDR(uint32_t val) CP_COND_WRITE_1_POLL_ADDR() argument 1659 CP_COND_WRITE_2_REF(uint32_t val) CP_COND_WRITE_2_REF() argument 1667 CP_COND_WRITE_3_MASK(uint32_t val) CP_COND_WRITE_3_MASK() argument 1675 CP_COND_WRITE_4_WRITE_ADDR(uint32_t val) CP_COND_WRITE_4_WRITE_ADDR() argument 1683 CP_COND_WRITE_5_WRITE_DATA(uint32_t val) CP_COND_WRITE_5_WRITE_DATA() argument 1691 CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) CP_COND_WRITE5_0_FUNCTION() argument 1703 CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val) CP_COND_WRITE5_1_POLL_ADDR_LO() argument 1711 CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val) CP_COND_WRITE5_2_POLL_ADDR_HI() argument 1719 CP_COND_WRITE5_3_REF(uint32_t val) CP_COND_WRITE5_3_REF() argument 1727 CP_COND_WRITE5_4_MASK(uint32_t val) CP_COND_WRITE5_4_MASK() argument 1735 CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val) CP_COND_WRITE5_5_WRITE_ADDR_LO() argument 1743 CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val) CP_COND_WRITE5_6_WRITE_ADDR_HI() argument 1751 CP_COND_WRITE5_7_WRITE_DATA(uint32_t val) CP_COND_WRITE5_7_WRITE_DATA() argument 1759 CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val) CP_WAIT_MEM_GTE_0_RESERVED() argument 1767 CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val) CP_WAIT_MEM_GTE_1_POLL_ADDR_LO() argument 1775 CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val) CP_WAIT_MEM_GTE_2_POLL_ADDR_HI() argument 1783 CP_WAIT_MEM_GTE_3_REF(uint32_t val) CP_WAIT_MEM_GTE_3_REF() argument 1791 CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val) CP_WAIT_REG_MEM_0_FUNCTION() argument 1803 CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val) CP_WAIT_REG_MEM_1_POLL_ADDR_LO() argument 1811 CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val) CP_WAIT_REG_MEM_2_POLL_ADDR_HI() argument 1819 CP_WAIT_REG_MEM_3_REF(uint32_t val) CP_WAIT_REG_MEM_3_REF() argument 1827 CP_WAIT_REG_MEM_4_MASK(uint32_t val) CP_WAIT_REG_MEM_4_MASK() argument 1835 CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val) CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES() argument 1843 CP_WAIT_TWO_REGS_0_REG0(uint32_t val) CP_WAIT_TWO_REGS_0_REG0() argument 1851 CP_WAIT_TWO_REGS_1_REG1(uint32_t val) CP_WAIT_TWO_REGS_1_REG1() argument 1859 CP_WAIT_TWO_REGS_2_REF(uint32_t val) CP_WAIT_TWO_REGS_2_REF() argument 1869 CP_DISPATCH_COMPUTE_1_X(uint32_t val) CP_DISPATCH_COMPUTE_1_X() argument 1877 CP_DISPATCH_COMPUTE_2_Y(uint32_t val) CP_DISPATCH_COMPUTE_2_Y() argument 1885 CP_DISPATCH_COMPUTE_3_Z(uint32_t val) CP_DISPATCH_COMPUTE_3_Z() argument 1893 CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) CP_SET_RENDER_MODE_0_MODE() argument 1901 CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) CP_SET_RENDER_MODE_1_ADDR_0_LO() argument 1909 CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) CP_SET_RENDER_MODE_2_ADDR_0_HI() argument 1923 CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) CP_SET_RENDER_MODE_5_ADDR_1_LEN() argument 1931 CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) CP_SET_RENDER_MODE_6_ADDR_1_LO() argument 1939 CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) CP_SET_RENDER_MODE_7_ADDR_1_HI() argument 1947 CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val) CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO() argument 1955 CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI() argument 1965 CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val) CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN() argument 1975 CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val) CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO() argument 1983 CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val) CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI() argument 1995 CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) CP_PERFCOUNTER_ACTION_1_ADDR_0_LO() argument 2003 CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) CP_PERFCOUNTER_ACTION_2_ADDR_0_HI() argument 2011 CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) CP_EVENT_WRITE_0_EVENT() argument 2021 CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) CP_EVENT_WRITE_1_ADDR_0_LO() argument 2029 CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) CP_EVENT_WRITE_2_ADDR_0_HI() argument 2039 CP_BLIT_0_OP(enum cp_blit_cmd val) CP_BLIT_0_OP() argument 2047 CP_BLIT_1_SRC_X1(uint32_t val) CP_BLIT_1_SRC_X1() argument 2053 CP_BLIT_1_SRC_Y1(uint32_t val) CP_BLIT_1_SRC_Y1() argument 2061 CP_BLIT_2_SRC_X2(uint32_t val) CP_BLIT_2_SRC_X2() argument 2067 CP_BLIT_2_SRC_Y2(uint32_t val) CP_BLIT_2_SRC_Y2() argument 2075 CP_BLIT_3_DST_X1(uint32_t val) CP_BLIT_3_DST_X1() argument 2081 CP_BLIT_3_DST_Y1(uint32_t val) CP_BLIT_3_DST_Y1() argument 2089 CP_BLIT_4_DST_X2(uint32_t val) CP_BLIT_4_DST_X2() argument 2095 CP_BLIT_4_DST_Y2(uint32_t val) CP_BLIT_4_DST_Y2() argument 2105 CP_EXEC_CS_1_NGROUPS_X(uint32_t val) CP_EXEC_CS_1_NGROUPS_X() argument 2113 CP_EXEC_CS_2_NGROUPS_Y(uint32_t val) CP_EXEC_CS_2_NGROUPS_Y() argument 2121 CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) CP_EXEC_CS_3_NGROUPS_Z() argument 2132 A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val) A4XX_CP_EXEC_CS_INDIRECT_1_ADDR() argument 2140 A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val) A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX() argument 2146 A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val) A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY() argument 2152 A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ() argument 2161 A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO() argument 2169 A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI() argument 2177 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX() argument 2183 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY() argument 2189 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ() argument 2197 A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val) A6XX_CP_SET_MARKER_0_MODE() argument 2203 A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val) A6XX_CP_SET_MARKER_0_MARKER() argument 2213 A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG() argument 2221 A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val) A6XX_CP_SET_PSEUDO_REG__1_LO() argument 2229 A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val) A6XX_CP_SET_PSEUDO_REG__2_HI() argument 2237 A6XX_CP_REG_TEST_0_REG(uint32_t val) A6XX_CP_REG_TEST_0_REG() argument 2243 A6XX_CP_REG_TEST_0_BIT(uint32_t val) A6XX_CP_REG_TEST_0_BIT() argument 2250 A6XX_CP_REG_TEST_0_PRED_BIT(uint32_t val) A6XX_CP_REG_TEST_0_PRED_BIT() argument 2263 CP_COND_REG_EXEC_0_REG0(uint32_t val) CP_COND_REG_EXEC_0_REG0() argument 2269 CP_COND_REG_EXEC_0_PRED_BIT(uint32_t val) CP_COND_REG_EXEC_0_PRED_BIT() argument 2278 CP_COND_REG_EXEC_0_MODE(enum compare_mode val) CP_COND_REG_EXEC_0_MODE() argument 2286 CP_COND_REG_EXEC_1_DWORDS(uint32_t val) CP_COND_REG_EXEC_1_DWORDS() argument 2294 CP_COND_EXEC_0_ADDR0_LO(uint32_t val) CP_COND_EXEC_0_ADDR0_LO() argument 2302 CP_COND_EXEC_1_ADDR0_HI(uint32_t val) CP_COND_EXEC_1_ADDR0_HI() argument 2310 CP_COND_EXEC_2_ADDR1_LO(uint32_t val) CP_COND_EXEC_2_ADDR1_LO() argument 2318 CP_COND_EXEC_3_ADDR1_HI(uint32_t val) CP_COND_EXEC_3_ADDR1_HI() argument 2326 CP_COND_EXEC_4_REF(uint32_t val) CP_COND_EXEC_4_REF() argument 2334 CP_COND_EXEC_5_DWORDS(uint32_t val) CP_COND_EXEC_5_DWORDS() argument 2342 CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val) CP_SET_CTXSWITCH_IB_0_ADDR_LO() argument 2350 CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val) CP_SET_CTXSWITCH_IB_1_ADDR_HI() argument 2358 CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val) CP_SET_CTXSWITCH_IB_2_DWORDS() argument 2364 CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val) CP_SET_CTXSWITCH_IB_2_TYPE() argument 2372 CP_REG_WRITE_0_TRACKER(enum reg_tracker val) CP_REG_WRITE_0_TRACKER() argument 2384 CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val) CP_SMMU_TABLE_UPDATE_0_TTBR0_LO() argument 2392 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val) CP_SMMU_TABLE_UPDATE_1_TTBR0_HI() argument 2398 CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val) CP_SMMU_TABLE_UPDATE_1_ASID() argument 2406 CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val) CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR() argument 2414 CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val) CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK() argument 2436 CP_THREAD_CONTROL_0_THREAD(enum cp_thread val) CP_THREAD_CONTROL_0_THREAD() argument [all...]
H A D	a3xx.xml.h	947 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() argument 949 return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK; in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() 955 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument 957 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() 961 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument 963 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() 969 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET() argument 971 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; in A3XX_GRAS_CL_VPORT_XOFFSET() 977 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE() argument 979 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIF in A3XX_GRAS_CL_VPORT_XSCALE() 985 A3XX_GRAS_CL_VPORT_YOFFSET(float val) A3XX_GRAS_CL_VPORT_YOFFSET() argument 993 A3XX_GRAS_CL_VPORT_YSCALE(float val) A3XX_GRAS_CL_VPORT_YSCALE() argument 1001 A3XX_GRAS_CL_VPORT_ZOFFSET(float val) A3XX_GRAS_CL_VPORT_ZOFFSET() argument 1009 A3XX_GRAS_CL_VPORT_ZSCALE(float val) A3XX_GRAS_CL_VPORT_ZSCALE() argument 1017 A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) A3XX_GRAS_SU_POINT_MINMAX_MIN() argument 1023 A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) A3XX_GRAS_SU_POINT_MINMAX_MAX() argument 1031 A3XX_GRAS_SU_POINT_SIZE(float val) A3XX_GRAS_SU_POINT_SIZE() argument 1039 A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL() argument 1047 A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) A3XX_GRAS_SU_POLY_OFFSET_OFFSET() argument 1058 A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH() argument 1067 A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) A3XX_GRAS_SC_CONTROL_RENDER_MODE() argument 1073 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES() argument 1079 A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) A3XX_GRAS_SC_CONTROL_RASTER_MODE() argument 1088 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X() argument 1094 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y() argument 1103 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X() argument 1109 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y() argument 1118 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X() argument 1124 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y() argument 1133 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X() argument 1139 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y() argument 1148 A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) A3XX_RB_MODE_CONTROL_RENDER_MODE() argument 1154 A3XX_RB_MODE_CONTROL_MRT(uint32_t val) A3XX_RB_MODE_CONTROL_MRT() argument 1168 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) A3XX_RB_RENDER_CONTROL_BIN_WIDTH() argument 1176 A3XX_RB_RENDER_CONTROL_COORD_MASK(uint32_t val) A3XX_RB_RENDER_CONTROL_COORD_MASK() argument 1185 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC() argument 1196 A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) A3XX_RB_MSAA_CONTROL_SAMPLES() argument 1202 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) A3XX_RB_MSAA_CONTROL_SAMPLE_MASK() argument 1210 A3XX_RB_ALPHA_REF_UINT(uint32_t val) A3XX_RB_ALPHA_REF_UINT() argument 1216 A3XX_RB_ALPHA_REF_FLOAT(float val) A3XX_RB_ALPHA_REF_FLOAT() argument 1229 A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) A3XX_RB_MRT_CONTROL_ROP_CODE() argument 1235 A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) A3XX_RB_MRT_CONTROL_DITHER_MODE() argument 1241 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE() argument 1249 A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT() argument 1255 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE() argument 1261 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) A3XX_RB_MRT_BUF_INFO_COLOR_SWAP() argument 1268 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH() argument 1276 A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE() argument 1284 A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR() argument 1290 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE() argument 1296 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR() argument 1302 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR() argument 1308 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE() argument 1314 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR() argument 1323 A3XX_RB_BLEND_RED_UINT(uint32_t val) A3XX_RB_BLEND_RED_UINT() argument 1329 A3XX_RB_BLEND_RED_FLOAT(float val) A3XX_RB_BLEND_RED_FLOAT() argument 1337 A3XX_RB_BLEND_GREEN_UINT(uint32_t val) A3XX_RB_BLEND_GREEN_UINT() argument 1343 A3XX_RB_BLEND_GREEN_FLOAT(float val) A3XX_RB_BLEND_GREEN_FLOAT() argument 1351 A3XX_RB_BLEND_BLUE_UINT(uint32_t val) A3XX_RB_BLEND_BLUE_UINT() argument 1357 A3XX_RB_BLEND_BLUE_FLOAT(float val) A3XX_RB_BLEND_BLUE_FLOAT() argument 1365 A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) A3XX_RB_BLEND_ALPHA_UINT() argument 1371 A3XX_RB_BLEND_ALPHA_FLOAT(float val) A3XX_RB_BLEND_ALPHA_FLOAT() argument 1387 A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) A3XX_RB_COPY_CONTROL_MSAA_RESOLVE() argument 1394 A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) A3XX_RB_COPY_CONTROL_MODE() argument 1401 A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) A3XX_RB_COPY_CONTROL_FASTCLEAR() argument 1408 A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) A3XX_RB_COPY_CONTROL_GMEM_BASE() argument 1416 A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) A3XX_RB_COPY_DEST_BASE_BASE() argument 1424 A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) A3XX_RB_COPY_DEST_PITCH_PITCH() argument 1432 A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) A3XX_RB_COPY_DEST_INFO_TILE() argument 1438 A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) A3XX_RB_COPY_DEST_INFO_FORMAT() argument 1444 A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) A3XX_RB_COPY_DEST_INFO_SWAP() argument 1450 A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) A3XX_RB_COPY_DEST_INFO_DITHER_MODE() argument 1456 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE() argument 1462 A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) A3XX_RB_COPY_DEST_INFO_ENDIAN() argument 1474 A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) A3XX_RB_DEPTH_CONTROL_ZFUNC() argument 1486 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) A3XX_RB_DEPTH_INFO_DEPTH_FORMAT() argument 1492 A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) A3XX_RB_DEPTH_INFO_DEPTH_BASE() argument 1500 A3XX_RB_DEPTH_PITCH(uint32_t val) A3XX_RB_DEPTH_PITCH() argument 1511 A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) A3XX_RB_STENCIL_CONTROL_FUNC() argument 1517 A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_FAIL() argument 1523 A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZPASS() argument 1529 A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZFAIL() argument 1535 A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) A3XX_RB_STENCIL_CONTROL_FUNC_BF() argument 1541 A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_FAIL_BF() argument 1547 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZPASS_BF() argument 1553 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZFAIL_BF() argument 1563 A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) A3XX_RB_STENCIL_INFO_STENCIL_BASE() argument 1571 A3XX_RB_STENCIL_PITCH(uint32_t val) A3XX_RB_STENCIL_PITCH() argument 1579 A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) A3XX_RB_STENCILREFMASK_STENCILREF() argument 1585 A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) A3XX_RB_STENCILREFMASK_STENCILMASK() argument 1591 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) A3XX_RB_STENCILREFMASK_STENCILWRITEMASK() argument 1599 A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) A3XX_RB_STENCILREFMASK_BF_STENCILREF() argument 1605 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) A3XX_RB_STENCILREFMASK_BF_STENCILMASK() argument 1611 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK() argument 1622 A3XX_RB_WINDOW_OFFSET_X(uint32_t val) A3XX_RB_WINDOW_OFFSET_X() argument 1628 A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) A3XX_RB_WINDOW_OFFSET_Y() argument 1650 A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) A3XX_PC_VSTREAM_CONTROL_SIZE() argument 1656 A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) A3XX_PC_VSTREAM_CONTROL_N() argument 1666 A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC() argument 1672 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE() argument 1678 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE() argument 1692 A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE() argument 1702 A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val) A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC() argument 1710 A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) A3XX_HLSQ_CONTROL_0_REG_CONSTMODE() argument 1722 A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE() argument 1729 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val) A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID() argument 1735 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val) A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID() argument 1743 A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val) A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID() argument 1749 A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val) A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID() argument 1755 A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD() argument 1763 A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(uint32_t val) A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID() argument 1769 A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(uint32_t val) A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID() argument 1775 A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(uint32_t val) A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID() argument 1781 A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(uint32_t val) A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID() argument 1789 A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH() argument 1795 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET() argument 1801 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH() argument 1809 A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH() argument 1815 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET() argument 1821 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH() argument 1829 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY() argument 1835 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY() argument 1843 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY() argument 1849 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY() argument 1857 A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM() argument 1863 A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0() argument 1869 A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1() argument 1875 A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2() argument 1905 A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) A3XX_VFD_CONTROL_0_TOTALATTRTOVS() argument 1911 A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) A3XX_VFD_CONTROL_0_PACKETSIZE() argument 1917 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) A3XX_VFD_CONTROL_0_STRMDECINSTRCNT() argument 1923 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT() argument 1931 A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) A3XX_VFD_CONTROL_1_MAXSTORAGE() argument 1937 A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val) A3XX_VFD_CONTROL_1_MAXTHRESHOLD() argument 1943 A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val) A3XX_VFD_CONTROL_1_MINTHRESHOLD() argument 1949 A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) A3XX_VFD_CONTROL_1_REGID4VTX() argument 1955 A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) A3XX_VFD_CONTROL_1_REGID4INST() argument 1973 A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_FETCHSIZE() argument 1979 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE() argument 1987 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_INDEXCODE() argument 1993 A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_STEPRATE() argument 2005 A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) A3XX_VFD_DECODE_INSTR_WRITEMASK() argument 2012 A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) A3XX_VFD_DECODE_INSTR_FORMAT() argument 2018 A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) A3XX_VFD_DECODE_INSTR_REGID() argument 2025 A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) A3XX_VFD_DECODE_INSTR_SWAP() argument 2031 A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) A3XX_VFD_DECODE_INSTR_SHIFTCNT() argument 2041 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD() argument 2047 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT() argument 2055 A3XX_VPC_ATTR_TOTALATTR(uint32_t val) A3XX_VPC_ATTR_TOTALATTR() argument 2062 A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) A3XX_VPC_ATTR_THRDASSIGN() argument 2068 A3XX_VPC_ATTR_LMSIZE(uint32_t val) A3XX_VPC_ATTR_LMSIZE() argument 2076 A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) A3XX_VPC_PACK_NUMFPNONPOSVAR() argument 2082 A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) A3XX_VPC_PACK_NUMNONPOSVSVAR() argument 2092 A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C0() argument 2098 A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C1() argument 2104 A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C2() argument 2110 A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C3() argument 2116 A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C4() argument 2122 A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C5() argument 2128 A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C6() argument 2134 A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C7() argument 2140 A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C8() argument 2146 A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C9() argument 2152 A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CA() argument 2158 A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CB() argument 2164 A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CC() argument 2170 A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CD() argument 2176 A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CE() argument 2182 A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CF() argument 2192 A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C0() argument 2198 A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C1() argument 2204 A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C2() argument 2210 A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C3() argument 2216 A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C4() argument 2222 A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C5() argument 2228 A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C6() argument 2234 A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C7() argument 2240 A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C8() argument 2246 A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C9() argument 2252 A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CA() argument 2258 A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CB() argument 2264 A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CC() argument 2270 A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CD() argument 2276 A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CE() argument 2282 A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CF() argument 2295 A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) A3XX_SP_SP_CTRL_REG_CONSTMODE() argument 2302 A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) A3XX_SP_SP_CTRL_REG_SLEEPMODE() argument 2308 A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) A3XX_SP_SP_CTRL_REG_L0MODE() argument 2316 A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A3XX_SP_VS_CTRL_REG0_THREADMODE() argument 2322 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE() argument 2330 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT() argument 2336 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT() argument 2342 A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A3XX_SP_VS_CTRL_REG0_THREADSIZE() argument 2349 A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) A3XX_SP_VS_CTRL_REG0_LENGTH() argument 2357 A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) A3XX_SP_VS_CTRL_REG1_CONSTLENGTH() argument 2363 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT() argument 2369 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING() argument 2377 A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) A3XX_SP_VS_PARAM_REG_POSREGID() argument 2383 A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) A3XX_SP_VS_PARAM_REG_PSIZEREGID() argument 2390 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR() argument 2400 A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) A3XX_SP_VS_OUT_REG_A_REGID() argument 2407 A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) A3XX_SP_VS_OUT_REG_A_COMPMASK() argument 2413 A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) A3XX_SP_VS_OUT_REG_B_REGID() argument 2420 A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) A3XX_SP_VS_OUT_REG_B_COMPMASK() argument 2430 A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC0() argument 2436 A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC1() argument 2442 A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC2() argument 2448 A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC3() argument 2456 A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET() argument 2462 A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument 2468 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument 2478 A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM() argument 2484 A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET() argument 2490 A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD() argument 2498 A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN() argument 2504 A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS() argument 2514 A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) A3XX_SP_VS_LENGTH_REG_SHADERLENGTH() argument 2522 A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A3XX_SP_FS_CTRL_REG0_THREADMODE() argument 2528 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE() argument 2536 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT() argument 2542 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT() argument 2551 A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A3XX_SP_FS_CTRL_REG0_THREADSIZE() argument 2560 A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) A3XX_SP_FS_CTRL_REG0_LENGTH() argument 2568 A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) A3XX_SP_FS_CTRL_REG1_CONSTLENGTH() argument 2574 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT() argument 2580 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING() argument 2586 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET() argument 2594 A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET() argument 2600 A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument 2606 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument 2616 A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM() argument 2622 A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET() argument 2628 A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD() argument 2636 A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN() argument 2642 A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS() argument 2656 A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) A3XX_SP_FS_OUTPUT_REG_MRT() argument 2663 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID() argument 2673 A3XX_SP_FS_MRT_REG_REGID(uint32_t val) A3XX_SP_FS_MRT_REG_REGID() argument 2686 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT() argument 2694 A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) A3XX_SP_FS_LENGTH_REG_SHADERLENGTH() argument 2704 A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET() argument 2710 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET() argument 2716 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR() argument 2726 A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET() argument 2732 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET() argument 2738 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR() argument 2822 A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) A3XX_VSC_BIN_SIZE_WIDTH() argument 2828 A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) A3XX_VSC_BIN_SIZE_HEIGHT() argument 2840 A3XX_VSC_PIPE_CONFIG_X(uint32_t val) A3XX_VSC_PIPE_CONFIG_X() argument 2846 A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) A3XX_VSC_PIPE_CONFIG_Y() argument 2852 A3XX_VSC_PIPE_CONFIG_W(uint32_t val) A3XX_VSC_PIPE_CONFIG_W() argument 2858 A3XX_VSC_PIPE_CONFIG_H(uint32_t val) A3XX_VSC_PIPE_CONFIG_H() argument 2911 A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument 2917 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument 2965 A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR() argument 2973 A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR() argument 2979 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE() argument 3026 A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE() argument 3032 A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT() argument 3038 A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) A3XX_VGT_DRAW_INITIATOR_VIS_CULL() argument 3044 A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE() argument 3053 A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES() argument 3065 A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) A3XX_TEX_SAMP_0_XY_MAG() argument 3071 A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) A3XX_TEX_SAMP_0_XY_MIN() argument 3077 A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) A3XX_TEX_SAMP_0_WRAP_S() argument 3083 A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) A3XX_TEX_SAMP_0_WRAP_T() argument 3089 A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) A3XX_TEX_SAMP_0_WRAP_R() argument 3095 A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) A3XX_TEX_SAMP_0_ANISO() argument 3101 A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) A3XX_TEX_SAMP_0_COMPARE_FUNC() argument 3111 A3XX_TEX_SAMP_1_LOD_BIAS(float val) A3XX_TEX_SAMP_1_LOD_BIAS() argument 3117 A3XX_TEX_SAMP_1_MAX_LOD(float val) A3XX_TEX_SAMP_1_MAX_LOD() argument 3123 A3XX_TEX_SAMP_1_MIN_LOD(float val) A3XX_TEX_SAMP_1_MIN_LOD() argument 3131 A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val) A3XX_TEX_CONST_0_TILE_MODE() argument 3138 A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_X() argument 3144 A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_Y() argument 3150 A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_Z() argument 3156 A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_W() argument 3162 A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) A3XX_TEX_CONST_0_MIPLVLS() argument 3168 A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val) A3XX_TEX_CONST_0_MSAATEX() argument 3174 A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) A3XX_TEX_CONST_0_FMT() argument 3181 A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) A3XX_TEX_CONST_0_TYPE() argument 3189 A3XX_TEX_CONST_1_HEIGHT(uint32_t val) A3XX_TEX_CONST_1_HEIGHT() argument 3195 A3XX_TEX_CONST_1_WIDTH(uint32_t val) A3XX_TEX_CONST_1_WIDTH() argument 3201 A3XX_TEX_CONST_1_PITCHALIGN(uint32_t val) A3XX_TEX_CONST_1_PITCHALIGN() argument 3209 A3XX_TEX_CONST_2_INDX(uint32_t val) A3XX_TEX_CONST_2_INDX() argument 3215 A3XX_TEX_CONST_2_PITCH(uint32_t val) A3XX_TEX_CONST_2_PITCH() argument 3221 A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) A3XX_TEX_CONST_2_SWAP() argument 3229 A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) A3XX_TEX_CONST_3_LAYERSZ1() argument 3235 A3XX_TEX_CONST_3_DEPTH(uint32_t val) A3XX_TEX_CONST_3_DEPTH() argument 3241 A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) A3XX_TEX_CONST_3_LAYERSZ2() argument [all...]
H A D	a6xx.xml.h	1123 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_MRB_START() argument 1125 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK; in A6XX_CP_ROQ_THRESHOLDS_1_MRB_START() 1129 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_VSD_START() argument 1131 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK; in A6XX_CP_ROQ_THRESHOLDS_1_VSD_START() 1135 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START() argument 1137 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START() 1141 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START() argument 1143 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START() 1149 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START() argument 1151 return ((val >> in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START() 1155 A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE() argument 1182 A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) A6XX_CP_PROTECT_REG_BASE_ADDR() argument 1188 A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) A6XX_CP_PROTECT_REG_MASK_LEN() argument 1257 A6XX_CP_ROQ_RB_STAT_RPTR(uint32_t val) A6XX_CP_ROQ_RB_STAT_RPTR() argument 1263 A6XX_CP_ROQ_RB_STAT_WPTR(uint32_t val) A6XX_CP_ROQ_RB_STAT_WPTR() argument 1271 A6XX_CP_ROQ_IB1_STAT_RPTR(uint32_t val) A6XX_CP_ROQ_IB1_STAT_RPTR() argument 1277 A6XX_CP_ROQ_IB1_STAT_WPTR(uint32_t val) A6XX_CP_ROQ_IB1_STAT_WPTR() argument 1285 A6XX_CP_ROQ_IB2_STAT_RPTR(uint32_t val) A6XX_CP_ROQ_IB2_STAT_RPTR() argument 1291 A6XX_CP_ROQ_IB2_STAT_WPTR(uint32_t val) A6XX_CP_ROQ_IB2_STAT_WPTR() argument 1299 A6XX_CP_ROQ_SDS_STAT_RPTR(uint32_t val) A6XX_CP_ROQ_SDS_STAT_RPTR() argument 1305 A6XX_CP_ROQ_SDS_STAT_WPTR(uint32_t val) A6XX_CP_ROQ_SDS_STAT_WPTR() argument 1313 A6XX_CP_ROQ_MRB_STAT_RPTR(uint32_t val) A6XX_CP_ROQ_MRB_STAT_RPTR() argument 1319 A6XX_CP_ROQ_MRB_STAT_WPTR(uint32_t val) A6XX_CP_ROQ_MRB_STAT_WPTR() argument 1327 A6XX_CP_ROQ_VSD_STAT_RPTR(uint32_t val) A6XX_CP_ROQ_VSD_STAT_RPTR() argument 1333 A6XX_CP_ROQ_VSD_STAT_WPTR(uint32_t val) A6XX_CP_ROQ_VSD_STAT_WPTR() argument 1351 A6XX_CP_ROQ_AVAIL_RB_REM(uint32_t val) A6XX_CP_ROQ_AVAIL_RB_REM() argument 1359 A6XX_CP_ROQ_AVAIL_IB1_REM(uint32_t val) A6XX_CP_ROQ_AVAIL_IB1_REM() argument 1367 A6XX_CP_ROQ_AVAIL_IB2_REM(uint32_t val) A6XX_CP_ROQ_AVAIL_IB2_REM() argument 1375 A6XX_CP_ROQ_AVAIL_SDS_REM(uint32_t val) A6XX_CP_ROQ_AVAIL_SDS_REM() argument 1383 A6XX_CP_ROQ_AVAIL_MRB_REM(uint32_t val) A6XX_CP_ROQ_AVAIL_MRB_REM() argument 1391 A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) A6XX_CP_ROQ_AVAIL_VSD_REM() argument 1953 A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX() argument 1959 A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL() argument 1967 A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN() argument 1973 A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU() argument 1979 A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT() argument 1987 A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE() argument 2011 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0() argument 2017 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1() argument 2023 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2() argument 2029 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3() argument 2035 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4() argument 2041 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5() argument 2047 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6() argument 2053 A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7() argument 2061 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8() argument 2067 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9() argument 2073 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10() argument 2079 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11() argument 2085 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12() argument 2091 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13() argument 2097 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14() argument 2103 A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15() argument 2139 A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) A6XX_UCHE_CLIENT_PF_PERFSEL() argument 2168 A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL() argument 2178 A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL() argument 2284 A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) A6XX_VSC_BIN_SIZE_WIDTH() argument 2290 A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) A6XX_VSC_BIN_SIZE_HEIGHT() argument 2300 A6XX_VSC_BIN_COUNT_NX(uint32_t val) A6XX_VSC_BIN_COUNT_NX() argument 2306 A6XX_VSC_BIN_COUNT_NY(uint32_t val) A6XX_VSC_BIN_COUNT_NY() argument 2316 A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) A6XX_VSC_PIPE_CONFIG_REG_X() argument 2322 A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) A6XX_VSC_PIPE_CONFIG_REG_Y() argument 2328 A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) A6XX_VSC_PIPE_CONFIG_REG_W() argument 2334 A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) A6XX_VSC_PIPE_CONFIG_REG_H() argument 2378 A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) A6XX_GRAS_VS_CL_CNTL_CLIP_MASK() argument 2384 A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) A6XX_GRAS_VS_CL_CNTL_CULL_MASK() argument 2392 A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val) A6XX_GRAS_DS_CL_CNTL_CLIP_MASK() argument 2398 A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val) A6XX_GRAS_DS_CL_CNTL_CULL_MASK() argument 2406 A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val) A6XX_GRAS_GS_CL_CNTL_CLIP_MASK() argument 2412 A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val) A6XX_GRAS_GS_CL_CNTL_CULL_MASK() argument 2428 A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) A6XX_GRAS_CNTL_COORD_MASK() argument 2436 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ() argument 2442 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT() argument 2452 A6XX_GRAS_CL_VPORT_XOFFSET(float val) A6XX_GRAS_CL_VPORT_XOFFSET() argument 2460 A6XX_GRAS_CL_VPORT_XSCALE(float val) A6XX_GRAS_CL_VPORT_XSCALE() argument 2468 A6XX_GRAS_CL_VPORT_YOFFSET(float val) A6XX_GRAS_CL_VPORT_YOFFSET() argument 2476 A6XX_GRAS_CL_VPORT_YSCALE(float val) A6XX_GRAS_CL_VPORT_YSCALE() argument 2484 A6XX_GRAS_CL_VPORT_ZOFFSET(float val) A6XX_GRAS_CL_VPORT_ZOFFSET() argument 2492 A6XX_GRAS_CL_VPORT_ZSCALE(float val) A6XX_GRAS_CL_VPORT_ZSCALE() argument 2502 A6XX_GRAS_CL_Z_CLAMP_MIN(float val) A6XX_GRAS_CL_Z_CLAMP_MIN() argument 2510 A6XX_GRAS_CL_Z_CLAMP_MAX(float val) A6XX_GRAS_CL_Z_CLAMP_MAX() argument 2521 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) A6XX_GRAS_SU_CNTL_LINEHALFWIDTH() argument 2528 A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) A6XX_GRAS_SU_CNTL_UNK12() argument 2534 A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) A6XX_GRAS_SU_CNTL_LINE_MODE() argument 2540 A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) A6XX_GRAS_SU_CNTL_UNK15() argument 2548 A6XX_GRAS_SU_CNTL_UNK19(uint32_t val) A6XX_GRAS_SU_CNTL_UNK19() argument 2556 A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) A6XX_GRAS_SU_POINT_MINMAX_MIN() argument 2562 A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) A6XX_GRAS_SU_POINT_MINMAX_MAX() argument 2570 A6XX_GRAS_SU_POINT_SIZE(float val) A6XX_GRAS_SU_POINT_SIZE() argument 2578 A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE() argument 2586 A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) A6XX_GRAS_SU_POLY_OFFSET_SCALE() argument 2594 A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) A6XX_GRAS_SU_POLY_OFFSET_OFFSET() argument 2602 A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP() argument 2610 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT() argument 2616 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val) A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3() argument 2625 A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val) A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT() argument 2632 A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val) A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4() argument 2656 A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE() argument 2662 A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val) A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE() argument 2668 A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val) A6XX_GRAS_SC_CNTL_RASTER_MODE() argument 2674 A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) A6XX_GRAS_SC_CNTL_RASTER_DIRECTION() argument 2680 A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val) A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION() argument 2687 A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val) A6XX_GRAS_SC_CNTL_ROTATION() argument 2696 A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) A6XX_GRAS_BIN_CONTROL_BINW() argument 2702 A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) A6XX_GRAS_BIN_CONTROL_BINH() argument 2708 A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) A6XX_GRAS_BIN_CONTROL_RENDER_MODE() argument 2715 A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION() argument 2721 A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK() argument 2727 A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val) A6XX_GRAS_BIN_CONTROL_UNK27() argument 2735 A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES() argument 2741 A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val) A6XX_GRAS_RAS_MSAA_CNTL_UNK2() argument 2747 A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val) A6XX_GRAS_RAS_MSAA_CNTL_UNK3() argument 2755 A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES() argument 2768 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X() argument 2774 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y() argument 2780 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X() argument 2786 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y() argument 2792 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X() argument 2798 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y() argument 2804 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X() argument 2810 A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y() argument 2818 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X() argument 2824 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y() argument 2830 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X() argument 2836 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y() argument 2842 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X() argument 2848 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y() argument 2854 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X() argument 2860 A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y() argument 2872 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X() argument 2878 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y() argument 2886 A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X() argument 2892 A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y() argument 2902 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val) A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X() argument 2908 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val) A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y() argument 2916 A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val) A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X() argument 2922 A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val) A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y() argument 2930 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X() argument 2936 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y() argument 2944 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X() argument 2950 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y() argument 2964 A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val) A6XX_GRAS_LRZ_CNTL_DIR() argument 2975 A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE() argument 2983 A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val) A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT() argument 2991 A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val) A6XX_GRAS_LRZ_BUFFER_BASE() argument 2999 A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH() argument 3005 A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH() argument 3013 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val) A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE() argument 3024 A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(uint32_t val) A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER() argument 3030 A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(uint32_t val) A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT() argument 3036 A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val) A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL() argument 3046 A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) A6XX_GRAS_2D_BLIT_CNTL_ROTATE() argument 3053 A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val) A6XX_GRAS_2D_BLIT_CNTL_UNK4() argument 3060 A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT() argument 3067 A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val) A6XX_GRAS_2D_BLIT_CNTL_UNK17() argument 3074 A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val) A6XX_GRAS_2D_BLIT_CNTL_MASK() argument 3080 A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) A6XX_GRAS_2D_BLIT_CNTL_IFMT() argument 3086 A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE() argument 3102 A6XX_GRAS_2D_DST_TL_X(uint32_t val) A6XX_GRAS_2D_DST_TL_X() argument 3108 A6XX_GRAS_2D_DST_TL_Y(uint32_t val) A6XX_GRAS_2D_DST_TL_Y() argument 3116 A6XX_GRAS_2D_DST_BR_X(uint32_t val) A6XX_GRAS_2D_DST_BR_X() argument 3122 A6XX_GRAS_2D_DST_BR_Y(uint32_t val) A6XX_GRAS_2D_DST_BR_Y() argument 3136 A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val) A6XX_GRAS_2D_RESOLVE_CNTL_1_X() argument 3142 A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val) A6XX_GRAS_2D_RESOLVE_CNTL_1_Y() argument 3150 A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val) A6XX_GRAS_2D_RESOLVE_CNTL_2_X() argument 3156 A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) A6XX_GRAS_2D_RESOLVE_CNTL_2_Y() argument 3178 A6XX_RB_BIN_CONTROL_BINW(uint32_t val) A6XX_RB_BIN_CONTROL_BINW() argument 3184 A6XX_RB_BIN_CONTROL_BINH(uint32_t val) A6XX_RB_BIN_CONTROL_BINH() argument 3190 A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) A6XX_RB_BIN_CONTROL_RENDER_MODE() argument 3197 A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION() argument 3203 A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK() argument 3211 A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE() argument 3219 A6XX_RB_RENDER_CNTL_UNK8(uint32_t val) A6XX_RB_RENDER_CNTL_UNK8() argument 3225 A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) A6XX_RB_RENDER_CNTL_RASTER_MODE() argument 3231 A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) A6XX_RB_RENDER_CNTL_RASTER_DIRECTION() argument 3240 A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) A6XX_RB_RENDER_CNTL_FLAG_MRTS() argument 3248 A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A6XX_RB_RAS_MSAA_CNTL_SAMPLES() argument 3254 A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val) A6XX_RB_RAS_MSAA_CNTL_UNK2() argument 3260 A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val) A6XX_RB_RAS_MSAA_CNTL_UNK3() argument 3268 A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A6XX_RB_DEST_MSAA_CNTL_SAMPLES() argument 3281 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X() argument 3287 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y() argument 3293 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X() argument 3299 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y() argument 3305 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X() argument 3311 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y() argument 3317 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X() argument 3323 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y() argument 3331 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X() argument 3337 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y() argument 3343 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X() argument 3349 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y() argument 3355 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X() argument 3361 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y() argument 3367 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X() argument 3373 A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y() argument 3387 A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) A6XX_RB_RENDER_CONTROL0_COORD_MASK() argument 3400 A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE() argument 3417 A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) A6XX_RB_FS_OUTPUT_CNTL1_MRT() argument 3425 A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) A6XX_RB_RENDER_COMPONENTS_RT0() argument 3431 A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) A6XX_RB_RENDER_COMPONENTS_RT1() argument 3437 A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) A6XX_RB_RENDER_COMPONENTS_RT2() argument 3443 A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) A6XX_RB_RENDER_COMPONENTS_RT3() argument 3449 A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) A6XX_RB_RENDER_COMPONENTS_RT4() argument 3455 A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) A6XX_RB_RENDER_COMPONENTS_RT5() argument 3461 A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) A6XX_RB_RENDER_COMPONENTS_RT6() argument 3467 A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) A6XX_RB_RENDER_COMPONENTS_RT7() argument 3475 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0() argument 3481 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1() argument 3487 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2() argument 3493 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3() argument 3499 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4() argument 3505 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5() argument 3511 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6() argument 3517 A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7() argument 3559 A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) A6XX_RB_MRT_CONTROL_ROP_CODE() argument 3565 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE() argument 3573 A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR() argument 3579 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE() argument 3585 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR() argument 3591 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR() argument 3597 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE() argument 3603 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR() argument 3611 A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT() argument 3617 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE() argument 3623 A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val) A6XX_RB_MRT_BUF_INFO_UNK10() argument 3629 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) A6XX_RB_MRT_BUF_INFO_COLOR_SWAP() argument 3637 A6XX_RB_MRT_PITCH(uint32_t val) A6XX_RB_MRT_PITCH() argument 3645 A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) A6XX_RB_MRT_ARRAY_PITCH() argument 3653 A6XX_RB_MRT_BASE(uint32_t val) A6XX_RB_MRT_BASE() argument 3661 A6XX_RB_MRT_BASE_GMEM(uint32_t val) A6XX_RB_MRT_BASE_GMEM() argument 3669 A6XX_RB_BLEND_RED_F32(float val) A6XX_RB_BLEND_RED_F32() argument 3677 A6XX_RB_BLEND_GREEN_F32(float val) A6XX_RB_BLEND_GREEN_F32() argument 3685 A6XX_RB_BLEND_BLUE_F32(float val) A6XX_RB_BLEND_BLUE_F32() argument 3693 A6XX_RB_BLEND_ALPHA_F32(float val) A6XX_RB_BLEND_ALPHA_F32() argument 3701 A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) A6XX_RB_ALPHA_CONTROL_ALPHA_REF() argument 3708 A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC() argument 3716 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) A6XX_RB_BLEND_CNTL_ENABLE_BLEND() argument 3726 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) A6XX_RB_BLEND_CNTL_SAMPLE_MASK() argument 3734 A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE() argument 3744 A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) A6XX_RB_DEPTH_CNTL_ZFUNC() argument 3755 A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT() argument 3761 A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) A6XX_RB_DEPTH_BUFFER_INFO_UNK3() argument 3769 A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) A6XX_RB_DEPTH_BUFFER_PITCH() argument 3777 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH() argument 3785 A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val) A6XX_RB_DEPTH_BUFFER_BASE() argument 3793 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val) A6XX_RB_DEPTH_BUFFER_BASE_GMEM() argument 3801 A6XX_RB_Z_BOUNDS_MIN(float val) A6XX_RB_Z_BOUNDS_MIN() argument 3809 A6XX_RB_Z_BOUNDS_MAX(float val) A6XX_RB_Z_BOUNDS_MAX() argument 3820 A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) A6XX_RB_STENCIL_CONTROL_FUNC() argument 3826 A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) A6XX_RB_STENCIL_CONTROL_FAIL() argument 3832 A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) A6XX_RB_STENCIL_CONTROL_ZPASS() argument 3838 A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) A6XX_RB_STENCIL_CONTROL_ZFAIL() argument 3844 A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) A6XX_RB_STENCIL_CONTROL_FUNC_BF() argument 3850 A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) A6XX_RB_STENCIL_CONTROL_FAIL_BF() argument 3856 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) A6XX_RB_STENCIL_CONTROL_ZPASS_BF() argument 3862 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) A6XX_RB_STENCIL_CONTROL_ZFAIL_BF() argument 3874 A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) A6XX_RB_STENCIL_BUFFER_PITCH() argument 3882 A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH() argument 3890 A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val) A6XX_RB_STENCIL_BUFFER_BASE() argument 3898 A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val) A6XX_RB_STENCIL_BUFFER_BASE_GMEM() argument 3906 A6XX_RB_STENCILREF_REF(uint32_t val) A6XX_RB_STENCILREF_REF() argument 3912 A6XX_RB_STENCILREF_BFREF(uint32_t val) A6XX_RB_STENCILREF_BFREF() argument 3920 A6XX_RB_STENCILMASK_MASK(uint32_t val) A6XX_RB_STENCILMASK_MASK() argument 3926 A6XX_RB_STENCILMASK_BFMASK(uint32_t val) A6XX_RB_STENCILMASK_BFMASK() argument 3934 A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) A6XX_RB_STENCILWRMASK_WRMASK() argument 3940 A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) A6XX_RB_STENCILWRMASK_BFWRMASK() argument 3948 A6XX_RB_WINDOW_OFFSET_X(uint32_t val) A6XX_RB_WINDOW_OFFSET_X() argument 3954 A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) A6XX_RB_WINDOW_OFFSET_Y() argument 3969 A6XX_RB_Z_CLAMP_MIN(float val) A6XX_RB_Z_CLAMP_MIN() argument 3977 A6XX_RB_Z_CLAMP_MAX(float val) A6XX_RB_Z_CLAMP_MAX() argument 3985 A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val) A6XX_RB_UNKNOWN_88D0_UNK0() argument 3991 A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val) A6XX_RB_UNKNOWN_88D0_UNK16() argument 3999 A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) A6XX_RB_BLIT_SCISSOR_TL_X() argument 4005 A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) A6XX_RB_BLIT_SCISSOR_TL_Y() argument 4013 A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) A6XX_RB_BLIT_SCISSOR_BR_X() argument 4019 A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) A6XX_RB_BLIT_SCISSOR_BR_Y() argument 4027 A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) A6XX_RB_BIN_CONTROL2_BINW() argument 4033 A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) A6XX_RB_BIN_CONTROL2_BINH() argument 4041 A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) A6XX_RB_WINDOW_OFFSET2_X() argument 4047 A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) A6XX_RB_WINDOW_OFFSET2_Y() argument 4055 A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES() argument 4063 A6XX_RB_BLIT_BASE_GMEM(uint32_t val) A6XX_RB_BLIT_BASE_GMEM() argument 4071 A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) A6XX_RB_BLIT_DST_INFO_TILE_MODE() argument 4078 A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) A6XX_RB_BLIT_DST_INFO_SAMPLES() argument 4084 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) A6XX_RB_BLIT_DST_INFO_COLOR_SWAP() argument 4090 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT() argument 4099 A6XX_RB_BLIT_DST(uint32_t val) A6XX_RB_BLIT_DST() argument 4107 A6XX_RB_BLIT_DST_PITCH(uint32_t val) A6XX_RB_BLIT_DST_PITCH() argument 4115 A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) A6XX_RB_BLIT_DST_ARRAY_PITCH() argument 4123 A6XX_RB_BLIT_FLAG_DST(uint32_t val) A6XX_RB_BLIT_FLAG_DST() argument 4131 A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH() argument 4137 A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH() argument 4157 A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) A6XX_RB_BLIT_INFO_CLEAR_MASK() argument 4163 A6XX_RB_BLIT_INFO_LAST(uint32_t val) A6XX_RB_BLIT_INFO_LAST() argument 4169 A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val) A6XX_RB_BLIT_INFO_BUFFER_ID() argument 4179 A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val) A6XX_RB_UNK_FLAG_BUFFER_BASE() argument 4187 A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH() argument 4193 A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH() argument 4203 A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val) A6XX_RB_DEPTH_FLAG_BUFFER_BASE() argument 4211 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH() argument 4217 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8() argument 4223 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH() argument 4233 A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val) A6XX_RB_MRT_FLAG_BUFFER_ADDR() argument 4241 A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH() argument 4247 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH() argument 4255 A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val) A6XX_RB_SAMPLE_COUNT_ADDR() argument 4271 A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) A6XX_RB_2D_BLIT_CNTL_ROTATE() argument 4278 A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val) A6XX_RB_2D_BLIT_CNTL_UNK4() argument 4285 A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT() argument 4292 A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val) A6XX_RB_2D_BLIT_CNTL_UNK17() argument 4299 A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val) A6XX_RB_2D_BLIT_CNTL_MASK() argument 4305 A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) A6XX_RB_2D_BLIT_CNTL_IFMT() argument 4311 A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) A6XX_RB_2D_BLIT_CNTL_RASTER_MODE() argument 4321 A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) A6XX_RB_2D_DST_INFO_COLOR_FORMAT() argument 4327 A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) A6XX_RB_2D_DST_INFO_TILE_MODE() argument 4333 A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) A6XX_RB_2D_DST_INFO_COLOR_SWAP() argument 4341 A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) A6XX_RB_2D_DST_INFO_SAMPLES() argument 4354 A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) A6XX_RB_2D_DST_INFO_UNK23() argument 4363 A6XX_RB_2D_DST(uint32_t val) A6XX_RB_2D_DST() argument 4371 A6XX_RB_2D_DST_PITCH(uint32_t val) A6XX_RB_2D_DST_PITCH() argument 4379 A6XX_RB_2D_DST_PLANE1(uint32_t val) A6XX_RB_2D_DST_PLANE1() argument 4387 A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) A6XX_RB_2D_DST_PLANE_PITCH() argument 4395 A6XX_RB_2D_DST_PLANE2(uint32_t val) A6XX_RB_2D_DST_PLANE2() argument 4403 A6XX_RB_2D_DST_FLAGS(uint32_t val) A6XX_RB_2D_DST_FLAGS() argument 4411 A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) A6XX_RB_2D_DST_FLAGS_PITCH() argument 4419 A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val) A6XX_RB_2D_DST_FLAGS_PLANE() argument 4427 A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) A6XX_RB_2D_DST_FLAGS_PLANE_PITCH() argument 4450 A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(uint32_t val) A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI() argument 4456 A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val) A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI() argument 4462 A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val) A6XX_RB_CCU_CNTL_DEPTH_OFFSET() argument 4469 A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val) A6XX_RB_CCU_CNTL_COLOR_OFFSET() argument 4478 A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val) A6XX_RB_NC_MODE_CNTL_LOWER_BIT() argument 4486 A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val) A6XX_RB_NC_MODE_CNTL_UPPER_BIT() argument 4493 A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) A6XX_RB_NC_MODE_CNTL_UNK12() argument 4517 A6XX_RB_UNKNOWN_8E51(uint32_t val) A6XX_RB_UNKNOWN_8E51() argument 4525 A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val) A6XX_VPC_GS_PARAM_LINELENGTHLOC() argument 4533 A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val) A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK() argument 4539 A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC() argument 4545 A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC() argument 4553 A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val) A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK() argument 4559 A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC() argument 4565 A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC() argument 4573 A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val) A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK() argument 4579 A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC() argument 4585 A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC() argument 4593 A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val) A6XX_VPC_VS_LAYER_CNTL_LAYERLOC() argument 4599 A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) A6XX_VPC_VS_LAYER_CNTL_VIEWLOC() argument 4607 A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val) A6XX_VPC_GS_LAYER_CNTL_LAYERLOC() argument 4613 A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) A6XX_VPC_GS_LAYER_CNTL_VIEWLOC() argument 4621 A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val) A6XX_VPC_DS_LAYER_CNTL_LAYERLOC() argument 4627 A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) A6XX_VPC_DS_LAYER_CNTL_VIEWLOC() argument 4639 A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) A6XX_VPC_POLYGON_MODE_MODE() argument 4663 A6XX_VPC_SO_CNTL_ADDR(uint32_t val) A6XX_VPC_SO_CNTL_ADDR() argument 4672 A6XX_VPC_SO_PROG_A_BUF(uint32_t val) A6XX_VPC_SO_PROG_A_BUF() argument 4678 A6XX_VPC_SO_PROG_A_OFF(uint32_t val) A6XX_VPC_SO_PROG_A_OFF() argument 4685 A6XX_VPC_SO_PROG_B_BUF(uint32_t val) A6XX_VPC_SO_PROG_B_BUF() argument 4691 A6XX_VPC_SO_PROG_B_OFF(uint32_t val) A6XX_VPC_SO_PROG_B_OFF() argument 4700 A6XX_VPC_SO_STREAM_COUNTS(uint32_t val) A6XX_VPC_SO_STREAM_COUNTS() argument 4710 A6XX_VPC_SO_BUFFER_BASE(uint32_t val) A6XX_VPC_SO_BUFFER_BASE() argument 4718 A6XX_VPC_SO_BUFFER_SIZE(uint32_t val) A6XX_VPC_SO_BUFFER_SIZE() argument 4726 A6XX_VPC_SO_BUFFER_STRIDE(uint32_t val) A6XX_VPC_SO_BUFFER_STRIDE() argument 4734 A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val) A6XX_VPC_SO_BUFFER_OFFSET() argument 4742 A6XX_VPC_SO_FLUSH_BASE(uint32_t val) A6XX_VPC_SO_FLUSH_BASE() argument 4755 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val) A6XX_VPC_VS_PACK_STRIDE_IN_VPC() argument 4761 A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val) A6XX_VPC_VS_PACK_POSITIONLOC() argument 4767 A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) A6XX_VPC_VS_PACK_PSIZELOC() argument 4773 A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val) A6XX_VPC_VS_PACK_EXTRAPOS() argument 4781 A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val) A6XX_VPC_GS_PACK_STRIDE_IN_VPC() argument 4787 A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val) A6XX_VPC_GS_PACK_POSITIONLOC() argument 4793 A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) A6XX_VPC_GS_PACK_PSIZELOC() argument 4799 A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val) A6XX_VPC_GS_PACK_EXTRAPOS() argument 4807 A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val) A6XX_VPC_DS_PACK_STRIDE_IN_VPC() argument 4813 A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val) A6XX_VPC_DS_PACK_POSITIONLOC() argument 4819 A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) A6XX_VPC_DS_PACK_PSIZELOC() argument 4825 A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val) A6XX_VPC_DS_PACK_EXTRAPOS() argument 4833 A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) A6XX_VPC_CNTL_0_NUMNONPOSVAR() argument 4839 A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) A6XX_VPC_CNTL_0_PRIMIDLOC() argument 4846 A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val) A6XX_VPC_CNTL_0_VIEWIDLOC() argument 4854 A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val) A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM() argument 4860 A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val) A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM() argument 4866 A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val) A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM() argument 4872 A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val) A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM() argument 4878 A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE() argument 4903 A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) A6XX_PC_HS_INPUT_SIZE_SIZE() argument 4909 A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val) A6XX_PC_HS_INPUT_SIZE_UNK13() argument 4917 A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) A6XX_PC_TESS_CNTL_SPACING() argument 4923 A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) A6XX_PC_TESS_CNTL_OUTPUT() argument 4939 A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE() argument 4950 A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val) A6XX_PC_DRAW_CMD_STATE_ID() argument 4958 A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val) A6XX_PC_DISPATCH_CMD_STATE_ID() argument 4966 A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val) A6XX_PC_EVENT_CMD_STATE_ID() argument 4972 A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) A6XX_PC_EVENT_CMD_EVENT() argument 4982 A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) A6XX_PC_POLYGON_MODE_MODE() argument 4990 A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) A6XX_PC_RASTER_CNTL_STREAM() argument 5005 A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC() argument 5015 A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) A6XX_PC_VS_OUT_CNTL_CLIP_MASK() argument 5023 A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC() argument 5033 A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) A6XX_PC_GS_OUT_CNTL_CLIP_MASK() argument 5041 A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC() argument 5051 A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val) A6XX_PC_HS_OUT_CNTL_CLIP_MASK() argument 5059 A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC() argument 5069 A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) A6XX_PC_DS_OUT_CNTL_CLIP_MASK() argument 5077 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT() argument 5083 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS() argument 5090 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT() argument 5096 A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val) A6XX_PC_PRIMITIVE_CNTL_5_UNK18() argument 5104 A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC() argument 5114 A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val) A6XX_PC_MULTIVIEW_CNTL_VIEWS() argument 5124 A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) A6XX_PC_2D_EVENT_CMD_EVENT() argument 5130 A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) A6XX_PC_2D_EVENT_CMD_STATE_ID() argument 5148 A6XX_PC_TESSFACTOR_ADDR(uint32_t val) A6XX_PC_TESSFACTOR_ADDR() argument 5156 A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) A6XX_PC_DRAW_INITIATOR_PRIM_TYPE() argument 5162 A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT() argument 5168 A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) A6XX_PC_DRAW_INITIATOR_VIS_CULL() argument 5174 A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) A6XX_PC_DRAW_INITIATOR_INDEX_SIZE() argument 5180 A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) A6XX_PC_DRAW_INITIATOR_PATCH_TYPE() argument 5194 A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val) A6XX_PC_VSTREAM_CONTROL_UNK0() argument 5200 A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val) A6XX_PC_VSTREAM_CONTROL_VSC_SIZE() argument 5206 A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) A6XX_PC_VSTREAM_CONTROL_VSC_N() argument 5214 A6XX_PC_BIN_PRIM_STRM(uint32_t val) A6XX_PC_BIN_PRIM_STRM() argument 5222 A6XX_PC_BIN_DRAW_STRM(uint32_t val) A6XX_PC_BIN_DRAW_STRM() argument 5239 A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val) A6XX_VFD_CONTROL_0_FETCH_CNT() argument 5245 A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val) A6XX_VFD_CONTROL_0_DECODE_CNT() argument 5253 A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) A6XX_VFD_CONTROL_1_REGID4VTX() argument 5259 A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) A6XX_VFD_CONTROL_1_REGID4INST() argument 5265 A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) A6XX_VFD_CONTROL_1_REGID4PRIMID() argument 5271 A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val) A6XX_VFD_CONTROL_1_REGID4VIEWID() argument 5279 A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val) A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID() argument 5285 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) A6XX_VFD_CONTROL_2_REGID_INVOCATIONID() argument 5293 A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val) A6XX_VFD_CONTROL_3_REGID_DSPRIMID() argument 5299 A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val) A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID() argument 5305 A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) A6XX_VFD_CONTROL_3_REGID_TESSX() argument 5311 A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) A6XX_VFD_CONTROL_3_REGID_TESSY() argument 5319 A6XX_VFD_CONTROL_4_UNK0(uint32_t val) A6XX_VFD_CONTROL_4_UNK0() argument 5327 A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) A6XX_VFD_CONTROL_5_REGID_GSHEADER() argument 5333 A6XX_VFD_CONTROL_5_UNK8(uint32_t val) A6XX_VFD_CONTROL_5_UNK8() argument 5344 A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val) A6XX_VFD_MODE_CNTL_RENDER_MODE() argument 5354 A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) A6XX_VFD_MULTIVIEW_CNTL_VIEWS() argument 5372 A6XX_VFD_FETCH_BASE(uint32_t val) A6XX_VFD_FETCH_BASE() argument 5386 A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) A6XX_VFD_DECODE_INSTR_IDX() argument 5392 A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val) A6XX_VFD_DECODE_INSTR_OFFSET() argument 5399 A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) A6XX_VFD_DECODE_INSTR_FORMAT() argument 5405 A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) A6XX_VFD_DECODE_INSTR_SWAP() argument 5419 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK() argument 5425 A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) A6XX_VFD_DEST_CNTL_INSTR_REGID() argument 5443 A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A6XX_SP_VS_CTRL_REG0_THREADMODE() argument 5449 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT() argument 5455 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT() argument 5462 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) A6XX_SP_VS_CTRL_REG0_BRANCHSTACK() argument 5472 A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) A6XX_SP_VS_PRIMITIVE_CNTL_OUT() argument 5478 A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID() argument 5488 A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) A6XX_SP_VS_OUT_REG_A_REGID() argument 5494 A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) A6XX_SP_VS_OUT_REG_A_COMPMASK() argument 5500 A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) A6XX_SP_VS_OUT_REG_B_REGID() argument 5506 A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) A6XX_SP_VS_OUT_REG_B_COMPMASK() argument 5516 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) A6XX_SP_VS_VPC_DST_REG_OUTLOC0() argument 5522 A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) A6XX_SP_VS_VPC_DST_REG_OUTLOC1() argument 5528 A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) A6XX_SP_VS_VPC_DST_REG_OUTLOC2() argument 5534 A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) A6XX_SP_VS_VPC_DST_REG_OUTLOC3() argument 5544 A6XX_SP_VS_OBJ_START(uint32_t val) A6XX_SP_VS_OBJ_START() argument 5552 A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM() argument 5558 A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD() argument 5566 A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val) A6XX_SP_VS_PVT_MEM_ADDR() argument 5574 A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE() argument 5590 A6XX_SP_VS_CONFIG_NTEX(uint32_t val) A6XX_SP_VS_CONFIG_NTEX() argument 5596 A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) A6XX_SP_VS_CONFIG_NSAMP() argument 5602 A6XX_SP_VS_CONFIG_NIBO(uint32_t val) A6XX_SP_VS_CONFIG_NIBO() argument 5612 A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET() argument 5621 A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A6XX_SP_HS_CTRL_REG0_THREADMODE() argument 5627 A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT() argument 5633 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT() argument 5640 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) A6XX_SP_HS_CTRL_REG0_BRANCHSTACK() argument 5654 A6XX_SP_HS_OBJ_START(uint32_t val) A6XX_SP_HS_OBJ_START() argument 5662 A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM() argument 5668 A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD() argument 5676 A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val) A6XX_SP_HS_PVT_MEM_ADDR() argument 5684 A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE() argument 5700 A6XX_SP_HS_CONFIG_NTEX(uint32_t val) A6XX_SP_HS_CONFIG_NTEX() argument 5706 A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) A6XX_SP_HS_CONFIG_NSAMP() argument 5712 A6XX_SP_HS_CONFIG_NIBO(uint32_t val) A6XX_SP_HS_CONFIG_NIBO() argument 5722 A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET() argument 5731 A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A6XX_SP_DS_CTRL_REG0_THREADMODE() argument 5737 A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT() argument 5743 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT() argument 5750 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) A6XX_SP_DS_CTRL_REG0_BRANCHSTACK() argument 5760 A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) A6XX_SP_DS_PRIMITIVE_CNTL_OUT() argument 5766 A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID() argument 5776 A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) A6XX_SP_DS_OUT_REG_A_REGID() argument 5782 A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) A6XX_SP_DS_OUT_REG_A_COMPMASK() argument 5788 A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) A6XX_SP_DS_OUT_REG_B_REGID() argument 5794 A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) A6XX_SP_DS_OUT_REG_B_COMPMASK() argument 5804 A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) A6XX_SP_DS_VPC_DST_REG_OUTLOC0() argument 5810 A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) A6XX_SP_DS_VPC_DST_REG_OUTLOC1() argument 5816 A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) A6XX_SP_DS_VPC_DST_REG_OUTLOC2() argument 5822 A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) A6XX_SP_DS_VPC_DST_REG_OUTLOC3() argument 5832 A6XX_SP_DS_OBJ_START(uint32_t val) A6XX_SP_DS_OBJ_START() argument 5840 A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM() argument 5846 A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD() argument 5854 A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val) A6XX_SP_DS_PVT_MEM_ADDR() argument 5862 A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE() argument 5878 A6XX_SP_DS_CONFIG_NTEX(uint32_t val) A6XX_SP_DS_CONFIG_NTEX() argument 5884 A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) A6XX_SP_DS_CONFIG_NSAMP() argument 5890 A6XX_SP_DS_CONFIG_NIBO(uint32_t val) A6XX_SP_DS_CONFIG_NIBO() argument 5900 A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET() argument 5909 A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A6XX_SP_GS_CTRL_REG0_THREADMODE() argument 5915 A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT() argument 5921 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT() argument 5928 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) A6XX_SP_GS_CTRL_REG0_BRANCHSTACK() argument 5940 A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val) A6XX_SP_GS_PRIMITIVE_CNTL_OUT() argument 5946 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID() argument 5956 A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val) A6XX_SP_GS_OUT_REG_A_REGID() argument 5962 A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) A6XX_SP_GS_OUT_REG_A_COMPMASK() argument 5968 A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val) A6XX_SP_GS_OUT_REG_B_REGID() argument 5974 A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) A6XX_SP_GS_OUT_REG_B_COMPMASK() argument 5984 A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) A6XX_SP_GS_VPC_DST_REG_OUTLOC0() argument 5990 A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) A6XX_SP_GS_VPC_DST_REG_OUTLOC1() argument 5996 A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) A6XX_SP_GS_VPC_DST_REG_OUTLOC2() argument 6002 A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) A6XX_SP_GS_VPC_DST_REG_OUTLOC3() argument 6012 A6XX_SP_GS_OBJ_START(uint32_t val) A6XX_SP_GS_OBJ_START() argument 6020 A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM() argument 6026 A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD() argument 6034 A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val) A6XX_SP_GS_PVT_MEM_ADDR() argument 6042 A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE() argument 6058 A6XX_SP_GS_CONFIG_NTEX(uint32_t val) A6XX_SP_GS_CONFIG_NTEX() argument 6064 A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) A6XX_SP_GS_CONFIG_NSAMP() argument 6070 A6XX_SP_GS_CONFIG_NIBO(uint32_t val) A6XX_SP_GS_CONFIG_NIBO() argument 6080 A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET() argument 6088 A6XX_SP_VS_TEX_SAMP(uint32_t val) A6XX_SP_VS_TEX_SAMP() argument 6096 A6XX_SP_HS_TEX_SAMP(uint32_t val) A6XX_SP_HS_TEX_SAMP() argument 6104 A6XX_SP_DS_TEX_SAMP(uint32_t val) A6XX_SP_DS_TEX_SAMP() argument 6112 A6XX_SP_GS_TEX_SAMP(uint32_t val) A6XX_SP_GS_TEX_SAMP() argument 6120 A6XX_SP_VS_TEX_CONST(uint32_t val) A6XX_SP_VS_TEX_CONST() argument 6128 A6XX_SP_HS_TEX_CONST(uint32_t val) A6XX_SP_HS_TEX_CONST() argument 6136 A6XX_SP_DS_TEX_CONST(uint32_t val) A6XX_SP_DS_TEX_CONST() argument 6144 A6XX_SP_GS_TEX_CONST(uint32_t val) A6XX_SP_GS_TEX_CONST() argument 6152 A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) A6XX_SP_FS_CTRL_REG0_THREADSIZE() argument 6167 A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A6XX_SP_FS_CTRL_REG0_THREADMODE() argument 6173 A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT() argument 6179 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT() argument 6186 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) A6XX_SP_FS_CTRL_REG0_BRANCHSTACK() argument 6198 A6XX_SP_FS_OBJ_START(uint32_t val) A6XX_SP_FS_OBJ_START() argument 6206 A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM() argument 6212 A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD() argument 6220 A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val) A6XX_SP_FS_PVT_MEM_ADDR() argument 6228 A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE() argument 6237 A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) A6XX_SP_BLEND_CNTL_ENABLE_BLEND() argument 6258 A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) A6XX_SP_FS_RENDER_COMPONENTS_RT0() argument 6264 A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) A6XX_SP_FS_RENDER_COMPONENTS_RT1() argument 6270 A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) A6XX_SP_FS_RENDER_COMPONENTS_RT2() argument 6276 A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) A6XX_SP_FS_RENDER_COMPONENTS_RT3() argument 6282 A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) A6XX_SP_FS_RENDER_COMPONENTS_RT4() argument 6288 A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) A6XX_SP_FS_RENDER_COMPONENTS_RT5() argument 6294 A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) A6XX_SP_FS_RENDER_COMPONENTS_RT6() argument 6300 A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) A6XX_SP_FS_RENDER_COMPONENTS_RT7() argument 6309 A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID() argument 6315 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID() argument 6321 A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val) A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID() argument 6329 A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) A6XX_SP_FS_OUTPUT_CNTL1_MRT() argument 6339 A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) A6XX_SP_FS_OUTPUT_REG_REGID() argument 6350 A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) A6XX_SP_FS_MRT_REG_COLOR_FORMAT() argument 6361 A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) A6XX_SP_FS_PREFETCH_CNTL_COUNT() argument 6370 A6XX_SP_FS_PREFETCH_CNTL_UNK6(uint32_t val) A6XX_SP_FS_PREFETCH_CNTL_UNK6() argument 6380 A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) A6XX_SP_FS_PREFETCH_CMD_SRC() argument 6386 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) A6XX_SP_FS_PREFETCH_CMD_SAMP_ID() argument 6392 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) A6XX_SP_FS_PREFETCH_CMD_TEX_ID() argument 6398 A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) A6XX_SP_FS_PREFETCH_CMD_DST() argument 6404 A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) A6XX_SP_FS_PREFETCH_CMD_WRMASK() argument 6413 A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) A6XX_SP_FS_PREFETCH_CMD_CMD() argument 6423 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID() argument 6429 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID() argument 6441 A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET() argument 6449 A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) A6XX_SP_CS_CTRL_REG0_THREADSIZE() argument 6459 A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A6XX_SP_CS_CTRL_REG0_THREADMODE() argument 6465 A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT() argument 6471 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT() argument 6478 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) A6XX_SP_CS_CTRL_REG0_BRANCHSTACK() argument 6486 A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE() argument 6500 A6XX_SP_CS_OBJ_START(uint32_t val) A6XX_SP_CS_OBJ_START() argument 6508 A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM() argument 6514 A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD() argument 6522 A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val) A6XX_SP_CS_PVT_MEM_ADDR() argument 6530 A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE() argument 6546 A6XX_SP_CS_CONFIG_NTEX(uint32_t val) A6XX_SP_CS_CONFIG_NTEX() argument 6552 A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) A6XX_SP_CS_CONFIG_NSAMP() argument 6558 A6XX_SP_CS_CONFIG_NIBO(uint32_t val) A6XX_SP_CS_CONFIG_NIBO() argument 6568 A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET() argument 6576 A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val) A6XX_SP_CS_CNTL_0_WGIDCONSTID() argument 6582 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val) A6XX_SP_CS_CNTL_0_WGSIZECONSTID() argument 6588 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID() argument 6594 A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val) A6XX_SP_CS_CNTL_0_LOCALIDREGID() argument 6602 A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID() argument 6609 A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) A6XX_SP_CS_CNTL_1_THREADSIZE() argument 6618 A6XX_SP_FS_TEX_SAMP(uint32_t val) A6XX_SP_FS_TEX_SAMP() argument 6626 A6XX_SP_CS_TEX_SAMP(uint32_t val) A6XX_SP_CS_TEX_SAMP() argument 6634 A6XX_SP_FS_TEX_CONST(uint32_t val) A6XX_SP_FS_TEX_CONST() argument 6642 A6XX_SP_CS_TEX_CONST(uint32_t val) A6XX_SP_CS_TEX_CONST() argument 6652 A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE() argument 6658 A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR() argument 6666 A6XX_SP_CS_IBO(uint32_t val) A6XX_SP_CS_IBO() argument 6677 A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) A6XX_SP_MODE_CONTROL_ISAMMODE() argument 6691 A6XX_SP_FS_CONFIG_NTEX(uint32_t val) A6XX_SP_FS_CONFIG_NTEX() argument 6697 A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) A6XX_SP_FS_CONFIG_NSAMP() argument 6703 A6XX_SP_FS_CONFIG_NIBO(uint32_t val) A6XX_SP_FS_CONFIG_NIBO() argument 6715 A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE() argument 6721 A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR() argument 6729 A6XX_SP_IBO(uint32_t val) A6XX_SP_IBO() argument 6742 A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT() argument 6749 A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) A6XX_SP_2D_DST_FORMAT_MASK() argument 6786 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR() argument 6802 A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES() argument 6808 A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val) A6XX_SP_TP_RAS_MSAA_CNTL_UNK2() argument 6816 A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES() argument 6825 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) A6XX_SP_TP_BORDER_COLOR_BASE_ADDR() argument 6837 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X() argument 6843 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y() argument 6849 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X() argument 6855 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y() argument 6861 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X() argument 6867 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y() argument 6873 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X() argument 6879 A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y() argument 6887 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X() argument 6893 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y() argument 6899 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X() argument 6905 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y() argument 6911 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X() argument 6917 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y() argument 6923 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X() argument 6929 A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y() argument 6937 A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) A6XX_SP_TP_WINDOW_OFFSET_X() argument 6943 A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) A6XX_SP_TP_WINDOW_OFFSET_Y() argument 6951 A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val) A6XX_SP_TP_MODE_CNTL_ISAMMODE() argument 6957 A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val) A6XX_SP_TP_MODE_CNTL_UNK3() argument 6965 A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT() argument 6971 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) A6XX_SP_PS_2D_SRC_INFO_TILE_MODE() argument 6977 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP() argument 6985 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) A6XX_SP_PS_2D_SRC_INFO_SAMPLES() argument 6998 A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) A6XX_SP_PS_2D_SRC_INFO_UNK23() argument 7007 A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) A6XX_SP_PS_2D_SRC_SIZE_WIDTH() argument 7013 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) A6XX_SP_PS_2D_SRC_SIZE_HEIGHT() argument 7021 A6XX_SP_PS_2D_SRC(uint32_t val) A6XX_SP_PS_2D_SRC() argument 7029 A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) A6XX_SP_PS_2D_SRC_PITCH_UNK0() argument 7035 A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) A6XX_SP_PS_2D_SRC_PITCH_PITCH() argument 7043 A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val) A6XX_SP_PS_2D_SRC_PLANE1() argument 7051 A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) A6XX_SP_PS_2D_SRC_PLANE_PITCH() argument 7059 A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val) A6XX_SP_PS_2D_SRC_PLANE2() argument 7067 A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val) A6XX_SP_PS_2D_SRC_FLAGS() argument 7075 A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) A6XX_SP_PS_2D_SRC_FLAGS_PITCH() argument 7091 A6XX_SP_WINDOW_OFFSET_X(uint32_t val) A6XX_SP_WINDOW_OFFSET_X() argument 7097 A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) A6XX_SP_WINDOW_OFFSET_Y() argument 7112 A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val) A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT() argument 7119 A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val) A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT() argument 7125 A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) A6XX_TPL1_NC_MODE_CNTL_UNK6() argument 7147 A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) A6XX_HLSQ_VS_CNTL_CONSTLEN() argument 7156 A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) A6XX_HLSQ_HS_CNTL_CONSTLEN() argument 7165 A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) A6XX_HLSQ_DS_CNTL_CONSTLEN() argument 7174 A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) A6XX_HLSQ_GS_CNTL_CONSTLEN() argument 7185 A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val) A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR() argument 7195 A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) A6XX_HLSQ_FS_CNTL_0_THREADSIZE() argument 7202 A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) A6XX_HLSQ_FS_CNTL_0_UNK2() argument 7216 A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) A6XX_HLSQ_CONTROL_2_REG_FACEREGID() argument 7222 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) A6XX_HLSQ_CONTROL_2_REG_SAMPLEID() argument 7228 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK() argument 7234 A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) A6XX_HLSQ_CONTROL_2_REG_CENTERRHW() argument 7242 A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) A7XX_HLSQ_CONTROL_2_REG_FACEREGID() argument 7248 A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) A7XX_HLSQ_CONTROL_2_REG_SAMPLEID() argument 7254 A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK() argument 7260 A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) A7XX_HLSQ_CONTROL_2_REG_CENTERRHW() argument 7268 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL() argument 7274 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL() argument 7280 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID() argument 7286 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID() argument 7294 A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL() argument 7300 A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL() argument 7306 A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID() argument 7312 A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID() argument 7320 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE() argument 7326 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE() argument 7332 A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID() argument 7338 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID() argument 7346 A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE() argument 7352 A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE() argument 7358 A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID() argument 7364 A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID() argument 7372 A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID() argument 7378 A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID() argument 7386 A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID() argument 7392 A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID() argument 7400 A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) A6XX_HLSQ_CS_CNTL_CONSTLEN() argument 7409 A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM() argument 7415 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX() argument 7421 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY() argument 7427 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ() argument 7435 A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X() argument 7443 A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X() argument 7451 A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y() argument 7459 A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y() argument 7467 A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z() argument 7475 A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z() argument 7483 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID() argument 7489 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val) A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID() argument 7495 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID() argument 7501 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID() argument 7509 A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID() argument 7516 A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) A6XX_HLSQ_CS_CNTL_1_THREADSIZE() argument 7533 A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val) A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR() argument 7545 A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE() argument 7551 A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR() argument 7559 A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val) A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE() argument 7569 A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val) A6XX_HLSQ_DRAW_CMD_STATE_ID() argument 7577 A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val) A6XX_HLSQ_DISPATCH_CMD_STATE_ID() argument 7585 A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val) A6XX_HLSQ_EVENT_CMD_STATE_ID() argument 7591 A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) A6XX_HLSQ_EVENT_CMD_EVENT() argument 7609 A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS() argument 7615 A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS() argument 7623 A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) A6XX_HLSQ_FS_CNTL_CONSTLEN() argument 7637 A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE() argument 7643 A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR() argument 7651 A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val) A6XX_HLSQ_2D_EVENT_CMD_STATE_ID() argument 7657 A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) A6XX_HLSQ_2D_EVENT_CMD_EVENT() argument 7681 A6XX_CP_EVENT_START_STATE_ID(uint32_t val) A6XX_CP_EVENT_START_STATE_ID() argument 7689 A6XX_CP_EVENT_END_STATE_ID(uint32_t val) A6XX_CP_EVENT_END_STATE_ID() argument 7697 A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val) A6XX_CP_2D_EVENT_START_STATE_ID() argument 7705 A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val) A6XX_CP_2D_EVENT_END_STATE_ID() argument 7714 A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) A6XX_TEX_SAMP_0_XY_MAG() argument 7720 A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) A6XX_TEX_SAMP_0_XY_MIN() argument 7726 A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) A6XX_TEX_SAMP_0_WRAP_S() argument 7732 A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) A6XX_TEX_SAMP_0_WRAP_T() argument 7738 A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) A6XX_TEX_SAMP_0_WRAP_R() argument 7744 A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) A6XX_TEX_SAMP_0_ANISO() argument 7750 A6XX_TEX_SAMP_0_LOD_BIAS(float val) A6XX_TEX_SAMP_0_LOD_BIAS() argument 7759 A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) A6XX_TEX_SAMP_1_COMPARE_FUNC() argument 7768 A6XX_TEX_SAMP_1_MAX_LOD(float val) A6XX_TEX_SAMP_1_MAX_LOD() argument 7774 A6XX_TEX_SAMP_1_MIN_LOD(float val) A6XX_TEX_SAMP_1_MIN_LOD() argument 7782 A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) A6XX_TEX_SAMP_2_REDUCTION_MODE() argument 7789 A6XX_TEX_SAMP_2_BCOLOR(uint32_t val) A6XX_TEX_SAMP_2_BCOLOR() argument 7799 A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) A6XX_TEX_CONST_0_TILE_MODE() argument 7806 A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) A6XX_TEX_CONST_0_SWIZ_X() argument 7812 A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) A6XX_TEX_CONST_0_SWIZ_Y() argument 7818 A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) A6XX_TEX_CONST_0_SWIZ_Z() argument 7824 A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) A6XX_TEX_CONST_0_SWIZ_W() argument 7830 A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) A6XX_TEX_CONST_0_MIPLVLS() argument 7838 A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) A6XX_TEX_CONST_0_SAMPLES() argument 7844 A6XX_TEX_CONST_0_FMT(enum a6xx_format val) A6XX_TEX_CONST_0_FMT() argument 7850 A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) A6XX_TEX_CONST_0_SWAP() argument 7858 A6XX_TEX_CONST_1_WIDTH(uint32_t val) A6XX_TEX_CONST_1_WIDTH() argument 7864 A6XX_TEX_CONST_1_HEIGHT(uint32_t val) A6XX_TEX_CONST_1_HEIGHT() argument 7872 A6XX_TEX_CONST_2_STRUCTSIZETEXELS(uint32_t val) A6XX_TEX_CONST_2_STRUCTSIZETEXELS() argument 7878 A6XX_TEX_CONST_2_STARTOFFSETTEXELS(uint32_t val) A6XX_TEX_CONST_2_STARTOFFSETTEXELS() argument 7884 A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val) A6XX_TEX_CONST_2_PITCHALIGN() argument 7890 A6XX_TEX_CONST_2_PITCH(uint32_t val) A6XX_TEX_CONST_2_PITCH() argument 7896 A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) A6XX_TEX_CONST_2_TYPE() argument 7904 A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) A6XX_TEX_CONST_3_ARRAY_PITCH() argument 7910 A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) A6XX_TEX_CONST_3_MIN_LAYERSZ() argument 7920 A6XX_TEX_CONST_4_BASE_LO(uint32_t val) A6XX_TEX_CONST_4_BASE_LO() argument 7928 A6XX_TEX_CONST_5_BASE_HI(uint32_t val) A6XX_TEX_CONST_5_BASE_HI() argument 7934 A6XX_TEX_CONST_5_DEPTH(uint32_t val) A6XX_TEX_CONST_5_DEPTH() argument 7942 A6XX_TEX_CONST_6_MIN_LOD_CLAMP(float val) A6XX_TEX_CONST_6_MIN_LOD_CLAMP() argument 7948 A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) A6XX_TEX_CONST_6_PLANE_PITCH() argument 7956 A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) A6XX_TEX_CONST_7_FLAG_LO() argument 7964 A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) A6XX_TEX_CONST_8_FLAG_HI() argument 7972 A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH() argument 7980 A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH() argument 7986 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val) A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW() argument 7992 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val) A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH() argument 8010 A6XX_UBO_0_BASE_LO(uint32_t val) A6XX_UBO_0_BASE_LO() argument 8018 A6XX_UBO_1_BASE_HI(uint32_t val) A6XX_UBO_1_BASE_HI() argument 8024 A6XX_UBO_1_SIZE(uint32_t val) A6XX_UBO_1_SIZE() argument 8086 A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX() argument 8092 A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL() argument 8106 A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN() argument 8112 A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU() argument 8118 A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT() argument 8126 A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE() argument 8150 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0() argument 8156 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1() argument 8162 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2() argument 8168 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3() argument 8174 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4() argument 8180 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5() argument 8186 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6() argument 8192 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7() argument 8200 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8() argument 8206 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9() argument 8212 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10() argument 8218 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11() argument 8224 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12() argument 8230 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13() argument 8236 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14() argument 8242 A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15() argument [all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/
H A D	adreno_pm4.xml.h	475 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument 477 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF() 481 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument 483 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC() 487 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument 489 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK() 493 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument 495 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT() 501 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument 503 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIF in CP_LOAD_STATE_1_STATE_TYPE() 507 CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) CP_LOAD_STATE_1_EXT_SRC_ADDR() argument 515 CP_LOAD_STATE4_0_DST_OFF(uint32_t val) CP_LOAD_STATE4_0_DST_OFF() argument 521 CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) CP_LOAD_STATE4_0_STATE_SRC() argument 527 CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) CP_LOAD_STATE4_0_STATE_BLOCK() argument 533 CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) CP_LOAD_STATE4_0_NUM_UNIT() argument 541 CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) CP_LOAD_STATE4_1_STATE_TYPE() argument 547 CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) CP_LOAD_STATE4_1_EXT_SRC_ADDR() argument 555 CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val) CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI() argument 563 CP_LOAD_STATE6_0_DST_OFF(uint32_t val) CP_LOAD_STATE6_0_DST_OFF() argument 569 CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val) CP_LOAD_STATE6_0_STATE_TYPE() argument 575 CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val) CP_LOAD_STATE6_0_STATE_SRC() argument 581 CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val) CP_LOAD_STATE6_0_STATE_BLOCK() argument 587 CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) CP_LOAD_STATE6_0_NUM_UNIT() argument 595 CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) CP_LOAD_STATE6_1_EXT_SRC_ADDR() argument 603 CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val) CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI() argument 613 CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) CP_DRAW_INDX_0_VIZ_QUERY() argument 621 CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) CP_DRAW_INDX_1_PRIM_TYPE() argument 627 CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) CP_DRAW_INDX_1_SOURCE_SELECT() argument 633 CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) CP_DRAW_INDX_1_VIS_CULL() argument 639 CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) CP_DRAW_INDX_1_INDEX_SIZE() argument 648 CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) CP_DRAW_INDX_1_NUM_INSTANCES() argument 656 CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) CP_DRAW_INDX_2_NUM_INDICES() argument 664 CP_DRAW_INDX_3_INDX_BASE(uint32_t val) CP_DRAW_INDX_3_INDX_BASE() argument 672 CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) CP_DRAW_INDX_4_INDX_SIZE() argument 680 CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) CP_DRAW_INDX_2_0_VIZ_QUERY() argument 688 CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) CP_DRAW_INDX_2_1_PRIM_TYPE() argument 694 CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) CP_DRAW_INDX_2_1_SOURCE_SELECT() argument 700 CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) CP_DRAW_INDX_2_1_VIS_CULL() argument 706 CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) CP_DRAW_INDX_2_1_INDEX_SIZE() argument 715 CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) CP_DRAW_INDX_2_1_NUM_INSTANCES() argument 723 CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) CP_DRAW_INDX_2_2_NUM_INDICES() argument 731 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) CP_DRAW_INDX_OFFSET_0_PRIM_TYPE() argument 737 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT() argument 743 CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) CP_DRAW_INDX_OFFSET_0_VIS_CULL() argument 749 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) CP_DRAW_INDX_OFFSET_0_INDEX_SIZE() argument 755 CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val) CP_DRAW_INDX_OFFSET_0_PATCH_TYPE() argument 765 CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES() argument 773 CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) CP_DRAW_INDX_OFFSET_2_NUM_INDICES() argument 781 CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val) CP_DRAW_INDX_OFFSET_3_FIRST_INDX() argument 790 CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val) CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO() argument 798 CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val) CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI() argument 808 CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val) CP_DRAW_INDX_OFFSET_6_MAX_INDICES() argument 816 CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) CP_DRAW_INDX_OFFSET_4_INDX_BASE() argument 824 CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) CP_DRAW_INDX_OFFSET_5_INDX_SIZE() argument 832 A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE() argument 838 A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT() argument 844 A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) A4XX_CP_DRAW_INDIRECT_0_VIS_CULL() argument 850 A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE() argument 856 A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE() argument 867 A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) A4XX_CP_DRAW_INDIRECT_1_INDIRECT() argument 876 A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val) A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO() argument 884 A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI() argument 894 A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE() argument 900 A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT() argument 906 A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL() argument 912 A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE() argument 918 A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE() argument 929 A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val) A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE() argument 937 A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val) A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE() argument 945 A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT() argument 954 A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO() argument 962 A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI() argument 972 A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES() argument 980 A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO() argument 988 A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI() argument 998 A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val) A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE() argument 1004 A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val) A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT() argument 1010 A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val) A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL() argument 1016 A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val) A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE() argument 1022 A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val) A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE() argument 1032 A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val) A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE() argument 1038 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val) A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF() argument 1046 A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val) A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT() argument 1056 A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val) A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0() argument 1066 A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val) A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE() argument 1076 CP_SET_DRAW_STATE__0_COUNT(uint32_t val) CP_SET_DRAW_STATE__0_COUNT() argument 1089 CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) CP_SET_DRAW_STATE__0_GROUP_ID() argument 1097 CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) CP_SET_DRAW_STATE__1_ADDR_LO() argument 1105 CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) CP_SET_DRAW_STATE__2_ADDR_HI() argument 1115 CP_SET_BIN_1_X1(uint32_t val) CP_SET_BIN_1_X1() argument 1121 CP_SET_BIN_1_Y1(uint32_t val) CP_SET_BIN_1_Y1() argument 1129 CP_SET_BIN_2_X2(uint32_t val) CP_SET_BIN_2_X2() argument 1135 CP_SET_BIN_2_Y2(uint32_t val) CP_SET_BIN_2_Y2() argument 1143 CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) CP_SET_BIN_DATA_0_BIN_DATA_ADDR() argument 1151 CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS() argument 1159 CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val) CP_SET_BIN_DATA5_0_VSC_SIZE() argument 1165 CP_SET_BIN_DATA5_0_VSC_N(uint32_t val) CP_SET_BIN_DATA5_0_VSC_N() argument 1173 CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val) CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO() argument 1181 CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val) CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI() argument 1189 CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val) CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO() argument 1197 CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val) CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI() argument 1205 CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val) CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO() argument 1213 CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val) CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI() argument 1221 CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val) CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE() argument 1227 CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val) CP_SET_BIN_DATA5_OFFSET_0_VSC_N() argument 1235 CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val) CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET() argument 1243 CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val) CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET() argument 1251 CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val) CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET() argument 1259 CP_REG_RMW_0_DST_REG(uint32_t val) CP_REG_RMW_0_DST_REG() argument 1265 CP_REG_RMW_0_ROTATE(uint32_t val) CP_REG_RMW_0_ROTATE() argument 1276 CP_REG_RMW_1_SRC0(uint32_t val) CP_REG_RMW_1_SRC0() argument 1284 CP_REG_RMW_2_SRC1(uint32_t val) CP_REG_RMW_2_SRC1() argument 1292 CP_REG_TO_MEM_0_REG(uint32_t val) CP_REG_TO_MEM_0_REG() argument 1298 CP_REG_TO_MEM_0_CNT(uint32_t val) CP_REG_TO_MEM_0_CNT() argument 1308 CP_REG_TO_MEM_1_DEST(uint32_t val) CP_REG_TO_MEM_1_DEST() argument 1316 CP_REG_TO_MEM_2_DEST_HI(uint32_t val) CP_REG_TO_MEM_2_DEST_HI() argument 1324 CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val) CP_REG_TO_MEM_OFFSET_REG_0_REG() argument 1330 CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val) CP_REG_TO_MEM_OFFSET_REG_0_CNT() argument 1340 CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val) CP_REG_TO_MEM_OFFSET_REG_1_DEST() argument 1348 CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val) CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI() argument 1356 CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val) CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0() argument 1365 CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_0_REG() argument 1371 CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_0_CNT() argument 1381 CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_1_DEST() argument 1389 CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI() argument 1397 CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO() argument 1405 CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val) CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI() argument 1413 CP_MEM_TO_REG_0_REG(uint32_t val) CP_MEM_TO_REG_0_REG() argument 1419 CP_MEM_TO_REG_0_CNT(uint32_t val) CP_MEM_TO_REG_0_CNT() argument 1429 CP_MEM_TO_REG_1_SRC(uint32_t val) CP_MEM_TO_REG_1_SRC() argument 1437 CP_MEM_TO_REG_2_SRC_HI(uint32_t val) CP_MEM_TO_REG_2_SRC_HI() argument 1453 CP_MEMCPY_0_DWORDS(uint32_t val) CP_MEMCPY_0_DWORDS() argument 1461 CP_MEMCPY_1_SRC_LO(uint32_t val) CP_MEMCPY_1_SRC_LO() argument 1469 CP_MEMCPY_2_SRC_HI(uint32_t val) CP_MEMCPY_2_SRC_HI() argument 1477 CP_MEMCPY_3_DST_LO(uint32_t val) CP_MEMCPY_3_DST_LO() argument 1485 CP_MEMCPY_4_DST_HI(uint32_t val) CP_MEMCPY_4_DST_HI() argument 1493 CP_REG_TO_SCRATCH_0_REG(uint32_t val) CP_REG_TO_SCRATCH_0_REG() argument 1499 CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val) CP_REG_TO_SCRATCH_0_SCRATCH() argument 1505 CP_REG_TO_SCRATCH_0_CNT(uint32_t val) CP_REG_TO_SCRATCH_0_CNT() argument 1513 CP_SCRATCH_TO_REG_0_REG(uint32_t val) CP_SCRATCH_TO_REG_0_REG() argument 1520 CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val) CP_SCRATCH_TO_REG_0_SCRATCH() argument 1526 CP_SCRATCH_TO_REG_0_CNT(uint32_t val) CP_SCRATCH_TO_REG_0_CNT() argument 1534 CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val) CP_SCRATCH_WRITE_0_SCRATCH() argument 1542 CP_MEM_WRITE_0_ADDR_LO(uint32_t val) CP_MEM_WRITE_0_ADDR_LO() argument 1550 CP_MEM_WRITE_1_ADDR_HI(uint32_t val) CP_MEM_WRITE_1_ADDR_HI() argument 1558 CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val) CP_COND_WRITE_0_FUNCTION() argument 1568 CP_COND_WRITE_1_POLL_ADDR(uint32_t val) CP_COND_WRITE_1_POLL_ADDR() argument 1576 CP_COND_WRITE_2_REF(uint32_t val) CP_COND_WRITE_2_REF() argument 1584 CP_COND_WRITE_3_MASK(uint32_t val) CP_COND_WRITE_3_MASK() argument 1592 CP_COND_WRITE_4_WRITE_ADDR(uint32_t val) CP_COND_WRITE_4_WRITE_ADDR() argument 1600 CP_COND_WRITE_5_WRITE_DATA(uint32_t val) CP_COND_WRITE_5_WRITE_DATA() argument 1608 CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) CP_COND_WRITE5_0_FUNCTION() argument 1620 CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val) CP_COND_WRITE5_1_POLL_ADDR_LO() argument 1628 CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val) CP_COND_WRITE5_2_POLL_ADDR_HI() argument 1636 CP_COND_WRITE5_3_REF(uint32_t val) CP_COND_WRITE5_3_REF() argument 1644 CP_COND_WRITE5_4_MASK(uint32_t val) CP_COND_WRITE5_4_MASK() argument 1652 CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val) CP_COND_WRITE5_5_WRITE_ADDR_LO() argument 1660 CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val) CP_COND_WRITE5_6_WRITE_ADDR_HI() argument 1668 CP_COND_WRITE5_7_WRITE_DATA(uint32_t val) CP_COND_WRITE5_7_WRITE_DATA() argument 1676 CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val) CP_WAIT_MEM_GTE_0_RESERVED() argument 1684 CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val) CP_WAIT_MEM_GTE_1_POLL_ADDR_LO() argument 1692 CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val) CP_WAIT_MEM_GTE_2_POLL_ADDR_HI() argument 1700 CP_WAIT_MEM_GTE_3_REF(uint32_t val) CP_WAIT_MEM_GTE_3_REF() argument 1708 CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val) CP_WAIT_REG_MEM_0_FUNCTION() argument 1720 CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val) CP_WAIT_REG_MEM_1_POLL_ADDR_LO() argument 1728 CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val) CP_WAIT_REG_MEM_2_POLL_ADDR_HI() argument 1736 CP_WAIT_REG_MEM_3_REF(uint32_t val) CP_WAIT_REG_MEM_3_REF() argument 1744 CP_WAIT_REG_MEM_4_MASK(uint32_t val) CP_WAIT_REG_MEM_4_MASK() argument 1752 CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val) CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES() argument 1760 CP_WAIT_TWO_REGS_0_REG0(uint32_t val) CP_WAIT_TWO_REGS_0_REG0() argument 1768 CP_WAIT_TWO_REGS_1_REG1(uint32_t val) CP_WAIT_TWO_REGS_1_REG1() argument 1776 CP_WAIT_TWO_REGS_2_REF(uint32_t val) CP_WAIT_TWO_REGS_2_REF() argument 1786 CP_DISPATCH_COMPUTE_1_X(uint32_t val) CP_DISPATCH_COMPUTE_1_X() argument 1794 CP_DISPATCH_COMPUTE_2_Y(uint32_t val) CP_DISPATCH_COMPUTE_2_Y() argument 1802 CP_DISPATCH_COMPUTE_3_Z(uint32_t val) CP_DISPATCH_COMPUTE_3_Z() argument 1810 CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) CP_SET_RENDER_MODE_0_MODE() argument 1818 CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) CP_SET_RENDER_MODE_1_ADDR_0_LO() argument 1826 CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) CP_SET_RENDER_MODE_2_ADDR_0_HI() argument 1840 CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) CP_SET_RENDER_MODE_5_ADDR_1_LEN() argument 1848 CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) CP_SET_RENDER_MODE_6_ADDR_1_LO() argument 1856 CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) CP_SET_RENDER_MODE_7_ADDR_1_HI() argument 1864 CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val) CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO() argument 1872 CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI() argument 1882 CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val) CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN() argument 1892 CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val) CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO() argument 1900 CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val) CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI() argument 1912 CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) CP_PERFCOUNTER_ACTION_1_ADDR_0_LO() argument 1920 CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) CP_PERFCOUNTER_ACTION_2_ADDR_0_HI() argument 1928 CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) CP_EVENT_WRITE_0_EVENT() argument 1938 CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) CP_EVENT_WRITE_1_ADDR_0_LO() argument 1946 CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) CP_EVENT_WRITE_2_ADDR_0_HI() argument 1956 CP_BLIT_0_OP(enum cp_blit_cmd val) CP_BLIT_0_OP() argument 1964 CP_BLIT_1_SRC_X1(uint32_t val) CP_BLIT_1_SRC_X1() argument 1970 CP_BLIT_1_SRC_Y1(uint32_t val) CP_BLIT_1_SRC_Y1() argument 1978 CP_BLIT_2_SRC_X2(uint32_t val) CP_BLIT_2_SRC_X2() argument 1984 CP_BLIT_2_SRC_Y2(uint32_t val) CP_BLIT_2_SRC_Y2() argument 1992 CP_BLIT_3_DST_X1(uint32_t val) CP_BLIT_3_DST_X1() argument 1998 CP_BLIT_3_DST_Y1(uint32_t val) CP_BLIT_3_DST_Y1() argument 2006 CP_BLIT_4_DST_X2(uint32_t val) CP_BLIT_4_DST_X2() argument 2012 CP_BLIT_4_DST_Y2(uint32_t val) CP_BLIT_4_DST_Y2() argument 2022 CP_EXEC_CS_1_NGROUPS_X(uint32_t val) CP_EXEC_CS_1_NGROUPS_X() argument 2030 CP_EXEC_CS_2_NGROUPS_Y(uint32_t val) CP_EXEC_CS_2_NGROUPS_Y() argument 2038 CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) CP_EXEC_CS_3_NGROUPS_Z() argument 2049 A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val) A4XX_CP_EXEC_CS_INDIRECT_1_ADDR() argument 2057 A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val) A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX() argument 2063 A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val) A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY() argument 2069 A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ() argument 2078 A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO() argument 2086 A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI() argument 2094 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX() argument 2100 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY() argument 2106 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ() argument 2114 A6XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val) A6XX_CP_SET_MARKER_0_MODE() argument 2120 A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_render_mode val) A6XX_CP_SET_MARKER_0_MARKER() argument 2130 A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG() argument 2138 A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val) A6XX_CP_SET_PSEUDO_REG__1_LO() argument 2146 A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val) A6XX_CP_SET_PSEUDO_REG__2_HI() argument 2154 A6XX_CP_REG_TEST_0_REG(uint32_t val) A6XX_CP_REG_TEST_0_REG() argument 2160 A6XX_CP_REG_TEST_0_BIT(uint32_t val) A6XX_CP_REG_TEST_0_BIT() argument 2169 CP_COND_REG_EXEC_0_REG0(uint32_t val) CP_COND_REG_EXEC_0_REG0() argument 2178 CP_COND_REG_EXEC_0_MODE(enum compare_mode val) CP_COND_REG_EXEC_0_MODE() argument 2186 CP_COND_REG_EXEC_1_DWORDS(uint32_t val) CP_COND_REG_EXEC_1_DWORDS() argument 2194 CP_COND_EXEC_0_ADDR0_LO(uint32_t val) CP_COND_EXEC_0_ADDR0_LO() argument 2202 CP_COND_EXEC_1_ADDR0_HI(uint32_t val) CP_COND_EXEC_1_ADDR0_HI() argument 2210 CP_COND_EXEC_2_ADDR1_LO(uint32_t val) CP_COND_EXEC_2_ADDR1_LO() argument 2218 CP_COND_EXEC_3_ADDR1_HI(uint32_t val) CP_COND_EXEC_3_ADDR1_HI() argument 2226 CP_COND_EXEC_4_REF(uint32_t val) CP_COND_EXEC_4_REF() argument 2234 CP_COND_EXEC_5_DWORDS(uint32_t val) CP_COND_EXEC_5_DWORDS() argument 2242 CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val) CP_SET_CTXSWITCH_IB_0_ADDR_LO() argument 2250 CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val) CP_SET_CTXSWITCH_IB_1_ADDR_HI() argument 2258 CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val) CP_SET_CTXSWITCH_IB_2_DWORDS() argument 2264 CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val) CP_SET_CTXSWITCH_IB_2_TYPE() argument 2272 CP_REG_WRITE_0_TRACKER(enum reg_tracker val) CP_REG_WRITE_0_TRACKER() argument 2280 CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val) CP_SMMU_TABLE_UPDATE_0_TTBR0_LO() argument 2288 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val) CP_SMMU_TABLE_UPDATE_1_TTBR0_HI() argument 2294 CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val) CP_SMMU_TABLE_UPDATE_1_ASID() argument 2302 CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val) CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR() argument 2310 CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val) CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK() argument [all...]
H A D	a3xx.xml.h	947 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() argument 949 return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK; in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() 955 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument 957 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() 961 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument 963 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() 969 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET() argument 971 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; in A3XX_GRAS_CL_VPORT_XOFFSET() 977 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE() argument 979 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIF in A3XX_GRAS_CL_VPORT_XSCALE() 985 A3XX_GRAS_CL_VPORT_YOFFSET(float val) A3XX_GRAS_CL_VPORT_YOFFSET() argument 993 A3XX_GRAS_CL_VPORT_YSCALE(float val) A3XX_GRAS_CL_VPORT_YSCALE() argument 1001 A3XX_GRAS_CL_VPORT_ZOFFSET(float val) A3XX_GRAS_CL_VPORT_ZOFFSET() argument 1009 A3XX_GRAS_CL_VPORT_ZSCALE(float val) A3XX_GRAS_CL_VPORT_ZSCALE() argument 1017 A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) A3XX_GRAS_SU_POINT_MINMAX_MIN() argument 1023 A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) A3XX_GRAS_SU_POINT_MINMAX_MAX() argument 1031 A3XX_GRAS_SU_POINT_SIZE(float val) A3XX_GRAS_SU_POINT_SIZE() argument 1039 A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL() argument 1047 A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) A3XX_GRAS_SU_POLY_OFFSET_OFFSET() argument 1058 A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH() argument 1067 A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) A3XX_GRAS_SC_CONTROL_RENDER_MODE() argument 1073 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES() argument 1079 A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) A3XX_GRAS_SC_CONTROL_RASTER_MODE() argument 1088 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X() argument 1094 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y() argument 1103 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X() argument 1109 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y() argument 1118 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X() argument 1124 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y() argument 1133 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X() argument 1139 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y() argument 1148 A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) A3XX_RB_MODE_CONTROL_RENDER_MODE() argument 1154 A3XX_RB_MODE_CONTROL_MRT(uint32_t val) A3XX_RB_MODE_CONTROL_MRT() argument 1168 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) A3XX_RB_RENDER_CONTROL_BIN_WIDTH() argument 1176 A3XX_RB_RENDER_CONTROL_COORD_MASK(uint32_t val) A3XX_RB_RENDER_CONTROL_COORD_MASK() argument 1185 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC() argument 1196 A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) A3XX_RB_MSAA_CONTROL_SAMPLES() argument 1202 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) A3XX_RB_MSAA_CONTROL_SAMPLE_MASK() argument 1210 A3XX_RB_ALPHA_REF_UINT(uint32_t val) A3XX_RB_ALPHA_REF_UINT() argument 1216 A3XX_RB_ALPHA_REF_FLOAT(float val) A3XX_RB_ALPHA_REF_FLOAT() argument 1229 A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) A3XX_RB_MRT_CONTROL_ROP_CODE() argument 1235 A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) A3XX_RB_MRT_CONTROL_DITHER_MODE() argument 1241 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE() argument 1249 A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT() argument 1255 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE() argument 1261 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) A3XX_RB_MRT_BUF_INFO_COLOR_SWAP() argument 1268 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH() argument 1276 A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE() argument 1284 A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR() argument 1290 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE() argument 1296 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR() argument 1302 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR() argument 1308 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE() argument 1314 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR() argument 1323 A3XX_RB_BLEND_RED_UINT(uint32_t val) A3XX_RB_BLEND_RED_UINT() argument 1329 A3XX_RB_BLEND_RED_FLOAT(float val) A3XX_RB_BLEND_RED_FLOAT() argument 1337 A3XX_RB_BLEND_GREEN_UINT(uint32_t val) A3XX_RB_BLEND_GREEN_UINT() argument 1343 A3XX_RB_BLEND_GREEN_FLOAT(float val) A3XX_RB_BLEND_GREEN_FLOAT() argument 1351 A3XX_RB_BLEND_BLUE_UINT(uint32_t val) A3XX_RB_BLEND_BLUE_UINT() argument 1357 A3XX_RB_BLEND_BLUE_FLOAT(float val) A3XX_RB_BLEND_BLUE_FLOAT() argument 1365 A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) A3XX_RB_BLEND_ALPHA_UINT() argument 1371 A3XX_RB_BLEND_ALPHA_FLOAT(float val) A3XX_RB_BLEND_ALPHA_FLOAT() argument 1387 A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) A3XX_RB_COPY_CONTROL_MSAA_RESOLVE() argument 1394 A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) A3XX_RB_COPY_CONTROL_MODE() argument 1401 A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) A3XX_RB_COPY_CONTROL_FASTCLEAR() argument 1408 A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) A3XX_RB_COPY_CONTROL_GMEM_BASE() argument 1416 A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) A3XX_RB_COPY_DEST_BASE_BASE() argument 1424 A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) A3XX_RB_COPY_DEST_PITCH_PITCH() argument 1432 A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) A3XX_RB_COPY_DEST_INFO_TILE() argument 1438 A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) A3XX_RB_COPY_DEST_INFO_FORMAT() argument 1444 A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) A3XX_RB_COPY_DEST_INFO_SWAP() argument 1450 A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) A3XX_RB_COPY_DEST_INFO_DITHER_MODE() argument 1456 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE() argument 1462 A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) A3XX_RB_COPY_DEST_INFO_ENDIAN() argument 1474 A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) A3XX_RB_DEPTH_CONTROL_ZFUNC() argument 1486 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) A3XX_RB_DEPTH_INFO_DEPTH_FORMAT() argument 1492 A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) A3XX_RB_DEPTH_INFO_DEPTH_BASE() argument 1500 A3XX_RB_DEPTH_PITCH(uint32_t val) A3XX_RB_DEPTH_PITCH() argument 1511 A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) A3XX_RB_STENCIL_CONTROL_FUNC() argument 1517 A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_FAIL() argument 1523 A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZPASS() argument 1529 A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZFAIL() argument 1535 A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) A3XX_RB_STENCIL_CONTROL_FUNC_BF() argument 1541 A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_FAIL_BF() argument 1547 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZPASS_BF() argument 1553 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) A3XX_RB_STENCIL_CONTROL_ZFAIL_BF() argument 1563 A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) A3XX_RB_STENCIL_INFO_STENCIL_BASE() argument 1571 A3XX_RB_STENCIL_PITCH(uint32_t val) A3XX_RB_STENCIL_PITCH() argument 1579 A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) A3XX_RB_STENCILREFMASK_STENCILREF() argument 1585 A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) A3XX_RB_STENCILREFMASK_STENCILMASK() argument 1591 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) A3XX_RB_STENCILREFMASK_STENCILWRITEMASK() argument 1599 A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) A3XX_RB_STENCILREFMASK_BF_STENCILREF() argument 1605 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) A3XX_RB_STENCILREFMASK_BF_STENCILMASK() argument 1611 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK() argument 1622 A3XX_RB_WINDOW_OFFSET_X(uint32_t val) A3XX_RB_WINDOW_OFFSET_X() argument 1628 A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) A3XX_RB_WINDOW_OFFSET_Y() argument 1650 A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) A3XX_PC_VSTREAM_CONTROL_SIZE() argument 1656 A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) A3XX_PC_VSTREAM_CONTROL_N() argument 1666 A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC() argument 1672 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE() argument 1678 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE() argument 1692 A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE() argument 1702 A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val) A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC() argument 1710 A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) A3XX_HLSQ_CONTROL_0_REG_CONSTMODE() argument 1722 A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE() argument 1729 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val) A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID() argument 1735 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val) A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID() argument 1743 A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val) A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID() argument 1749 A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val) A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID() argument 1755 A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD() argument 1763 A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(uint32_t val) A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID() argument 1769 A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(uint32_t val) A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID() argument 1775 A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(uint32_t val) A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID() argument 1781 A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(uint32_t val) A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID() argument 1789 A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH() argument 1795 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET() argument 1801 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH() argument 1809 A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH() argument 1815 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET() argument 1821 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH() argument 1829 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY() argument 1835 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY() argument 1843 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY() argument 1849 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY() argument 1857 A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM() argument 1863 A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0() argument 1869 A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1() argument 1875 A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2() argument 1905 A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) A3XX_VFD_CONTROL_0_TOTALATTRTOVS() argument 1911 A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) A3XX_VFD_CONTROL_0_PACKETSIZE() argument 1917 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) A3XX_VFD_CONTROL_0_STRMDECINSTRCNT() argument 1923 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT() argument 1931 A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) A3XX_VFD_CONTROL_1_MAXSTORAGE() argument 1937 A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val) A3XX_VFD_CONTROL_1_MAXTHRESHOLD() argument 1943 A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val) A3XX_VFD_CONTROL_1_MINTHRESHOLD() argument 1949 A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) A3XX_VFD_CONTROL_1_REGID4VTX() argument 1955 A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) A3XX_VFD_CONTROL_1_REGID4INST() argument 1973 A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_FETCHSIZE() argument 1979 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE() argument 1987 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_INDEXCODE() argument 1993 A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) A3XX_VFD_FETCH_INSTR_0_STEPRATE() argument 2005 A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) A3XX_VFD_DECODE_INSTR_WRITEMASK() argument 2012 A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) A3XX_VFD_DECODE_INSTR_FORMAT() argument 2018 A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) A3XX_VFD_DECODE_INSTR_REGID() argument 2025 A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) A3XX_VFD_DECODE_INSTR_SWAP() argument 2031 A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) A3XX_VFD_DECODE_INSTR_SHIFTCNT() argument 2041 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD() argument 2047 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT() argument 2055 A3XX_VPC_ATTR_TOTALATTR(uint32_t val) A3XX_VPC_ATTR_TOTALATTR() argument 2062 A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) A3XX_VPC_ATTR_THRDASSIGN() argument 2068 A3XX_VPC_ATTR_LMSIZE(uint32_t val) A3XX_VPC_ATTR_LMSIZE() argument 2076 A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) A3XX_VPC_PACK_NUMFPNONPOSVAR() argument 2082 A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) A3XX_VPC_PACK_NUMNONPOSVSVAR() argument 2092 A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C0() argument 2098 A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C1() argument 2104 A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C2() argument 2110 A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C3() argument 2116 A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C4() argument 2122 A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C5() argument 2128 A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C6() argument 2134 A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C7() argument 2140 A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C8() argument 2146 A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_C9() argument 2152 A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CA() argument 2158 A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CB() argument 2164 A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CC() argument 2170 A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CD() argument 2176 A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CE() argument 2182 A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) A3XX_VPC_VARYING_INTERP_MODE_CF() argument 2192 A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C0() argument 2198 A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C1() argument 2204 A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C2() argument 2210 A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C3() argument 2216 A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C4() argument 2222 A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C5() argument 2228 A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C6() argument 2234 A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C7() argument 2240 A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C8() argument 2246 A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_C9() argument 2252 A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CA() argument 2258 A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CB() argument 2264 A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CC() argument 2270 A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CD() argument 2276 A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CE() argument 2282 A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) A3XX_VPC_VARYING_PS_REPL_MODE_CF() argument 2295 A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) A3XX_SP_SP_CTRL_REG_CONSTMODE() argument 2302 A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) A3XX_SP_SP_CTRL_REG_SLEEPMODE() argument 2308 A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) A3XX_SP_SP_CTRL_REG_L0MODE() argument 2316 A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A3XX_SP_VS_CTRL_REG0_THREADMODE() argument 2322 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE() argument 2330 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT() argument 2336 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT() argument 2342 A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A3XX_SP_VS_CTRL_REG0_THREADSIZE() argument 2349 A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) A3XX_SP_VS_CTRL_REG0_LENGTH() argument 2357 A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) A3XX_SP_VS_CTRL_REG1_CONSTLENGTH() argument 2363 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT() argument 2369 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING() argument 2377 A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) A3XX_SP_VS_PARAM_REG_POSREGID() argument 2383 A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) A3XX_SP_VS_PARAM_REG_PSIZEREGID() argument 2390 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR() argument 2400 A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) A3XX_SP_VS_OUT_REG_A_REGID() argument 2407 A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) A3XX_SP_VS_OUT_REG_A_COMPMASK() argument 2413 A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) A3XX_SP_VS_OUT_REG_B_REGID() argument 2420 A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) A3XX_SP_VS_OUT_REG_B_COMPMASK() argument 2430 A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC0() argument 2436 A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC1() argument 2442 A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC2() argument 2448 A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) A3XX_SP_VS_VPC_DST_REG_OUTLOC3() argument 2456 A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET() argument 2462 A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument 2468 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument 2478 A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM() argument 2484 A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET() argument 2490 A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD() argument 2498 A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN() argument 2504 A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS() argument 2514 A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) A3XX_SP_VS_LENGTH_REG_SHADERLENGTH() argument 2522 A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) A3XX_SP_FS_CTRL_REG0_THREADMODE() argument 2528 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE() argument 2536 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT() argument 2542 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT() argument 2551 A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) A3XX_SP_FS_CTRL_REG0_THREADSIZE() argument 2560 A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) A3XX_SP_FS_CTRL_REG0_LENGTH() argument 2568 A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) A3XX_SP_FS_CTRL_REG1_CONSTLENGTH() argument 2574 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT() argument 2580 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING() argument 2586 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET() argument 2594 A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET() argument 2600 A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET() argument 2606 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET() argument 2616 A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM() argument 2622 A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET() argument 2628 A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD() argument 2636 A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN() argument 2642 A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS() argument 2656 A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) A3XX_SP_FS_OUTPUT_REG_MRT() argument 2663 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID() argument 2673 A3XX_SP_FS_MRT_REG_REGID(uint32_t val) A3XX_SP_FS_MRT_REG_REGID() argument 2686 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT() argument 2694 A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) A3XX_SP_FS_LENGTH_REG_SHADERLENGTH() argument 2704 A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET() argument 2710 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET() argument 2716 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR() argument 2726 A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET() argument 2732 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET() argument 2738 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR() argument 2822 A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) A3XX_VSC_BIN_SIZE_WIDTH() argument 2828 A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) A3XX_VSC_BIN_SIZE_HEIGHT() argument 2840 A3XX_VSC_PIPE_CONFIG_X(uint32_t val) A3XX_VSC_PIPE_CONFIG_X() argument 2846 A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) A3XX_VSC_PIPE_CONFIG_Y() argument 2852 A3XX_VSC_PIPE_CONFIG_W(uint32_t val) A3XX_VSC_PIPE_CONFIG_W() argument 2858 A3XX_VSC_PIPE_CONFIG_H(uint32_t val) A3XX_VSC_PIPE_CONFIG_H() argument 2911 A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument 2917 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument 2965 A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR() argument 2973 A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR() argument 2979 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE() argument 3026 A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE() argument 3032 A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT() argument 3038 A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) A3XX_VGT_DRAW_INITIATOR_VIS_CULL() argument 3044 A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE() argument 3053 A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES() argument 3065 A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) A3XX_TEX_SAMP_0_XY_MAG() argument 3071 A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) A3XX_TEX_SAMP_0_XY_MIN() argument 3077 A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) A3XX_TEX_SAMP_0_WRAP_S() argument 3083 A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) A3XX_TEX_SAMP_0_WRAP_T() argument 3089 A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) A3XX_TEX_SAMP_0_WRAP_R() argument 3095 A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) A3XX_TEX_SAMP_0_ANISO() argument 3101 A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) A3XX_TEX_SAMP_0_COMPARE_FUNC() argument 3111 A3XX_TEX_SAMP_1_LOD_BIAS(float val) A3XX_TEX_SAMP_1_LOD_BIAS() argument 3117 A3XX_TEX_SAMP_1_MAX_LOD(float val) A3XX_TEX_SAMP_1_MAX_LOD() argument 3123 A3XX_TEX_SAMP_1_MIN_LOD(float val) A3XX_TEX_SAMP_1_MIN_LOD() argument 3131 A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val) A3XX_TEX_CONST_0_TILE_MODE() argument 3138 A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_X() argument 3144 A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_Y() argument 3150 A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_Z() argument 3156 A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) A3XX_TEX_CONST_0_SWIZ_W() argument 3162 A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) A3XX_TEX_CONST_0_MIPLVLS() argument 3168 A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val) A3XX_TEX_CONST_0_MSAATEX() argument 3174 A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) A3XX_TEX_CONST_0_FMT() argument 3181 A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) A3XX_TEX_CONST_0_TYPE() argument 3189 A3XX_TEX_CONST_1_HEIGHT(uint32_t val) A3XX_TEX_CONST_1_HEIGHT() argument 3195 A3XX_TEX_CONST_1_WIDTH(uint32_t val) A3XX_TEX_CONST_1_WIDTH() argument 3201 A3XX_TEX_CONST_1_PITCHALIGN(uint32_t val) A3XX_TEX_CONST_1_PITCHALIGN() argument 3209 A3XX_TEX_CONST_2_INDX(uint32_t val) A3XX_TEX_CONST_2_INDX() argument 3215 A3XX_TEX_CONST_2_PITCH(uint32_t val) A3XX_TEX_CONST_2_PITCH() argument 3221 A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) A3XX_TEX_CONST_2_SWAP() argument 3229 A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) A3XX_TEX_CONST_3_LAYERSZ1() argument 3235 A3XX_TEX_CONST_3_DEPTH(uint32_t val) A3XX_TEX_CONST_3_DEPTH() argument 3241 A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) A3XX_TEX_CONST_3_LAYERSZ2() argument [all...]
/kernel/linux/linux-5.10/drivers/phy/
H A D	phy-xgene.c	554 u32 val; in sds_wr() local 564 val = readl(csr_base + indirect_cmd_reg); in sds_wr() 565 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr() 567 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr() 576 u32 val; in sds_rd() local 584 val = readl(csr_base + indirect_cmd_reg); in sds_rd() 585 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd() 588 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd() 597 u32 val; in cmu_wr() local 606 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr() 627 u32 val; cmu_toggle1to0() local 640 u32 val; cmu_clrbits() local 650 u32 val; cmu_setbits() local 660 u32 val; serdes_wr() local 686 u32 val; serdes_clrbits() local 696 u32 val; serdes_setbits() local 707 u32 val; xgene_phy_cfg_cmu_clk_type() local 761 u32 val; xgene_phy_sata_cfg_cmu_core() local 915 u32 val; xgene_phy_ssc_enable() local 940 u32 val; xgene_phy_sata_cfg_lanes() local 1139 u32 val; xgene_phy_cal_rdy_chk() local 1237 u32 val; xgene_phy_pdwn_force_vco() local 1255 u32 val; xgene_phy_hw_init_sata() local 1347 u32 val; xgene_phy_force_lat_summer_cal() member 1434 u32 val; xgene_phy_gen_avg_val() local [all...]
/kernel/linux/linux-6.6/drivers/phy/
H A D	phy-xgene.c	555 u32 val; in sds_wr() local 565 val = readl(csr_base + indirect_cmd_reg); in sds_wr() 566 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr() 568 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr() 577 u32 val; in sds_rd() local 585 val = readl(csr_base + indirect_cmd_reg); in sds_rd() 586 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd() 589 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd() 598 u32 val; in cmu_wr() local 607 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr() 628 u32 val; cmu_toggle1to0() local 641 u32 val; cmu_clrbits() local 651 u32 val; cmu_setbits() local 661 u32 val; serdes_wr() local 687 u32 val; serdes_clrbits() local 697 u32 val; serdes_setbits() local 708 u32 val; xgene_phy_cfg_cmu_clk_type() local 762 u32 val; xgene_phy_sata_cfg_cmu_core() local 916 u32 val; xgene_phy_ssc_enable() local 941 u32 val; xgene_phy_sata_cfg_lanes() local 1141 u32 val; xgene_phy_cal_rdy_chk() local 1239 u32 val; xgene_phy_pdwn_force_vco() local 1257 u32 val; xgene_phy_hw_init_sata() local 1349 u32 val; xgene_phy_force_lat_summer_cal() member 1436 u32 val; xgene_phy_gen_avg_val() local [all...]
/kernel/linux/linux-5.10/arch/mips/include/asm/
H A D	mipsregs.h	1392 #define write_r10k_perf_cntr(counter,val) \ 1397 : "r" (val), "i" (counter)); \ 1411 #define write_r10k_perf_cntl(counter,val) \ 1416 : "r" (val), "i" (counter)); \ 1518 #define __write_ulong_c0_register(reg, sel, val) \ 1521 __write_32bit_c0_register(reg, sel, val); \ 1523 __write_64bit_c0_register(reg, sel, val); \ 1577 #define __write_64bit_c0_split(source, sel, val) \ 1579 unsigned long long __tmp = (val); \ 1656 #define write_c0_index(val) __write_32bit_c0_registe [all...]
/kernel/linux/linux-6.6/arch/mips/include/asm/
H A D	mipsregs.h	1383 #define write_r10k_perf_cntr(counter,val) \ 1388 : "r" (val), "i" (counter)); \ 1402 #define write_r10k_perf_cntl(counter,val) \ 1407 : "r" (val), "i" (counter)); \ 1509 #define __write_ulong_c0_register(reg, sel, val) \ 1512 __write_32bit_c0_register(reg, sel, val); \ 1514 __write_64bit_c0_register(reg, sel, val); \ 1568 #define __write_64bit_c0_split(source, sel, val) \ 1570 unsigned long long __tmp = (val); \ 1655 #define write_c0_index(val) __write_32bit_c0_registe [all...]
/kernel/linux/linux-6.6/tools/perf/util/
H A D	expr.y	38 double val; 73 /* During computing ids, does val represent a constant (non-BOTTOM) value? */ 74 static bool is_const(double val) 76 return isfinite(val); 82 .val = BOTTOM, 100 result.val = NAN; 102 result.val = source_count 113 result.val = BOTTOM; 129 if (!compute_ids || (is_const(LHS.val) && is_const(RHS.val))) { \ [all...]
/kernel/linux/linux-5.10/arch/mips/pci/
H A D	pci-bcm63xx.c	109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg) in bcm63xx_int_cfg_writel() argument 116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG); in bcm63xx_int_cfg_writel() 123 u32 val; in bcm63xx_reset_pcie() local 132 val = bcm_misc_readl(reg); in bcm63xx_reset_pcie() 133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; in bcm63xx_reset_pcie() 134 bcm_misc_writel(val, reg); in bcm63xx_reset_pcie() 152 u32 val; in bcm63xx_register_pcie() local 164 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); in bcm63xx_register_pcie() 165 val |= OPT1_RD_BE_OPT_EN; in bcm63xx_register_pcie() 166 val | in bcm63xx_register_pcie() 214 u32 val; bcm63xx_register_pci() local [all...]
/kernel/linux/linux-6.6/arch/mips/pci/
H A D	pci-bcm63xx.c	109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg) in bcm63xx_int_cfg_writel() argument 116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG); in bcm63xx_int_cfg_writel() 123 u32 val; in bcm63xx_reset_pcie() local 132 val = bcm_misc_readl(reg); in bcm63xx_reset_pcie() 133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; in bcm63xx_reset_pcie() 134 bcm_misc_writel(val, reg); in bcm63xx_reset_pcie() 152 u32 val; in bcm63xx_register_pcie() local 164 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); in bcm63xx_register_pcie() 165 val |= OPT1_RD_BE_OPT_EN; in bcm63xx_register_pcie() 166 val | in bcm63xx_register_pcie() 214 u32 val; bcm63xx_register_pci() local [all...]

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