Lines Matching refs:val
109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
123 u32 val;
132 val = bcm_misc_readl(reg);
133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
134 bcm_misc_writel(val, reg);
152 u32 val;
164 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
165 val |= OPT1_RD_BE_OPT_EN;
166 val |= OPT1_RD_REPLY_BE_FIX_EN;
167 val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
168 val |= OPT1_L1_INT_STATUS_MASK_POL;
169 bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
172 val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
173 val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
174 bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
176 val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
178 val |= OPT2_TX_CREDIT_CHK_EN;
179 val |= OPT2_UBUS_UR_DECODE_DIS;
182 val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
183 val |= OPT2_CFG_TYPE1_BD_SEL;
184 bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
187 val = bcm_pcie_readl(PCIE_IDVAL3_REG);
188 val &= ~IDVAL3_CLASS_CODE_MASK;
189 val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
190 bcm_pcie_writel(val, PCIE_IDVAL3_REG);
193 val = bcm_pcie_readl(PCIE_CONFIG2_REG);
194 val &= ~CONFIG2_BAR1_SIZE_MASK;
195 bcm_pcie_writel(val, PCIE_CONFIG2_REG);
198 val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
199 val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
200 val |= BASEMASK_REMAP_EN;
201 bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
203 val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
204 bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
214 u32 val;
229 val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
230 bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
232 bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
236 val = bcm_pcmcia_readl(PCMCIA_C1_REG);
237 val &= ~PCMCIA_C1_CBIDSEL_MASK;
238 val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
239 bcm_pcmcia_writel(val, PCMCIA_C1_REG);
243 val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
244 bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
246 val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
247 bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
258 val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
259 bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
261 bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
270 val = MPI_SP0_REMAP_ENABLE_MASK;
272 val = 0;
273 bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
296 val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
297 val &= ~REG_TIMER_RETRY_MASK;
298 bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
301 val = bcm63xx_int_cfg_readl(PCI_COMMAND);
302 val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
303 bcm63xx_int_cfg_writel(val, PCI_COMMAND);
307 val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
308 val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
309 val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
310 val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
311 val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
312 bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
315 val = bcm_mpi_readl(MPI_LOCINT_REG);
316 val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
317 bcm_mpi_writel(val, MPI_LOCINT_REG);