Lines Matching refs:val
554 u32 val;
564 val = readl(csr_base + indirect_cmd_reg);
565 } while (!(val & CFG_IND_CMD_DONE_MASK) &&
567 if (!(val & CFG_IND_CMD_DONE_MASK))
576 u32 val;
584 val = readl(csr_base + indirect_cmd_reg);
585 } while (!(val & CFG_IND_CMD_DONE_MASK) &&
588 if (!(val & CFG_IND_CMD_DONE_MASK))
597 u32 val;
606 SATA_ENET_SDS_IND_RDATA_REG, reg, &val);
607 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val);
627 u32 val;
629 cmu_rd(ctx, cmu_type, reg, &val);
630 val |= bits;
631 cmu_wr(ctx, cmu_type, reg, val);
632 cmu_rd(ctx, cmu_type, reg, &val);
633 val &= ~bits;
634 cmu_wr(ctx, cmu_type, reg, val);
640 u32 val;
642 cmu_rd(ctx, cmu_type, reg, &val);
643 val &= ~bits;
644 cmu_wr(ctx, cmu_type, reg, val);
650 u32 val;
652 cmu_rd(ctx, cmu_type, reg, &val);
653 val |= bits;
654 cmu_wr(ctx, cmu_type, reg, val);
660 u32 val;
667 SATA_ENET_SDS_IND_RDATA_REG, reg, &val);
669 val);
686 u32 val;
688 serdes_rd(ctx, lane, reg, &val);
689 val &= ~bits;
690 serdes_wr(ctx, lane, reg, val);
696 u32 val;
698 serdes_rd(ctx, lane, reg, &val);
699 val |= bits;
700 serdes_wr(ctx, lane, reg, val);
707 u32 val;
710 cmu_rd(ctx, cmu_type, CMU_REG12, &val);
711 val = CMU_REG12_STATE_DELAY9_SET(val, 0x1);
712 cmu_wr(ctx, cmu_type, CMU_REG12, val);
720 cmu_rd(ctx, cmu_type, CMU_REG0, &val);
721 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0);
722 cmu_wr(ctx, cmu_type, CMU_REG0, val);
724 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
725 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);
726 cmu_wr(ctx, cmu_type, CMU_REG1, val);
730 cmu_rd(ctx, cmu_type, CMU_REG0, &val);
731 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1);
732 cmu_wr(ctx, cmu_type, CMU_REG0, val);
734 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
735 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);
736 cmu_wr(ctx, cmu_type, CMU_REG1, val);
745 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
746 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);
747 cmu_wr(ctx, cmu_type, CMU_REG1, val);
749 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
750 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);
751 cmu_wr(ctx, cmu_type, CMU_REG1, val);
761 u32 val;
766 cmu_rd(ctx, cmu_type, CMU_REG34, &val);
767 val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7);
768 val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc);
769 val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3);
770 val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8);
771 cmu_wr(ctx, cmu_type, CMU_REG34, val);
775 cmu_rd(ctx, cmu_type, CMU_REG0, &val);
777 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4);
779 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7);
780 cmu_wr(ctx, cmu_type, CMU_REG0, val);
783 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
784 val = CMU_REG1_PLL_CP_SET(val, 0x1);
786 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5);
788 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3);
790 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);
792 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1);
793 cmu_wr(ctx, cmu_type, CMU_REG1, val);
799 cmu_rd(ctx, cmu_type, CMU_REG2, &val);
801 val = CMU_REG2_PLL_LFRES_SET(val, 0xa);
804 val = CMU_REG2_PLL_LFRES_SET(val, 0x3);
811 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_100M);
812 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_100M);
814 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_50M);
815 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_50M);
817 cmu_wr(ctx, cmu_type, CMU_REG2, val);
820 cmu_rd(ctx, cmu_type, CMU_REG3, &val);
822 val = CMU_REG3_VCOVARSEL_SET(val, 0x3);
823 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10);
825 val = CMU_REG3_VCOVARSEL_SET(val, 0xF);
827 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15);
829 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a);
830 val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15);
832 cmu_wr(ctx, cmu_type, CMU_REG3, val);
835 cmu_rd(ctx, cmu_type, CMU_REG26, &val);
836 val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0);
837 cmu_wr(ctx, cmu_type, CMU_REG26, val);
840 cmu_rd(ctx, cmu_type, CMU_REG5, &val);
841 val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3);
842 val = CMU_REG5_PLL_LFCAP_SET(val, 0x3);
844 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7);
846 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4);
847 cmu_wr(ctx, cmu_type, CMU_REG5, val);
850 cmu_rd(ctx, cmu_type, CMU_REG6, &val);
851 val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2);
852 val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0);
853 cmu_wr(ctx, cmu_type, CMU_REG6, val);
857 cmu_rd(ctx, cmu_type, CMU_REG9, &val);
858 val = CMU_REG9_TX_WORD_MODE_CH1_SET(val,
860 val = CMU_REG9_TX_WORD_MODE_CH0_SET(val,
862 val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1);
864 val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0);
865 val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0);
867 cmu_wr(ctx, cmu_type, CMU_REG9, val);
870 cmu_rd(ctx, cmu_type, CMU_REG10, &val);
871 val = CMU_REG10_VREG_REFSEL_SET(val, 0x1);
872 cmu_wr(ctx, cmu_type, CMU_REG10, val);
876 cmu_rd(ctx, cmu_type, CMU_REG16, &val);
877 val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1);
878 val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1);
880 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4);
882 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);
883 cmu_wr(ctx, cmu_type, CMU_REG16, val);
886 cmu_rd(ctx, cmu_type, CMU_REG30, &val);
887 val = CMU_REG30_PCIE_MODE_SET(val, 0x0);
888 val = CMU_REG30_LOCK_COUNT_SET(val, 0x3);
889 cmu_wr(ctx, cmu_type, CMU_REG30, val);
894 cmu_rd(ctx, cmu_type, CMU_REG32, &val);
895 val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3);
897 val = CMU_REG32_IREF_ADJ_SET(val, 0x3);
899 val = CMU_REG32_IREF_ADJ_SET(val, 0x1);
900 cmu_wr(ctx, cmu_type, CMU_REG32, val);
915 u32 val;
918 cmu_rd(ctx, cmu_type, CMU_REG35, &val);
919 val = CMU_REG35_PLL_SSC_MOD_SET(val, 98);
920 cmu_wr(ctx, cmu_type, CMU_REG35, val);
923 cmu_rd(ctx, cmu_type, CMU_REG36, &val);
924 val = CMU_REG36_PLL_SSC_VSTEP_SET(val, 30);
925 val = CMU_REG36_PLL_SSC_EN_SET(val, 1);
926 val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1);
927 cmu_wr(ctx, cmu_type, CMU_REG36, val);
940 u32 val;
949 serdes_rd(ctx, lane, RXTX_REG0, &val);
950 val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10);
951 val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10);
952 val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10);
953 serdes_wr(ctx, lane, RXTX_REG0, val);
956 serdes_rd(ctx, lane, RXTX_REG1, &val);
957 val = RXTX_REG1_RXACVCM_SET(val, 0x7);
958 val = RXTX_REG1_CTLE_EQ_SET(val,
961 serdes_wr(ctx, lane, RXTX_REG1, val);
965 serdes_rd(ctx, lane, RXTX_REG2, &val);
966 val = RXTX_REG2_VTT_ENA_SET(val, 0x1);
967 val = RXTX_REG2_VTT_SEL_SET(val, 0x1);
968 val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1);
969 serdes_wr(ctx, lane, RXTX_REG2, val);
972 serdes_rd(ctx, lane, RXTX_REG4, &val);
973 val = RXTX_REG4_TX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT);
974 serdes_wr(ctx, lane, RXTX_REG4, val);
977 serdes_rd(ctx, lane, RXTX_REG1, &val);
978 val = RXTX_REG1_RXVREG1_SET(val, 0x2);
979 val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2);
980 serdes_wr(ctx, lane, RXTX_REG1, val);
984 serdes_rd(ctx, lane, RXTX_REG5, &val);
985 val = RXTX_REG5_TX_CN1_SET(val,
988 val = RXTX_REG5_TX_CP1_SET(val,
991 val = RXTX_REG5_TX_CN2_SET(val,
994 serdes_wr(ctx, lane, RXTX_REG5, val);
997 serdes_rd(ctx, lane, RXTX_REG6, &val);
998 val = RXTX_REG6_TXAMP_CNTL_SET(val,
1001 val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1);
1002 val = RXTX_REG6_TX_IDLE_SET(val, 0x0);
1003 val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0);
1004 val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0);
1005 serdes_wr(ctx, lane, RXTX_REG6, val);
1008 serdes_rd(ctx, lane, RXTX_REG7, &val);
1009 val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0);
1010 val = RXTX_REG7_RX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT);
1011 serdes_wr(ctx, lane, RXTX_REG7, val);
1014 serdes_rd(ctx, lane, RXTX_REG8, &val);
1015 val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1);
1016 val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0);
1017 val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1);
1018 val = RXTX_REG8_SD_DISABLE_SET(val, 0x0);
1019 val = RXTX_REG8_SD_VREF_SET(val, 0x4);
1020 serdes_wr(ctx, lane, RXTX_REG8, val);
1023 serdes_rd(ctx, lane, RXTX_REG11, &val);
1024 val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0);
1025 serdes_wr(ctx, lane, RXTX_REG11, val);
1028 serdes_rd(ctx, lane, RXTX_REG12, &val);
1029 val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1);
1030 val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0);
1031 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0);
1032 serdes_wr(ctx, lane, RXTX_REG12, val);
1035 serdes_rd(ctx, lane, RXTX_REG26, &val);
1036 val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0);
1037 val = RXTX_REG26_BLWC_ENA_SET(val, 0x1);
1038 serdes_wr(ctx, lane, RXTX_REG26, val);
1046 serdes_rd(ctx, lane, RXTX_REG61, &val);
1047 val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1);
1048 val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0);
1049 val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0);
1050 serdes_wr(ctx, lane, RXTX_REG61, val);
1052 serdes_rd(ctx, lane, RXTX_REG62, &val);
1053 val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0);
1054 serdes_wr(ctx, lane, RXTX_REG62, val);
1059 serdes_rd(ctx, lane, reg, &val);
1060 val = RXTX_REG89_MU_TH7_SET(val, 0xe);
1061 val = RXTX_REG89_MU_TH8_SET(val, 0xe);
1062 val = RXTX_REG89_MU_TH9_SET(val, 0xe);
1063 serdes_wr(ctx, lane, reg, val);
1069 serdes_rd(ctx, lane, reg, &val);
1070 val = RXTX_REG96_MU_FREQ1_SET(val, 0x10);
1071 val = RXTX_REG96_MU_FREQ2_SET(val, 0x10);
1072 val = RXTX_REG96_MU_FREQ3_SET(val, 0x10);
1073 serdes_wr(ctx, lane, reg, val);
1079 serdes_rd(ctx, lane, reg, &val);
1080 val = RXTX_REG99_MU_PHASE1_SET(val, 0x7);
1081 val = RXTX_REG99_MU_PHASE2_SET(val, 0x7);
1082 val = RXTX_REG99_MU_PHASE3_SET(val, 0x7);
1083 serdes_wr(ctx, lane, reg, val);
1086 serdes_rd(ctx, lane, RXTX_REG102, &val);
1087 val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0);
1088 serdes_wr(ctx, lane, RXTX_REG102, val);
1092 serdes_rd(ctx, lane, RXTX_REG125, &val);
1093 val = RXTX_REG125_SIGN_PQ_SET(val,
1096 val = RXTX_REG125_PQ_REG_SET(val,
1099 val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1);
1100 serdes_wr(ctx, lane, RXTX_REG125, val);
1102 serdes_rd(ctx, lane, RXTX_REG127, &val);
1103 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0);
1104 serdes_wr(ctx, lane, RXTX_REG127, val);
1106 serdes_rd(ctx, lane, RXTX_REG128, &val);
1107 val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3);
1108 serdes_wr(ctx, lane, RXTX_REG128, val);
1110 serdes_rd(ctx, lane, RXTX_REG145, &val);
1111 val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3);
1112 val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0);
1114 val = RXTX_REG145_RXES_ENA_SET(val, 0x1);
1115 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1);
1117 val = RXTX_REG145_RXES_ENA_SET(val, 0x0);
1118 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0);
1120 serdes_wr(ctx, lane, RXTX_REG145, val);
1139 u32 val;
1153 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
1154 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);
1155 cmu_wr(ctx, cmu_type, CMU_REG1, val);
1179 cmu_rd(ctx, cmu_type, CMU_REG17, &val);
1180 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12);
1181 val = CMU_REG17_RESERVED_7_SET(val, 0x0);
1182 cmu_wr(ctx, cmu_type, CMU_REG17, val);
1190 cmu_rd(ctx, cmu_type, CMU_REG17, &val);
1191 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29);
1192 val = CMU_REG17_RESERVED_7_SET(val, 0x0);
1193 cmu_wr(ctx, cmu_type, CMU_REG17, val);
1197 cmu_rd(ctx, cmu_type, CMU_REG17, &val);
1198 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28);
1199 val = CMU_REG17_RESERVED_7_SET(val, 0x0);
1200 cmu_wr(ctx, cmu_type, CMU_REG17, val);
1208 cmu_rd(ctx, cmu_type, CMU_REG7, &val);
1209 if (CMU_REG7_PLL_CALIB_DONE_RD(val))
1218 cmu_rd(ctx, cmu_type, CMU_REG7, &val);
1220 CMU_REG7_PLL_CALIB_DONE_RD(val) ? "done" : "failed");
1221 if (CMU_REG7_VCO_CAL_FAIL_RD(val)) {
1228 cmu_rd(ctx, cmu_type, CMU_REG15, &val);
1229 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not ");
1237 u32 val;
1241 cmu_rd(ctx, cmu_type, CMU_REG16, &val);
1242 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);
1243 cmu_wr(ctx, cmu_type, CMU_REG16, val);
1255 u32 val;
1262 val = readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */
1271 val = readl(sds_base + SATA_ENET_SDS_CTL1);
1272 val = CFG_I_SPD_SEL_CDR_OVR1_SET(val,
1274 writel(val, sds_base + SATA_ENET_SDS_CTL1);
1277 val = readl(sds_base + SATA_ENET_SDS_CTL0);
1278 val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421);
1279 writel(val, sds_base + SATA_ENET_SDS_CTL0);
1295 val = readl(sds_base + SATA_ENET_SDS_PCS_CTL0);
1296 val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3);
1297 val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3);
1298 writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0);
1347 u32 val;
1405 serdes_reg[i].val);
1434 u32 val;
1458 serdes_rd(ctx, lane, RXTX_REG21, &val);
1459 lat_do_itr = RXTX_REG21_DO_LATCH_CALOUT_RD(val);
1460 lat_xo_itr = RXTX_REG21_XO_LATCH_CALOUT_RD(val);
1461 fail_odd = RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(val);
1463 serdes_rd(ctx, lane, RXTX_REG22, &val);
1464 lat_eo_itr = RXTX_REG22_EO_LATCH_CALOUT_RD(val);
1465 lat_so_itr = RXTX_REG22_SO_LATCH_CALOUT_RD(val);
1466 fail_even = RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(val);
1468 serdes_rd(ctx, lane, RXTX_REG23, &val);
1469 lat_de_itr = RXTX_REG23_DE_LATCH_CALOUT_RD(val);
1470 lat_xe_itr = RXTX_REG23_XE_LATCH_CALOUT_RD(val);
1472 serdes_rd(ctx, lane, RXTX_REG24, &val);
1473 lat_ee_itr = RXTX_REG24_EE_LATCH_CALOUT_RD(val);
1474 lat_se_itr = RXTX_REG24_SE_LATCH_CALOUT_RD(val);
1476 serdes_rd(ctx, lane, RXTX_REG121, &val);
1477 sum_cal_itr = RXTX_REG121_SUMOS_CAL_CODE_RD(val);
1510 serdes_rd(ctx, lane, RXTX_REG127, &val);
1511 val = RXTX_REG127_DO_LATCH_MANCAL_SET(val,
1513 val = RXTX_REG127_XO_LATCH_MANCAL_SET(val,
1515 serdes_wr(ctx, lane, RXTX_REG127, val);
1517 serdes_rd(ctx, lane, RXTX_REG128, &val);
1518 val = RXTX_REG128_EO_LATCH_MANCAL_SET(val,
1520 val = RXTX_REG128_SO_LATCH_MANCAL_SET(val,
1522 serdes_wr(ctx, lane, RXTX_REG128, val);
1524 serdes_rd(ctx, lane, RXTX_REG129, &val);
1525 val = RXTX_REG129_DE_LATCH_MANCAL_SET(val,
1527 val = RXTX_REG129_XE_LATCH_MANCAL_SET(val,
1529 serdes_wr(ctx, lane, RXTX_REG129, val);
1531 serdes_rd(ctx, lane, RXTX_REG130, &val);
1532 val = RXTX_REG130_EE_LATCH_MANCAL_SET(val,
1534 val = RXTX_REG130_SE_LATCH_MANCAL_SET(val,
1536 serdes_wr(ctx, lane, RXTX_REG130, val);
1539 serdes_rd(ctx, lane, RXTX_REG14, &val);
1540 val = RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(val,
1542 serdes_wr(ctx, lane, RXTX_REG14, val);
1558 serdes_rd(ctx, lane, RXTX_REG14, &val);
1559 val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1);
1560 serdes_wr(ctx, lane, RXTX_REG14, val);
1563 serdes_rd(ctx, lane, RXTX_REG127, &val);
1564 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1);
1566 serdes_wr(ctx, lane, RXTX_REG127, val);
1569 serdes_rd(ctx, lane, RXTX_REG12, &val);
1570 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0);
1571 serdes_wr(ctx, lane, RXTX_REG12, val);