Lines Matching refs:val
555 u32 val;
565 val = readl(csr_base + indirect_cmd_reg);
566 } while (!(val & CFG_IND_CMD_DONE_MASK) &&
568 if (!(val & CFG_IND_CMD_DONE_MASK))
577 u32 val;
585 val = readl(csr_base + indirect_cmd_reg);
586 } while (!(val & CFG_IND_CMD_DONE_MASK) &&
589 if (!(val & CFG_IND_CMD_DONE_MASK))
598 u32 val;
607 SATA_ENET_SDS_IND_RDATA_REG, reg, &val);
608 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val);
628 u32 val;
630 cmu_rd(ctx, cmu_type, reg, &val);
631 val |= bits;
632 cmu_wr(ctx, cmu_type, reg, val);
633 cmu_rd(ctx, cmu_type, reg, &val);
634 val &= ~bits;
635 cmu_wr(ctx, cmu_type, reg, val);
641 u32 val;
643 cmu_rd(ctx, cmu_type, reg, &val);
644 val &= ~bits;
645 cmu_wr(ctx, cmu_type, reg, val);
651 u32 val;
653 cmu_rd(ctx, cmu_type, reg, &val);
654 val |= bits;
655 cmu_wr(ctx, cmu_type, reg, val);
661 u32 val;
668 SATA_ENET_SDS_IND_RDATA_REG, reg, &val);
670 val);
687 u32 val;
689 serdes_rd(ctx, lane, reg, &val);
690 val &= ~bits;
691 serdes_wr(ctx, lane, reg, val);
697 u32 val;
699 serdes_rd(ctx, lane, reg, &val);
700 val |= bits;
701 serdes_wr(ctx, lane, reg, val);
708 u32 val;
711 cmu_rd(ctx, cmu_type, CMU_REG12, &val);
712 val = CMU_REG12_STATE_DELAY9_SET(val, 0x1);
713 cmu_wr(ctx, cmu_type, CMU_REG12, val);
721 cmu_rd(ctx, cmu_type, CMU_REG0, &val);
722 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0);
723 cmu_wr(ctx, cmu_type, CMU_REG0, val);
725 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
726 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);
727 cmu_wr(ctx, cmu_type, CMU_REG1, val);
731 cmu_rd(ctx, cmu_type, CMU_REG0, &val);
732 val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1);
733 cmu_wr(ctx, cmu_type, CMU_REG0, val);
735 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
736 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);
737 cmu_wr(ctx, cmu_type, CMU_REG1, val);
746 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
747 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);
748 cmu_wr(ctx, cmu_type, CMU_REG1, val);
750 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
751 val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);
752 cmu_wr(ctx, cmu_type, CMU_REG1, val);
762 u32 val;
767 cmu_rd(ctx, cmu_type, CMU_REG34, &val);
768 val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7);
769 val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc);
770 val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3);
771 val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8);
772 cmu_wr(ctx, cmu_type, CMU_REG34, val);
776 cmu_rd(ctx, cmu_type, CMU_REG0, &val);
778 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4);
780 val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7);
781 cmu_wr(ctx, cmu_type, CMU_REG0, val);
784 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
785 val = CMU_REG1_PLL_CP_SET(val, 0x1);
787 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5);
789 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3);
791 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);
793 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1);
794 cmu_wr(ctx, cmu_type, CMU_REG1, val);
800 cmu_rd(ctx, cmu_type, CMU_REG2, &val);
802 val = CMU_REG2_PLL_LFRES_SET(val, 0xa);
805 val = CMU_REG2_PLL_LFRES_SET(val, 0x3);
812 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_100M);
813 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_100M);
815 val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_50M);
816 val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_50M);
818 cmu_wr(ctx, cmu_type, CMU_REG2, val);
821 cmu_rd(ctx, cmu_type, CMU_REG3, &val);
823 val = CMU_REG3_VCOVARSEL_SET(val, 0x3);
824 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10);
826 val = CMU_REG3_VCOVARSEL_SET(val, 0xF);
828 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15);
830 val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a);
831 val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15);
833 cmu_wr(ctx, cmu_type, CMU_REG3, val);
836 cmu_rd(ctx, cmu_type, CMU_REG26, &val);
837 val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0);
838 cmu_wr(ctx, cmu_type, CMU_REG26, val);
841 cmu_rd(ctx, cmu_type, CMU_REG5, &val);
842 val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3);
843 val = CMU_REG5_PLL_LFCAP_SET(val, 0x3);
845 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7);
847 val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4);
848 cmu_wr(ctx, cmu_type, CMU_REG5, val);
851 cmu_rd(ctx, cmu_type, CMU_REG6, &val);
852 val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2);
853 val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0);
854 cmu_wr(ctx, cmu_type, CMU_REG6, val);
858 cmu_rd(ctx, cmu_type, CMU_REG9, &val);
859 val = CMU_REG9_TX_WORD_MODE_CH1_SET(val,
861 val = CMU_REG9_TX_WORD_MODE_CH0_SET(val,
863 val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1);
865 val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0);
866 val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0);
868 cmu_wr(ctx, cmu_type, CMU_REG9, val);
871 cmu_rd(ctx, cmu_type, CMU_REG10, &val);
872 val = CMU_REG10_VREG_REFSEL_SET(val, 0x1);
873 cmu_wr(ctx, cmu_type, CMU_REG10, val);
877 cmu_rd(ctx, cmu_type, CMU_REG16, &val);
878 val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1);
879 val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1);
881 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4);
883 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);
884 cmu_wr(ctx, cmu_type, CMU_REG16, val);
887 cmu_rd(ctx, cmu_type, CMU_REG30, &val);
888 val = CMU_REG30_PCIE_MODE_SET(val, 0x0);
889 val = CMU_REG30_LOCK_COUNT_SET(val, 0x3);
890 cmu_wr(ctx, cmu_type, CMU_REG30, val);
895 cmu_rd(ctx, cmu_type, CMU_REG32, &val);
896 val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3);
898 val = CMU_REG32_IREF_ADJ_SET(val, 0x3);
900 val = CMU_REG32_IREF_ADJ_SET(val, 0x1);
901 cmu_wr(ctx, cmu_type, CMU_REG32, val);
916 u32 val;
919 cmu_rd(ctx, cmu_type, CMU_REG35, &val);
920 val = CMU_REG35_PLL_SSC_MOD_SET(val, 98);
921 cmu_wr(ctx, cmu_type, CMU_REG35, val);
924 cmu_rd(ctx, cmu_type, CMU_REG36, &val);
925 val = CMU_REG36_PLL_SSC_VSTEP_SET(val, 30);
926 val = CMU_REG36_PLL_SSC_EN_SET(val, 1);
927 val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1);
928 cmu_wr(ctx, cmu_type, CMU_REG36, val);
941 u32 val;
950 serdes_rd(ctx, lane, RXTX_REG0, &val);
951 val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10);
952 val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10);
953 val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10);
954 serdes_wr(ctx, lane, RXTX_REG0, val);
957 serdes_rd(ctx, lane, RXTX_REG1, &val);
958 val = RXTX_REG1_RXACVCM_SET(val, 0x7);
959 val = RXTX_REG1_CTLE_EQ_SET(val,
962 serdes_wr(ctx, lane, RXTX_REG1, val);
967 serdes_rd(ctx, lane, RXTX_REG2, &val);
968 val = RXTX_REG2_VTT_ENA_SET(val, 0x1);
969 val = RXTX_REG2_VTT_SEL_SET(val, 0x1);
970 val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1);
971 serdes_wr(ctx, lane, RXTX_REG2, val);
974 serdes_rd(ctx, lane, RXTX_REG4, &val);
975 val = RXTX_REG4_TX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT);
976 serdes_wr(ctx, lane, RXTX_REG4, val);
979 serdes_rd(ctx, lane, RXTX_REG1, &val);
980 val = RXTX_REG1_RXVREG1_SET(val, 0x2);
981 val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2);
982 serdes_wr(ctx, lane, RXTX_REG1, val);
986 serdes_rd(ctx, lane, RXTX_REG5, &val);
987 val = RXTX_REG5_TX_CN1_SET(val,
990 val = RXTX_REG5_TX_CP1_SET(val,
993 val = RXTX_REG5_TX_CN2_SET(val,
996 serdes_wr(ctx, lane, RXTX_REG5, val);
999 serdes_rd(ctx, lane, RXTX_REG6, &val);
1000 val = RXTX_REG6_TXAMP_CNTL_SET(val,
1003 val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1);
1004 val = RXTX_REG6_TX_IDLE_SET(val, 0x0);
1005 val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0);
1006 val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0);
1007 serdes_wr(ctx, lane, RXTX_REG6, val);
1010 serdes_rd(ctx, lane, RXTX_REG7, &val);
1011 val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0);
1012 val = RXTX_REG7_RX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT);
1013 serdes_wr(ctx, lane, RXTX_REG7, val);
1016 serdes_rd(ctx, lane, RXTX_REG8, &val);
1017 val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1);
1018 val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0);
1019 val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1);
1020 val = RXTX_REG8_SD_DISABLE_SET(val, 0x0);
1021 val = RXTX_REG8_SD_VREF_SET(val, 0x4);
1022 serdes_wr(ctx, lane, RXTX_REG8, val);
1025 serdes_rd(ctx, lane, RXTX_REG11, &val);
1026 val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0);
1027 serdes_wr(ctx, lane, RXTX_REG11, val);
1030 serdes_rd(ctx, lane, RXTX_REG12, &val);
1031 val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1);
1032 val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0);
1033 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0);
1034 serdes_wr(ctx, lane, RXTX_REG12, val);
1037 serdes_rd(ctx, lane, RXTX_REG26, &val);
1038 val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0);
1039 val = RXTX_REG26_BLWC_ENA_SET(val, 0x1);
1040 serdes_wr(ctx, lane, RXTX_REG26, val);
1048 serdes_rd(ctx, lane, RXTX_REG61, &val);
1049 val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1);
1050 val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0);
1051 val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0);
1052 serdes_wr(ctx, lane, RXTX_REG61, val);
1054 serdes_rd(ctx, lane, RXTX_REG62, &val);
1055 val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0);
1056 serdes_wr(ctx, lane, RXTX_REG62, val);
1061 serdes_rd(ctx, lane, reg, &val);
1062 val = RXTX_REG89_MU_TH7_SET(val, 0xe);
1063 val = RXTX_REG89_MU_TH8_SET(val, 0xe);
1064 val = RXTX_REG89_MU_TH9_SET(val, 0xe);
1065 serdes_wr(ctx, lane, reg, val);
1071 serdes_rd(ctx, lane, reg, &val);
1072 val = RXTX_REG96_MU_FREQ1_SET(val, 0x10);
1073 val = RXTX_REG96_MU_FREQ2_SET(val, 0x10);
1074 val = RXTX_REG96_MU_FREQ3_SET(val, 0x10);
1075 serdes_wr(ctx, lane, reg, val);
1081 serdes_rd(ctx, lane, reg, &val);
1082 val = RXTX_REG99_MU_PHASE1_SET(val, 0x7);
1083 val = RXTX_REG99_MU_PHASE2_SET(val, 0x7);
1084 val = RXTX_REG99_MU_PHASE3_SET(val, 0x7);
1085 serdes_wr(ctx, lane, reg, val);
1088 serdes_rd(ctx, lane, RXTX_REG102, &val);
1089 val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0);
1090 serdes_wr(ctx, lane, RXTX_REG102, val);
1094 serdes_rd(ctx, lane, RXTX_REG125, &val);
1095 val = RXTX_REG125_SIGN_PQ_SET(val,
1098 val = RXTX_REG125_PQ_REG_SET(val,
1101 val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1);
1102 serdes_wr(ctx, lane, RXTX_REG125, val);
1104 serdes_rd(ctx, lane, RXTX_REG127, &val);
1105 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0);
1106 serdes_wr(ctx, lane, RXTX_REG127, val);
1108 serdes_rd(ctx, lane, RXTX_REG128, &val);
1109 val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3);
1110 serdes_wr(ctx, lane, RXTX_REG128, val);
1112 serdes_rd(ctx, lane, RXTX_REG145, &val);
1113 val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3);
1114 val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0);
1116 val = RXTX_REG145_RXES_ENA_SET(val, 0x1);
1117 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1);
1119 val = RXTX_REG145_RXES_ENA_SET(val, 0x0);
1120 val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0);
1122 serdes_wr(ctx, lane, RXTX_REG145, val);
1141 u32 val;
1155 cmu_rd(ctx, cmu_type, CMU_REG1, &val);
1156 val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);
1157 cmu_wr(ctx, cmu_type, CMU_REG1, val);
1181 cmu_rd(ctx, cmu_type, CMU_REG17, &val);
1182 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12);
1183 val = CMU_REG17_RESERVED_7_SET(val, 0x0);
1184 cmu_wr(ctx, cmu_type, CMU_REG17, val);
1192 cmu_rd(ctx, cmu_type, CMU_REG17, &val);
1193 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29);
1194 val = CMU_REG17_RESERVED_7_SET(val, 0x0);
1195 cmu_wr(ctx, cmu_type, CMU_REG17, val);
1199 cmu_rd(ctx, cmu_type, CMU_REG17, &val);
1200 val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28);
1201 val = CMU_REG17_RESERVED_7_SET(val, 0x0);
1202 cmu_wr(ctx, cmu_type, CMU_REG17, val);
1210 cmu_rd(ctx, cmu_type, CMU_REG7, &val);
1211 if (CMU_REG7_PLL_CALIB_DONE_RD(val))
1220 cmu_rd(ctx, cmu_type, CMU_REG7, &val);
1222 CMU_REG7_PLL_CALIB_DONE_RD(val) ? "done" : "failed");
1223 if (CMU_REG7_VCO_CAL_FAIL_RD(val)) {
1230 cmu_rd(ctx, cmu_type, CMU_REG15, &val);
1231 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not ");
1239 u32 val;
1243 cmu_rd(ctx, cmu_type, CMU_REG16, &val);
1244 val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);
1245 cmu_wr(ctx, cmu_type, CMU_REG16, val);
1257 u32 val;
1264 val = readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */
1273 val = readl(sds_base + SATA_ENET_SDS_CTL1);
1274 val = CFG_I_SPD_SEL_CDR_OVR1_SET(val,
1276 writel(val, sds_base + SATA_ENET_SDS_CTL1);
1279 val = readl(sds_base + SATA_ENET_SDS_CTL0);
1280 val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421);
1281 writel(val, sds_base + SATA_ENET_SDS_CTL0);
1297 val = readl(sds_base + SATA_ENET_SDS_PCS_CTL0);
1298 val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3);
1299 val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3);
1300 writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0);
1349 u32 val;
1407 serdes_reg[i].val);
1436 u32 val;
1460 serdes_rd(ctx, lane, RXTX_REG21, &val);
1461 lat_do_itr = RXTX_REG21_DO_LATCH_CALOUT_RD(val);
1462 lat_xo_itr = RXTX_REG21_XO_LATCH_CALOUT_RD(val);
1463 fail_odd = RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(val);
1465 serdes_rd(ctx, lane, RXTX_REG22, &val);
1466 lat_eo_itr = RXTX_REG22_EO_LATCH_CALOUT_RD(val);
1467 lat_so_itr = RXTX_REG22_SO_LATCH_CALOUT_RD(val);
1468 fail_even = RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(val);
1470 serdes_rd(ctx, lane, RXTX_REG23, &val);
1471 lat_de_itr = RXTX_REG23_DE_LATCH_CALOUT_RD(val);
1472 lat_xe_itr = RXTX_REG23_XE_LATCH_CALOUT_RD(val);
1474 serdes_rd(ctx, lane, RXTX_REG24, &val);
1475 lat_ee_itr = RXTX_REG24_EE_LATCH_CALOUT_RD(val);
1476 lat_se_itr = RXTX_REG24_SE_LATCH_CALOUT_RD(val);
1478 serdes_rd(ctx, lane, RXTX_REG121, &val);
1479 sum_cal_itr = RXTX_REG121_SUMOS_CAL_CODE_RD(val);
1512 serdes_rd(ctx, lane, RXTX_REG127, &val);
1513 val = RXTX_REG127_DO_LATCH_MANCAL_SET(val,
1515 val = RXTX_REG127_XO_LATCH_MANCAL_SET(val,
1517 serdes_wr(ctx, lane, RXTX_REG127, val);
1519 serdes_rd(ctx, lane, RXTX_REG128, &val);
1520 val = RXTX_REG128_EO_LATCH_MANCAL_SET(val,
1522 val = RXTX_REG128_SO_LATCH_MANCAL_SET(val,
1524 serdes_wr(ctx, lane, RXTX_REG128, val);
1526 serdes_rd(ctx, lane, RXTX_REG129, &val);
1527 val = RXTX_REG129_DE_LATCH_MANCAL_SET(val,
1529 val = RXTX_REG129_XE_LATCH_MANCAL_SET(val,
1531 serdes_wr(ctx, lane, RXTX_REG129, val);
1533 serdes_rd(ctx, lane, RXTX_REG130, &val);
1534 val = RXTX_REG130_EE_LATCH_MANCAL_SET(val,
1536 val = RXTX_REG130_SE_LATCH_MANCAL_SET(val,
1538 serdes_wr(ctx, lane, RXTX_REG130, val);
1541 serdes_rd(ctx, lane, RXTX_REG14, &val);
1542 val = RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(val,
1544 serdes_wr(ctx, lane, RXTX_REG14, val);
1560 serdes_rd(ctx, lane, RXTX_REG14, &val);
1561 val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1);
1562 serdes_wr(ctx, lane, RXTX_REG14, val);
1565 serdes_rd(ctx, lane, RXTX_REG127, &val);
1566 val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1);
1568 serdes_wr(ctx, lane, RXTX_REG127, val);
1571 serdes_rd(ctx, lane, RXTX_REG12, &val);
1572 val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0);
1573 serdes_wr(ctx, lane, RXTX_REG12, val);