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Searched refs:lane (Results 1 - 23 of 23) sorted by relevance

/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-naneng-edp.c34 #define EDP_PHY_TX_EMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 1, 4 * (lane))
36 #define EDP_PHY_TX_AMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 2, 4 * (lane))
39 #define EDP_PHY_TX_AMP_SCALE(lane, x) HIWORD_UPDATE(x, 2 * ((lane) + 1) - 1, 2 * (lane))
87 u8 lane; in rockchip_edp_phy_set_voltages() local
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H A Dphy-rockchip-usbdp.c304 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
308 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
312 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
316 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
501 prop = of_find_property(np, "rockchip,dp-lane-mux", &len); in udphy_parse_lane_mux_data()
503 dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n"); in udphy_parse_lane_mux_data()
511 dev_err(udphy->dev, "invalid number of lane mu in udphy_parse_lane_mux_data()
1293 rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u32 voltage, u32 pre, u32 lane) rk3588_dp_phy_set_voltage() argument
1313 u32 i, lane; rk3588_dp_phy_set_voltages() local
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H A Dphy-rockchip-csi2-dphy-hw.c290 static void csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw, int hsfreq, enum csi2_dphy_lane lane) in csi_mipidphy_wr_ths_settle() argument
295 switch (lane) { in csi_mipidphy_wr_ths_settle()
586 /* set data lane num and enable clock lane */ in csi2_dphy_hw_stream_on()
670 /* set clock lane and data lane */ in csi2_dphy_hw_stream_on()
795 /* set data lane */ in csi2_dcphy_hw_stream_on()
843 /* wait for clk lane ready */ in csi2_dcphy_hw_stream_on()
850 /* wait for data lane ready */ in csi2_dcphy_hw_stream_on()
H A Dphy-rockchip-mipi-rx.c631 static void csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq, enum mipi_dphy_lane lane) in csi_mipidphy_wr_ths_settle() argument
636 switch (lane) { in csi_mipidphy_wr_ths_settle()
1141 * step10.1:set clock lane in mipidphy_rx_stream_on()
1154 /* set lane num */ in mipidphy_rx_stream_on()
1248 * step10.1:set clock lane in mipidphy_txrx_stream_on()
1262 * Set lane num: in mipidphy_txrx_stream_on()
1303 /* set data lane num and enable clock lane */ in csi_mipidphy_stream_on()
1363 /* set clock lane and data lane */ in csi_mipidphy_stream_on()
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/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-edp.c35 #define EDP_PHY_TX_EMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 1, \
36 4 * (lane))
38 #define EDP_PHY_TX_AMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 2, \
39 4 * (lane))
42 #define EDP_PHY_TX_AMP_SCALE(lane, x) HIWORD_UPDATE(x, 2 * ((lane) + 1) - 1, \
43 2 * (lane))
92 u8 lane; in rockchip_edp_phy_set_voltages() local
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H A Dphy-rockchip-samsung-hdptx.c322 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset))
489 u8 lane) in rockchip_hdptx_phy_set_voltage()
493 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28), in rockchip_hdptx_phy_set_voltage()
499 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; in rockchip_hdptx_phy_set_voltage()
500 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28), in rockchip_hdptx_phy_set_voltage()
503 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c30), in rockchip_hdptx_phy_set_voltage()
506 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), in rockchip_hdptx_phy_set_voltage()
511 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][d in rockchip_hdptx_phy_set_voltage()
487 rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, struct phy_configure_opts_dp *dp, u8 lane) rockchip_hdptx_phy_set_voltage() argument
581 u8 lane; rockchip_hdptx_phy_set_voltages() local
967 u32 lane; rockchip_hdptx_phy_reset() local
1004 u32 lane; rockchip_hdptx_phy_power_on() local
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H A Dphy-rockchip-usbdp.c368 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
372 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
376 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
380 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
564 prop = of_find_property(np, "rockchip,dp-lane-mux", &len); in udphy_parse_lane_mux_data()
566 dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n"); in udphy_parse_lane_mux_data()
574 dev_err(udphy->dev, "invalid number of lane mu in udphy_parse_lane_mux_data()
1350 rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u32 voltage, u32 pre, u32 lane) rk3588_dp_phy_set_voltage() argument
1372 u32 i, lane; rk3588_dp_phy_set_voltages() local
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H A Dphy-rockchip-csi2-dphy-hw.c295 enum csi2_dphy_lane lane) in csi_mipidphy_wr_ths_settle()
300 switch (lane) { in csi_mipidphy_wr_ths_settle()
605 /* set data lane num and enable clock lane */ in csi2_dphy_hw_stream_on()
682 /* set clock lane and data lane */ in csi2_dphy_hw_stream_on()
801 /* set data lane */ in csi2_dcphy_hw_stream_on()
844 /*wait for clk lane ready*/ in csi2_dcphy_hw_stream_on()
849 /*wait for data lane ready*/ in csi2_dcphy_hw_stream_on()
293 csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw, int hsfreq, enum csi2_dphy_lane lane) csi_mipidphy_wr_ths_settle() argument
H A Dphy-rockchip-mipi-rx.c656 enum mipi_dphy_lane lane) in csi_mipidphy_wr_ths_settle()
661 switch (lane) { in csi_mipidphy_wr_ths_settle()
1169 * step10.1:set clock lane in mipidphy_rx_stream_on()
1182 /* set lane num */ in mipidphy_rx_stream_on()
1277 * step10.1:set clock lane in mipidphy_txrx_stream_on()
1291 * Set lane num: in mipidphy_txrx_stream_on()
1334 /* set data lane num and enable clock lane */ in csi_mipidphy_stream_on()
1390 /* set clock lane and data lane */ in csi_mipidphy_stream_on()
655 csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq, enum mipi_dphy_lane lane) csi_mipidphy_wr_ths_settle() argument
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/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c319 int lane, lane_count, retval; in analogix_dp_link_start() local
326 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_link_start()
327 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
358 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_link_start()
359 dp->link_train.training_lane[lane] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0; in analogix_dp_link_start()
372 for (lane in analogix_dp_link_start()
384 analogix_dp_get_lane_status(u8 link_status[2], int lane) analogix_dp_get_lane_status() argument
394 int lane; analogix_dp_clock_recovery_ok() local
408 int lane; analogix_dp_channel_eq_ok() local
426 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) analogix_dp_get_adjust_request_voltage() argument
434 analogix_dp_get_adjust_request_pre_emphasis(u8 adjust_request[0x2], int lane) analogix_dp_get_adjust_request_pre_emphasis() argument
452 int lane, lane_count; analogix_dp_get_adjust_training_lane() local
486 int lane, lane_count, retval; analogix_dp_process_clock_recovery() local
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H A Danalogix_dp_reg.c650 u8 lane; in analogix_dp_set_lane_link_training() local
653 for (lane = 0; lane < dp->link_train.lane_count; lane++) { in analogix_dp_set_lane_link_training()
654 analogix_dp_write(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane, dp->link_train.training_lane[lane]); in analogix_dp_set_lane_link_training()
660 for (lane = 0; lane < dp->link_train.lane_count; lane++) { in analogix_dp_set_lane_link_training()
661 u8 training_lane = dp->link_train.training_lane[lane]; in analogix_dp_set_lane_link_training()
683 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane) analogix_dp_get_lane_link_training() argument
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H A Danalogix_dp_core.h173 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane);
/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-typec.c618 * The PHY_PMA_LANE_CFG register is used to select whether a PMA lane in tcphy_set_lane_mapping()
716 static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_tx_usb3_cfg_lane() argument
718 writel(0x7799, tcphy->base + TX_PSC_A0(lane)); in tcphy_tx_usb3_cfg_lane()
719 writel(0x7798, tcphy->base + TX_PSC_A1(lane)); in tcphy_tx_usb3_cfg_lane()
720 writel(0x5098, tcphy->base + TX_PSC_A2(lane)); in tcphy_tx_usb3_cfg_lane()
721 writel(0x5098, tcphy->base + TX_PSC_A3(lane)); in tcphy_tx_usb3_cfg_lane()
722 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); in tcphy_tx_usb3_cfg_lane()
723 writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); in tcphy_tx_usb3_cfg_lane()
726 static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_rx_usb3_cfg_lane() argument
728 writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); in tcphy_rx_usb3_cfg_lane()
740 tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, int link_rate, u8 swing, u8 pre_emp, u32 lane) tcphy_dp_cfg_lane() argument
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/hi3516cv500/mipi_rx/
H A Dmipi_rx.c163 HI_ERR("When divide mode is LANE_DIVIDE_MODE_1, valid lane number cannot be greater than 2 !\n"); in check_lane_id()
422 /* phy lane config */ in mipi_set_lvds_phy_sync_cfg()
642 /* phy lane config */ in mipi_set_mipi_dev_attr()
1534 short lane; in proc_show_lvds_lane_detect_info() local
1544 for (lane = 0; lane < LVDS_LANE_NUM; lane++) { in proc_show_lvds_lane_detect_info()
1545 if (pstcombo_dev_attr->lvds_attr.lane_id[lane] != -1) { in proc_show_lvds_lane_detect_info()
1546 mipi_rx_drv_get_lvds_lane_imgsize_statis(devno_array[devno_idx], lane, &image_size); in proc_show_lvds_lane_detect_info()
1548 devno_array[devno_idx], pstcombo_dev_attr->lvds_attr.lane_id[lane], in proc_show_lvds_lane_detect_info()
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H A Dmipi_rx_hal.c1663 short get_sensor_lane_index(short lane, const short lane_id[LVDS_LANE_NUM]) in get_sensor_lane_index() argument
1668 if (lane_id[i] == lane) { in get_sensor_lane_index()
1688 short lane; in mipi_rx_drv_set_lvds_phy_sync_code() local
1697 lane = 0 + 4 * phy_id; /* 4 -- 1 phy have 4 lane */ in mipi_rx_drv_set_lvds_phy_sync_code()
1698 sensor_lane_idx = get_sensor_lane_index(lane, lane_id); in mipi_rx_drv_set_lvds_phy_sync_code()
1704 lane = 1 + 4 * phy_id; /* 4 -- 1 phy have 4 lane */ in mipi_rx_drv_set_lvds_phy_sync_code()
1705 sensor_lane_idx = get_sensor_lane_index(lane, lane_id); in mipi_rx_drv_set_lvds_phy_sync_code()
1711 lane in mipi_rx_drv_set_lvds_phy_sync_code()
2036 mipi_rx_drv_get_lvds_lane_imgsize_statis(combo_dev_t devno, short lane, img_size_t *p_size) mipi_rx_drv_get_lvds_lane_imgsize_statis() argument
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H A Dmipi_rx_hal.h180 void mipi_rx_drv_get_lvds_lane_imgsize_statis(combo_dev_t devno, short lane, img_size_t *p_size);
/device/soc/hisilicon/common/platform/mipi_csi/
H A Dmipi_rx_hi2121.c1658 short GetSensorLaneIndex(short lane, const short laneId[LVDS_LANE_NUM]) in GetSensorLaneIndex() argument
1663 if (laneId[i] == lane) { in GetSensorLaneIndex()
1681 short lane; in MipiRxDrvSetLvdsPhySyncCode() local
1690 lane = 0 + 4 * phyId; /* 4 -- 1 phy have 4 lane */ in MipiRxDrvSetLvdsPhySyncCode()
1691 sensorLaneIdx = GetSensorLaneIndex(lane, laneId); in MipiRxDrvSetLvdsPhySyncCode()
1697 lane = 1 + 4 * phyId; /* 4 -- 1 phy have 4 lane */ in MipiRxDrvSetLvdsPhySyncCode()
1698 sensorLaneIdx = GetSensorLaneIndex(lane, laneId); in MipiRxDrvSetLvdsPhySyncCode()
1704 lane in MipiRxDrvSetLvdsPhySyncCode()
2029 MipiRxDrvGetLvdsLaneImgsizeStatis(uint8_t devno, short lane, ImgSize *pSize) MipiRxDrvGetLvdsLaneImgsizeStatis() argument
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H A Dmipi_rx_hi2121.h103 void MipiRxDrvGetLvdsLaneImgsizeStatis(uint8_t devno, short lane, ImgSize *pSize);
H A Dmipi_csi_hi35xx.c145 HDF_LOGE("%s: When divide mode is LANE_DIVIDE_MODE_1, valid lane number cannot be greater than 2", __func__); in CheckLaneId()
404 /* phy lane config */ in MipiSetLvdsPhySyncCfg()
619 /* phy lane config */ in MipiSetMipiDevAttr()
1103 static void Hi35xxGetLvdsLaneImgsizeStatis(struct MipiCsiCntlr *cntlr, uint8_t devno, short lane, ImgSize *pSize) in Hi35xxGetLvdsLaneImgsizeStatis() argument
1106 MipiRxDrvGetLvdsLaneImgsizeStatis(devno, lane, pSize); in Hi35xxGetLvdsLaneImgsizeStatis()
/device/soc/rockchip/common/sdk_linux/include/linux/usb/
H A Dpd_vdo.h381 * <3> :: USB lanes supported (0b == one lane, 1b == two lanes)
416 #define VDO_ACABLE2(mtemp, stemp, u3p, trans, phy, ele, u4, hops, u2, u32, lane, iso, gen) \
418 (u4) << 8 | ((hops)&0x3) << 6 | (u2) << 5 | (u32) << 4 | (lane) << 3 | (iso) << 2 | (gen))
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Drkisp.c1504 u32 ret = 0, val, lane, data; in rkisp_config_lvds() local
1514 lane = 1; in rkisp_config_lvds()
1517 lane = 0x02; in rkisp_config_lvds()
1520 lane = 0x03; in rkisp_config_lvds()
1524 lane = 0x04; in rkisp_config_lvds()
1526 lane = BIT(lane) - 1; in rkisp_config_lvds()
1549 val = SW_LVDS_EN | SW_LVDS_WIDTH(data) | SW_LVDS_LANE_EN(lane) | cfg.mode; in rkisp_config_lvds()
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/
H A Drkisp.c1542 u32 ret = 0, val, lane, data; in rkisp_config_lvds() local
1551 lane = 1; in rkisp_config_lvds()
1554 lane = 2; in rkisp_config_lvds()
1557 lane = 3; in rkisp_config_lvds()
1561 lane = 4; in rkisp_config_lvds()
1563 lane = BIT(lane) - 1; in rkisp_config_lvds()
1586 val = SW_LVDS_EN | SW_LVDS_WIDTH(data) | SW_LVDS_LANE_EN(lane) | cfg.mode; in rkisp_config_lvds()
/device/soc/hisilicon/common/platform/mipi_dsi/
H A Dmipi_tx_hi35xx.c608 for (i = 0; i < cntlr->cfg.lane; i++) { in GetDevCfg()
973 /* fail will block mipi data lane, so need reset */ in MipiTxDrvGetCmdInfo()

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