1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip HDMI/DP Combo PHY with Samsung IP block
4 *
5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/kernel.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18
19 #define HDPTXPHY_GRF_CON0 0x0000
20 #define RO_REF_CLK_SEL GENMASK(11, 10)
21 #define LC_REF_CLK_SEL GENMASK(9, 8)
22 #define PLL_EN BIT(7)
23 #define BIAS_EN BIT(6)
24 #define BGR_EN BIT(5)
25 #define HDPTX_MODE_SEL BIT(0)
26 #define HDPTXPHY_GRF_STATUS0 0x0080
27 #define PLL_LOCK_DONE BIT(3)
28 #define PHY_CLK_RDY BIT(2)
29 #define PHY_RDY BIT(1)
30 #define SB_RDY BIT(0)
31
32 /* cmn_reg0008 */
33 #define OVRD_LCPLL_EN BIT(7)
34 #define LCPLL_EN BIT(6)
35
36 /* cmn_reg003C */
37 #define ANA_LCPLL_RESERVED7 BIT(7)
38
39 /* cmn_reg003D */
40 #define OVRD_ROPLL_EN BIT(7)
41 #define ROPLL_EN BIT(6)
42
43 /* cmn_reg0046 */
44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4)
45 #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0)
46
47 /* cmn_reg0047 */
48 #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3)
49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0)
50
51 /* cmn_reg004E */
52 #define ANA_ROPLL_PI_EN BIT(5)
53
54 /* cmn_reg0051 */
55 #define ROPLL_PMS_MDIV GENMASK(7, 0)
56
57 /* cmn_reg0055 */
58 #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0)
59
60 /* cmn_reg0059 */
61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4)
62 #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0)
63
64 /* cmn_reg005A */
65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4)
66 #define ROPLL_PMS_SDIV_HBR GENMASK(3, 0)
67
68 /* cmn_reg005B */
69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4)
70 #define ROPLL_PMS_SDIV_HBR3 GENMASK(3, 0)
71
72 /* cmn_reg005D */
73 #define OVRD_ROPLL_REF_CLK_SEL BIT(5)
74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3)
75
76 /* cmn_reg005E */
77 #define ANA_ROPLL_SDM_EN BIT(6)
78 #define OVRD_ROPLL_SDM_RSTN BIT(5)
79 #define ROPLL_SDM_RSTN BIT(4)
80 #define ROPLL_SDC_FRACTIONAL_EN_RBR BIT(3)
81 #define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2)
82 #define ROPLL_SDC_FRACTIONAL_EN_HBR2 BIT(1)
83 #define ROPLL_SDC_FRACTIONAL_EN_HBR3 BIT(0)
84
85 /* cmn_reg005F */
86 #define OVRD_ROPLL_SDC_RSTN BIT(5)
87 #define ROPLL_SDC_RSTN BIT(4)
88
89 /* cmn_reg0060 */
90 #define ROPLL_SDM_DENOMINATOR GENMASK(7, 0)
91
92 /* cmn_reg0064 */
93 #define ROPLL_SDM_NUMERATOR_SIGN_RBR BIT(3)
94 #define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2)
95 #define ROPLL_SDM_NUMERATOR_SIGN_HBR2 BIT(1)
96 #define ROPLL_SDM_NUMERATOR_SIGN_HBR3 BIT(0)
97
98 /* cmn_reg0065 */
99 #define ROPLL_SDM_NUMERATOR GENMASK(7, 0)
100
101 /* cmn_reg0069 */
102 #define ROPLL_SDC_N_RBR GENMASK(2, 0)
103
104 /* cmn_reg006A */
105 #define ROPLL_SDC_N_HBR GENMASK(5, 3)
106 #define ROPLL_SDC_N_HBR2 GENMASK(2, 0)
107
108 /* cmn_reg006B */
109 #define ROPLL_SDC_N_HBR3 GENMASK(3, 1)
110
111 /* cmn_reg006C */
112 #define ROPLL_SDC_NUMERATOR GENMASK(5, 0)
113
114 /* cmn_reg0070 */
115 #define ROPLL_SDC_DENOMINATOR GENMASK(5, 0)
116
117 /* cmn_reg0074 */
118 #define OVRD_ROPLL_SDC_NDIV_RSTN BIT(3)
119 #define ROPLL_SDC_NDIV_RSTN BIT(2)
120 #define OVRD_ROPLL_SSC_EN BIT(1)
121 #define ROPLL_SSC_EN BIT(0)
122
123 /* cmn_reg0075 */
124 #define ANA_ROPLL_SSC_FM_DEVIATION GENMASK(5, 0)
125
126 /* cmn_reg0076 */
127 #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2)
128
129 /* cmn_reg0077 */
130 #define ANA_ROPLL_SSC_CLK_DIV_SEL GENMASK(6, 3)
131
132 /* cmn_reg0081 */
133 #define ANA_PLL_CD_TX_SER_RATE_SEL BIT(3)
134 #define ANA_PLL_CD_HSCLK_WEST_EN BIT(1)
135 #define ANA_PLL_CD_HSCLK_EAST_EN BIT(0)
136
137 /* cmn_reg0082 */
138 #define ANA_PLL_CD_VREG_GAIN_CTRL GENMASK(3, 0)
139
140 /* cmn_reg0083 */
141 #define ANA_PLL_CD_VREG_ICTRL GENMASK(6, 5)
142
143 /* cmn_reg0084 */
144 #define PLL_LCRO_CLK_SEL BIT(5)
145
146 /* cmn_reg0085 */
147 #define ANA_PLL_SYNC_LOSS_DET_MODE GENMASK(1, 0)
148
149 /* cmn_reg0087 */
150 #define ANA_PLL_TX_HS_CLK_EN BIT(2)
151
152 /* cmn_reg0095 */
153 #define DP_TX_LINK_BW GENMASK(1, 0)
154
155 /* cmn_reg0097 */
156 #define DIG_CLK_SEL BIT(1)
157
158 /* cmn_reg0099 */
159 #define SSC_EN GENMASK(7, 6)
160 #define CMN_ROPLL_ALONE_MODE BIT(2)
161
162 /* cmn_reg009A */
163 #define HS_SPEED_SEL BIT(0)
164
165 /* cmn_reg009B */
166 #define LS_SPEED_SEL BIT(4)
167
168 /* sb_reg0102 */
169 #define OVRD_SB_RXTERM_EN BIT(5)
170 #define SB_RXRERM_EN BIT(4)
171 #define ANA_SB_RXTERM_OFFSP GENMASK(3, 0)
172
173 /* sb_reg0103 */
174 #define ANA_SB_RXTERM_OFFSN GENMASK(6, 3)
175 #define OVRD_SB_RX_RESCAL_DONE BIT(1)
176 #define SB_RX_RESCAL_DONE BIT(0)
177
178 /* sb_reg0104 */
179 #define OVRD_SB_EN BIT(5)
180 #define SB_EN BIT(4)
181 #define OVRD_SB_AUX_EN BIT(1)
182 #define SB_AUX_EN BIT(0)
183
184 /* sb_reg0105 */
185 #define ANA_SB_TX_HLVL_PROG GENMASK(2, 0)
186
187 /* sb_reg0106 */
188 #define ANA_SB_TX_LLVL_PROG GENMASK(6, 4)
189
190 /* sb_reg010D */
191 #define ANA_SB_DMRX_LPBK_DATA BIT(4)
192
193 /* sb_reg010F */
194 #define OVRD_SB_VREG_EN BIT(7)
195 #define SB_VREG_EN BIT(6)
196 #define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0)
197
198 /* sb_reg0110 */
199 #define ANA_SB_VREG_OUT_SEL BIT(1)
200 #define ANA_SB_VREG_REF_SEL BIT(0)
201
202 /* sb_reg0113 */
203 #define SB_RX_RCAL_OPT_CODE GENMASK(5, 4)
204 #define SB_RX_RTERM_CTRL GENMASK(3, 0)
205
206 /* sb_reg0114 */
207 #define SB_TG_SB_EN_DELAY_TIME GENMASK(5, 3)
208 #define SB_TG_RXTERN_EN_DELAY_TIME GENMASK(2, 0)
209
210 /* sb_reg0115 */
211 #define SB_READY_DELAY_TIME GENMASK(5, 3)
212 #define SB_TG_OSC_EN_DELAY_TIME GENMASK(2, 0)
213
214 /* sb_reg0116 */
215 #define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4)
216
217 /* sb_reg0117 */
218 #define SB_TG_PLL_CD_VREG_FAST_PULSE_TIME GENMASK(3, 0)
219
220 /* sb_reg0118 */
221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT GENMASK(7, 0)
222
223 /* sb_reg011A */
224 #define SB_TG_CNT_RUN_NO_7_0 GENMASK(7, 0)
225
226 /* sb_reg011B */
227 #define SB_EARC_SIG_DET_BYPASS BIT(4)
228 #define SB_AFC_TOL GENMASK(3, 0)
229
230 /* sb_reg011C */
231 #define SB_AFC_STB_NUM GENMASK(3, 0)
232
233 /* sb_reg011D */
234 #define SB_TG_OSC_CNT_MIN GENMASK(7, 0)
235
236 /* sb_reg011E */
237 #define SB_TG_OSC_CNT_MAX GENMASK(7, 0)
238
239 /* sb_reg011F */
240 #define SB_PWM_AFC_CTRL GENMASK(7, 2)
241 #define SB_RCAL_RSTN BIT(1)
242
243 /* sb_reg0120 */
244 #define SB_AUX_EN_IN BIT(7)
245
246 /* sb_reg0123 */
247 #define OVRD_SB_READY BIT(5)
248 #define SB_READY BIT(4)
249
250 /* lntop_reg0200 */
251 #define PROTOCOL_SEL BIT(2)
252
253 /* lntop_reg0206 */
254 #define DATA_BUS_WIDTH GENMASK(2, 1)
255 #define BUS_WIDTH_SEL BIT(0)
256
257 /* lntop_reg0207 */
258 #define LANE_EN GENMASK(3, 0)
259
260 /* lane_reg0301 */
261 #define OVRD_LN_TX_DRV_EI_EN BIT(7)
262 #define LN_TX_DRV_EI_EN BIT(6)
263
264 /* lane_reg0303 */
265 #define OVRD_LN_TX_DRV_LVL_CTRL BIT(5)
266 #define LN_TX_DRV_LVL_CTRL GENMASK(4, 0)
267
268 /* lane_reg0304 */
269 #define OVRD_LN_TX_DRV_POST_LVL_CTRL BIT(4)
270 #define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0)
271
272 /* lane_reg0305 */
273 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL BIT(6)
274 #define LN_TX_DRV_PRE_LVL_CTRL GENMASK(5, 2)
275
276 /* lane_reg0306 */
277 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL GENMASK(7, 5)
278 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL GENMASK(4, 2)
279 #define LN_ANA_TX_DRV_ACCDRV_EN BIT(0)
280
281 /* lane_reg0307 */
282 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL BIT(6)
283 #define LN_ANA_TX_DRV_ACCDRV_CTRL GENMASK(5, 3)
284
285 /* lane_reg030A */
286 #define LN_ANA_TX_JEQ_EN BIT(4)
287 #define LN_TX_JEQ_EVEN_CTRL_RBR GENMASK(3, 0)
288
289 /* lane_reg030B */
290 #define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4)
291 #define LN_TX_JEQ_EVEN_CTRL_HBR2 GENMASK(3, 0)
292
293 /* lane_reg030C */
294 #define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4)
295 #define LN_TX_JEQ_ODD_CTRL_RBR GENMASK(3, 0)
296
297 /* lane_reg030D */
298 #define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4)
299 #define LN_TX_JEQ_ODD_CTRL_HBR2 GENMASK(3, 0)
300
301 /* lane_reg030E */
302 #define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4)
303
304 /* lane_reg0310 */
305 #define LN_ANA_TX_SYNC_LOSS_DET_MODE GENMASK(1, 0)
306
307 /* lane_reg0311 */
308 #define LN_TX_SER_40BIT_EN_RBR BIT(3)
309 #define LN_TX_SER_40BIT_EN_HBR BIT(2)
310 #define LN_TX_SER_40BIT_EN_HBR2 BIT(1)
311 #define LN_TX_SER_40BIT_EN_HBR3 BIT(0)
312
313 /* lane_reg0316 */
314 #define LN_ANA_TX_SER_VREG_GAIN_CTRL GENMASK(3, 0)
315
316 /* lane_reg031B */
317 #define LN_ANA_TX_RESERVED GENMASK(7, 0)
318
319 /* lane_reg031E */
320 #define LN_POLARITY_INV BIT(2)
321
322 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset))
323
324 struct rockchip_hdptx_phy {
325 struct device *dev;
326 struct clk_bulk_data *clks;
327 int nr_clks;
328 struct reset_control *apb_reset;
329 struct reset_control *cmn_reset;
330 struct reset_control *init_reset;
331 struct reset_control *lane_reset;
332 struct regmap *regmap;
333 struct regmap *grf;
334 u32 lane_polarity_invert[4];
335 };
336
337 enum {
338 DP_BW_RBR,
339 DP_BW_HBR,
340 DP_BW_HBR2,
341 DP_BW_HBR3,
342 };
343
344 struct tx_drv_ctrl {
345 u8 tx_drv_lvl_ctrl;
346 u8 tx_drv_post_lvl_ctrl;
347 u8 ana_tx_drv_idrv_idn_ctrl;
348 u8 ana_tx_drv_idrv_iup_ctrl;
349 u8 ana_tx_drv_accdrv_en;
350 u8 ana_tx_drv_accdrv_ctrl;
351 };
352
353 static const struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = {
354 /* voltage swing 0, pre-emphasis 0->3 */
355 {
356 { 0x1, 0x0, 0x4, 0x6, 0x0, 0x4 },
357 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4 },
358 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4 },
359 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 },
360 },
361
362 /* voltage swing 1, pre-emphasis 0->2 */
363 {
364 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4 },
365 { 0xa, 0x5, 0x4, 0x6, 0x0, 0x4 },
366 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 },
367 },
368
369 /* voltage swing 2, pre-emphasis 0->1 */
370 {
371 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4 },
372 { 0xd, 0x5, 0x7, 0x7, 0x1, 0x7 },
373 },
374
375 /* voltage swing 3, pre-emphasis 0 */
376 {
377 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 },
378 }
379 };
380
381 static const struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = {
382 /* voltage swing 0, pre-emphasis 0->3 */
383 {
384 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 },
385 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 },
386 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4 },
387 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 },
388 },
389
390 /* voltage swing 1, pre-emphasis 0->2 */
391 {
392 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 },
393 { 0xb, 0x6, 0x4, 0x6, 0x0, 0x4 },
394 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 },
395 },
396
397 /* voltage swing 2, pre-emphasis 0->1 */
398 {
399 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 },
400 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 },
401 },
402
403 /* voltage swing 3, pre-emphasis 0 */
404 {
405 { 0xd, 0x1, 0x7, 0x7, 0x1, 0x4 },
406 }
407 };
408
409 static const struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = {
410 /* voltage swing 0, pre-emphasis 0->3 */
411 {
412 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 },
413 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 },
414 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4 },
415 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 },
416 },
417
418 /* voltage swing 1, pre-emphasis 0->2 */
419 {
420 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 },
421 { 0xc, 0x7, 0x4, 0x6, 0x0, 0x4 },
422 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 },
423 },
424
425 /* voltage swing 2, pre-emphasis 0->1 */
426 {
427 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 },
428 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 },
429 },
430
431 /* voltage swing 3, pre-emphasis 0 */
432 {
433 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 },
434 }
435 };
436
rockchip_grf_write(struct regmap *grf, unsigned int reg, unsigned int mask, unsigned int val)437 static int rockchip_grf_write(struct regmap *grf, unsigned int reg,
438 unsigned int mask, unsigned int val)
439 {
440 return regmap_write(grf, reg, (mask << 16) | (val & mask));
441 }
442
rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)443 static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode,
444 int submode)
445 {
446 return 0;
447 }
448
rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy *hdptx, struct phy_configure_opts_dp *dp)449 static int rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy *hdptx,
450 struct phy_configure_opts_dp *dp)
451 {
452 int i;
453
454 if (dp->set_rate) {
455 switch (dp->link_rate) {
456 case 1620:
457 case 2700:
458 case 5400:
459 break;
460 default:
461 return -EINVAL;
462 }
463 }
464
465 switch (dp->lanes) {
466 case 1:
467 case 2:
468 case 4:
469 break;
470 default:
471 return -EINVAL;
472 }
473
474 if (dp->set_voltages) {
475 for (i = 0; i < dp->lanes; i++) {
476 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
477 return -EINVAL;
478
479 if (dp->voltage[i] + dp->pre[i] > 3)
480 return -EINVAL;
481 }
482 }
483
484 return 0;
485 }
486
rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, struct phy_configure_opts_dp *dp, u8 lane)487 static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx,
488 struct phy_configure_opts_dp *dp,
489 u8 lane)
490 {
491 const struct tx_drv_ctrl *ctrl;
492
493 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28),
494 LN_ANA_TX_JEQ_EN,
495 FIELD_PREP(LN_ANA_TX_JEQ_EN, 0x1));
496
497 switch (dp->link_rate) {
498 case 1620:
499 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]];
500 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28),
501 LN_TX_JEQ_EVEN_CTRL_RBR,
502 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR, 0x7));
503 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c30),
504 LN_TX_JEQ_ODD_CTRL_RBR,
505 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR, 0x7));
506 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
507 LN_TX_SER_40BIT_EN_RBR,
508 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1));
509 break;
510 case 2700:
511 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];
512 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
513 LN_TX_JEQ_EVEN_CTRL_HBR,
514 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR, 0x7));
515 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
516 LN_TX_JEQ_ODD_CTRL_HBR,
517 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, 0x7));
518 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
519 LN_TX_SER_40BIT_EN_HBR,
520 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1));
521 break;
522 case 5400:
523 default:
524 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]];
525 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
526 LN_TX_JEQ_EVEN_CTRL_HBR2,
527 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, 0x7));
528 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
529 LN_TX_JEQ_ODD_CTRL_HBR2,
530 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, 0x7));
531 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
532 LN_TX_SER_40BIT_EN_HBR2,
533 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1));
534 break;
535 }
536
537 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c0c),
538 OVRD_LN_TX_DRV_LVL_CTRL | LN_TX_DRV_LVL_CTRL,
539 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL, 0x1) |
540 FIELD_PREP(LN_TX_DRV_LVL_CTRL,
541 ctrl->tx_drv_lvl_ctrl));
542
543 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c10),
544 OVRD_LN_TX_DRV_POST_LVL_CTRL |
545 LN_TX_DRV_POST_LVL_CTRL,
546 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL, 0x1) |
547 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL,
548 ctrl->tx_drv_post_lvl_ctrl));
549
550 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c18),
551 LN_ANA_TX_DRV_IDRV_IDN_CTRL |
552 LN_ANA_TX_DRV_IDRV_IUP_CTRL |
553 LN_ANA_TX_DRV_ACCDRV_EN,
554 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL,
555 ctrl->ana_tx_drv_idrv_idn_ctrl) |
556 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL,
557 ctrl->ana_tx_drv_idrv_iup_ctrl) |
558 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN,
559 ctrl->ana_tx_drv_accdrv_en));
560
561 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c1c),
562 LN_ANA_TX_DRV_ACCDRV_POL_SEL |
563 LN_ANA_TX_DRV_ACCDRV_CTRL,
564 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL, 0x1) |
565 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL,
566 ctrl->ana_tx_drv_accdrv_ctrl));
567 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c6c),
568 LN_ANA_TX_RESERVED,
569 FIELD_PREP(LN_ANA_TX_RESERVED, 0x1));
570 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c58),
571 LN_ANA_TX_SER_VREG_GAIN_CTRL,
572 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL, 0x2));
573 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c40),
574 LN_ANA_TX_SYNC_LOSS_DET_MODE,
575 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE, 0x3));
576 }
577
rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy *hdptx, struct phy_configure_opts_dp *dp)578 static int rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy *hdptx,
579 struct phy_configure_opts_dp *dp)
580 {
581 u8 lane;
582
583 for (lane = 0; lane < dp->lanes; lane++)
584 rockchip_hdptx_phy_set_voltage(hdptx, dp, lane);
585
586 return 0;
587 }
588
rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy *hdptx, struct phy_configure_opts_dp *dp)589 static int rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy *hdptx,
590 struct phy_configure_opts_dp *dp)
591 {
592 u32 bw, status;
593 int ret;
594
595 reset_control_assert(hdptx->lane_reset);
596 udelay(20);
597 reset_control_assert(hdptx->cmn_reset);
598 udelay(20);
599 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
600 FIELD_PREP(PLL_EN, 0x0));
601 udelay(20);
602 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN,
603 FIELD_PREP(LANE_EN, 0x0));
604
605 switch (dp->link_rate) {
606 case 1620:
607 bw = DP_BW_RBR;
608 break;
609 case 2700:
610 bw = DP_BW_HBR;
611 break;
612 case 5400:
613 bw = DP_BW_HBR2;
614 break;
615 default:
616 return -EINVAL;
617 }
618
619 regmap_update_bits(hdptx->regmap, 0x0254, DP_TX_LINK_BW,
620 FIELD_PREP(DP_TX_LINK_BW, bw));
621
622 if (dp->ssc) {
623 regmap_update_bits(hdptx->regmap, 0x01d0,
624 OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN,
625 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) |
626 FIELD_PREP(ROPLL_SSC_EN, 0x1));
627 regmap_write(hdptx->regmap, 0x01d4,
628 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0xc));
629 regmap_update_bits(hdptx->regmap, 0x01d8,
630 ANA_ROPLL_SSC_FM_FREQ,
631 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0x1f));
632 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN,
633 FIELD_PREP(SSC_EN, 0x2));
634 } else {
635 regmap_update_bits(hdptx->regmap, 0x01d0,
636 OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN,
637 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) |
638 FIELD_PREP(ROPLL_SSC_EN, 0x0));
639 regmap_write(hdptx->regmap, 0x01d4,
640 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0x20));
641 regmap_update_bits(hdptx->regmap, 0x01d8,
642 ANA_ROPLL_SSC_FM_FREQ,
643 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0xc));
644 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN,
645 FIELD_PREP(SSC_EN, 0x0));
646 }
647
648 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
649 FIELD_PREP(PLL_EN, 0x1));
650 udelay(20);
651 reset_control_deassert(hdptx->cmn_reset);
652 udelay(20);
653
654 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
655 status, FIELD_GET(PLL_LOCK_DONE, status),
656 50, 1000);
657 if (ret) {
658 dev_err(hdptx->dev, "timeout waiting for pll_lock_done\n");
659 return ret;
660 }
661
662 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN,
663 FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0)));
664
665 reset_control_deassert(hdptx->lane_reset);
666 udelay(20);
667
668 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
669 status, FIELD_PREP(PHY_RDY, status),
670 50, 1000);
671 if (ret) {
672 dev_err(hdptx->dev, "timeout waiting for phy_rdy\n");
673 return ret;
674 }
675
676 return 0;
677 }
678
rockchip_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opts)679 static int rockchip_hdptx_phy_configure(struct phy *phy,
680 union phy_configure_opts *opts)
681 {
682 struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
683 enum phy_mode mode = phy_get_mode(phy);
684 int ret;
685
686 if (mode != PHY_MODE_DP)
687 return -EINVAL;
688
689 ret = rockchip_hdptx_phy_verify_config(hdptx, &opts->dp);
690 if (ret) {
691 dev_err(hdptx->dev, "invalid params for phy configure\n");
692 return ret;
693 }
694
695 if (opts->dp.set_rate) {
696 ret = rockchip_hdptx_phy_set_rate(hdptx, &opts->dp);
697 if (ret) {
698 dev_err(hdptx->dev, "failed to set rate: %d\n", ret);
699 return ret;
700 }
701 }
702
703 if (opts->dp.set_voltages) {
704 ret = rockchip_hdptx_phy_set_voltages(hdptx, &opts->dp);
705 if (ret) {
706 dev_err(hdptx->dev, "failed to set voltages: %d\n",
707 ret);
708 return ret;
709 }
710 }
711
712 return 0;
713 }
714
rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy *hdptx)715 static void rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy *hdptx)
716 {
717 regmap_update_bits(hdptx->regmap, 0x0020, OVRD_LCPLL_EN | LCPLL_EN,
718 FIELD_PREP(OVRD_LCPLL_EN, 0x1) |
719 FIELD_PREP(LCPLL_EN, 0x0));
720 regmap_update_bits(hdptx->regmap, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN,
721 FIELD_PREP(OVRD_ROPLL_EN, 0x1) |
722 FIELD_PREP(ROPLL_EN, 0x1));
723 regmap_update_bits(hdptx->regmap, 0x0138, ANA_ROPLL_PI_EN,
724 FIELD_PREP(ANA_ROPLL_PI_EN, 0x1));
725
726 regmap_write(hdptx->regmap, 0x0144, FIELD_PREP(ROPLL_PMS_MDIV, 0x87));
727 regmap_write(hdptx->regmap, 0x0148, FIELD_PREP(ROPLL_PMS_MDIV, 0x71));
728 regmap_write(hdptx->regmap, 0x014c, FIELD_PREP(ROPLL_PMS_MDIV, 0x71));
729
730 regmap_write(hdptx->regmap, 0x0154,
731 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x87));
732 regmap_write(hdptx->regmap, 0x0158,
733 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71));
734 regmap_write(hdptx->regmap, 0x015c,
735 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71));
736
737 regmap_write(hdptx->regmap, 0x0164,
738 FIELD_PREP(ANA_ROPLL_PMS_PDIV, 0x1) |
739 FIELD_PREP(ANA_ROPLL_PMS_REFDIV, 0x1));
740
741 regmap_write(hdptx->regmap, 0x0168,
742 FIELD_PREP(ROPLL_PMS_SDIV_RBR, 0x3) |
743 FIELD_PREP(ROPLL_PMS_SDIV_HBR, 0x1));
744 regmap_update_bits(hdptx->regmap, 0x016c, ROPLL_PMS_SDIV_HBR2,
745 FIELD_PREP(ROPLL_PMS_SDIV_HBR2, 0x0));
746
747 regmap_update_bits(hdptx->regmap, 0x0178, ANA_ROPLL_SDM_EN,
748 FIELD_PREP(ANA_ROPLL_SDM_EN, 0x1));
749 regmap_update_bits(hdptx->regmap, 0x0178,
750 OVRD_ROPLL_SDM_RSTN | ROPLL_SDM_RSTN,
751 FIELD_PREP(OVRD_ROPLL_SDM_RSTN, 0x1) |
752 FIELD_PREP(ROPLL_SDM_RSTN, 0x1));
753 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_RBR,
754 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_RBR, 0x1));
755 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR,
756 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR, 0x1));
757 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR2,
758 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR2, 0x1));
759 regmap_update_bits(hdptx->regmap, 0x017c,
760 OVRD_ROPLL_SDC_RSTN | ROPLL_SDC_RSTN,
761 FIELD_PREP(OVRD_ROPLL_SDC_RSTN, 0x1) |
762 FIELD_PREP(ROPLL_SDC_RSTN, 0x1));
763
764 regmap_write(hdptx->regmap, 0x0180,
765 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x21));
766 regmap_write(hdptx->regmap, 0x0184,
767 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27));
768 regmap_write(hdptx->regmap, 0x0188,
769 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27));
770
771 regmap_update_bits(hdptx->regmap, 0x0190,
772 ROPLL_SDM_NUMERATOR_SIGN_RBR |
773 ROPLL_SDM_NUMERATOR_SIGN_HBR |
774 ROPLL_SDM_NUMERATOR_SIGN_HBR2,
775 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_RBR, 0x0) |
776 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR, 0x1) |
777 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR2, 0x1));
778
779 regmap_write(hdptx->regmap, 0x0194,
780 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0x0));
781 regmap_write(hdptx->regmap, 0x0198,
782 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd));
783 regmap_write(hdptx->regmap, 0x019c,
784 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd));
785
786 regmap_update_bits(hdptx->regmap, 0x01a4, ROPLL_SDC_N_RBR,
787 FIELD_PREP(ROPLL_SDC_N_RBR, 0x2));
788 regmap_update_bits(hdptx->regmap, 0x01a8,
789 ROPLL_SDC_N_HBR | ROPLL_SDC_N_HBR2,
790 FIELD_PREP(ROPLL_SDC_N_HBR, 0x1) |
791 FIELD_PREP(ROPLL_SDC_N_HBR2, 0x1));
792
793 regmap_write(hdptx->regmap, 0x01b0,
794 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x3));
795 regmap_write(hdptx->regmap, 0x01b4,
796 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7));
797 regmap_write(hdptx->regmap, 0x01b8,
798 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7));
799
800 regmap_write(hdptx->regmap, 0x01c0,
801 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x8));
802 regmap_write(hdptx->regmap, 0x01c4,
803 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18));
804 regmap_write(hdptx->regmap, 0x01c8,
805 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18));
806
807 regmap_update_bits(hdptx->regmap, 0x01d0,
808 OVRD_ROPLL_SDC_NDIV_RSTN | ROPLL_SDC_NDIV_RSTN,
809 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN, 0x1) |
810 FIELD_PREP(ROPLL_SDC_NDIV_RSTN, 0x1));
811 regmap_update_bits(hdptx->regmap, 0x01dc, ANA_ROPLL_SSC_CLK_DIV_SEL,
812 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL, 0x1));
813
814 regmap_update_bits(hdptx->regmap, 0x0118,
815 ROPLL_ANA_CPP_CTRL_COARSE | ROPLL_ANA_CPP_CTRL_FINE,
816 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE, 0xe) |
817 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE, 0xe));
818 regmap_update_bits(hdptx->regmap, 0x011c,
819 ROPLL_ANA_LPF_C_SEL_COARSE |
820 ROPLL_ANA_LPF_C_SEL_FINE,
821 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE, 0x4) |
822 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE, 0x4));
823
824 regmap_update_bits(hdptx->regmap, 0x0204, ANA_PLL_CD_TX_SER_RATE_SEL,
825 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL, 0x0));
826
827 regmap_update_bits(hdptx->regmap, 0x025c, DIG_CLK_SEL,
828 FIELD_PREP(DIG_CLK_SEL, 0x1));
829 regmap_update_bits(hdptx->regmap, 0x021c, ANA_PLL_TX_HS_CLK_EN,
830 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN, 0x1));
831 regmap_update_bits(hdptx->regmap, 0x0204,
832 ANA_PLL_CD_HSCLK_EAST_EN | ANA_PLL_CD_HSCLK_WEST_EN,
833 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN, 0x1) |
834 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN, 0x0));
835 regmap_update_bits(hdptx->regmap, 0x0264, CMN_ROPLL_ALONE_MODE,
836 FIELD_PREP(CMN_ROPLL_ALONE_MODE, 0x1));
837 regmap_update_bits(hdptx->regmap, 0x0208, ANA_PLL_CD_VREG_GAIN_CTRL,
838 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL, 0x4));
839 regmap_update_bits(hdptx->regmap, 0x00f0, ANA_LCPLL_RESERVED7,
840 FIELD_PREP(ANA_LCPLL_RESERVED7, 0x1));
841 regmap_update_bits(hdptx->regmap, 0x020c, ANA_PLL_CD_VREG_ICTRL,
842 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL, 0x1));
843 regmap_update_bits(hdptx->regmap, 0x0214, ANA_PLL_SYNC_LOSS_DET_MODE,
844 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE, 0x3));
845 regmap_update_bits(hdptx->regmap, 0x0210, PLL_LCRO_CLK_SEL,
846 FIELD_PREP(PLL_LCRO_CLK_SEL, 0x1));
847 regmap_update_bits(hdptx->regmap, 0x0268, HS_SPEED_SEL,
848 FIELD_PREP(HS_SPEED_SEL, 0x1));
849 regmap_update_bits(hdptx->regmap, 0x026c, LS_SPEED_SEL,
850 FIELD_PREP(LS_SPEED_SEL, 0x1));
851 }
852
rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy *hdptx)853 static int rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy *hdptx)
854 {
855 u32 status;
856 int ret;
857
858 regmap_update_bits(hdptx->regmap, 0x0414, ANA_SB_TX_HLVL_PROG,
859 FIELD_PREP(ANA_SB_TX_HLVL_PROG, 0x7));
860 regmap_update_bits(hdptx->regmap, 0x0418, ANA_SB_TX_LLVL_PROG,
861 FIELD_PREP(ANA_SB_TX_LLVL_PROG, 0x7));
862
863 regmap_update_bits(hdptx->regmap, 0x044c,
864 SB_RX_RCAL_OPT_CODE | SB_RX_RTERM_CTRL,
865 FIELD_PREP(SB_RX_RCAL_OPT_CODE, 0x1) |
866 FIELD_PREP(SB_RX_RTERM_CTRL, 0x3));
867 regmap_update_bits(hdptx->regmap, 0x0450,
868 SB_TG_SB_EN_DELAY_TIME | SB_TG_RXTERN_EN_DELAY_TIME,
869 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME, 0x2) |
870 FIELD_PREP(SB_TG_RXTERN_EN_DELAY_TIME, 0x2));
871 regmap_update_bits(hdptx->regmap, 0x0454,
872 SB_READY_DELAY_TIME | SB_TG_OSC_EN_DELAY_TIME,
873 FIELD_PREP(SB_READY_DELAY_TIME, 0x2) |
874 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME, 0x2));
875 regmap_update_bits(hdptx->regmap, 0x0458,
876 SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME,
877 FIELD_PREP(SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 0x2));
878 regmap_update_bits(hdptx->regmap, 0x045c,
879 SB_TG_PLL_CD_VREG_FAST_PULSE_TIME,
880 FIELD_PREP(SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 0x4));
881 regmap_update_bits(hdptx->regmap, 0x0460,
882 SB_TG_EARC_DMRX_RECVRD_CLK_CNT,
883 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 0xa));
884 regmap_update_bits(hdptx->regmap, 0x0468, SB_TG_CNT_RUN_NO_7_0,
885 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0, 0x3));
886 regmap_update_bits(hdptx->regmap, 0x046c,
887 SB_EARC_SIG_DET_BYPASS | SB_AFC_TOL,
888 FIELD_PREP(SB_EARC_SIG_DET_BYPASS, 0x1) |
889 FIELD_PREP(SB_AFC_TOL, 0x3));
890 regmap_update_bits(hdptx->regmap, 0x0470, SB_AFC_STB_NUM,
891 FIELD_PREP(SB_AFC_STB_NUM, 0x4));
892 regmap_update_bits(hdptx->regmap, 0x0474, SB_TG_OSC_CNT_MIN,
893 FIELD_PREP(SB_TG_OSC_CNT_MIN, 0x67));
894 regmap_update_bits(hdptx->regmap, 0x0478, SB_TG_OSC_CNT_MAX,
895 FIELD_PREP(SB_TG_OSC_CNT_MAX, 0x6a));
896 regmap_update_bits(hdptx->regmap, 0x047c, SB_PWM_AFC_CTRL,
897 FIELD_PREP(SB_PWM_AFC_CTRL, 0x5));
898 regmap_update_bits(hdptx->regmap, 0x0434, ANA_SB_DMRX_LPBK_DATA,
899 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA, 0x1));
900 regmap_update_bits(hdptx->regmap, 0x0440,
901 ANA_SB_VREG_OUT_SEL | ANA_SB_VREG_REF_SEL,
902 FIELD_PREP(ANA_SB_VREG_OUT_SEL, 0x1) |
903 FIELD_PREP(ANA_SB_VREG_REF_SEL, 0x1));
904 regmap_update_bits(hdptx->regmap, 0x043c, ANA_SB_VREG_GAIN_CTRL,
905 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL, 0x0));
906 regmap_update_bits(hdptx->regmap, 0x0408, ANA_SB_RXTERM_OFFSP,
907 FIELD_PREP(ANA_SB_RXTERM_OFFSP, 0x3));
908 regmap_update_bits(hdptx->regmap, 0x040c, ANA_SB_RXTERM_OFFSN,
909 FIELD_PREP(ANA_SB_RXTERM_OFFSN, 0x3));
910 regmap_update_bits(hdptx->regmap, 0x047c, SB_RCAL_RSTN,
911 FIELD_PREP(SB_RCAL_RSTN, 0x1));
912 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN,
913 FIELD_PREP(SB_AUX_EN, 0x1));
914 regmap_update_bits(hdptx->regmap, 0x0480, SB_AUX_EN_IN,
915 FIELD_PREP(SB_AUX_EN_IN, 0x1));
916 regmap_update_bits(hdptx->regmap, 0x040c, OVRD_SB_RX_RESCAL_DONE,
917 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE, 0x1));
918 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_EN,
919 FIELD_PREP(OVRD_SB_EN, 0x1));
920 regmap_update_bits(hdptx->regmap, 0x0408, OVRD_SB_RXTERM_EN,
921 FIELD_PREP(OVRD_SB_RXTERM_EN, 0x1));
922 regmap_update_bits(hdptx->regmap, 0x043c, OVRD_SB_VREG_EN,
923 FIELD_PREP(OVRD_SB_VREG_EN, 0x1));
924 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_AUX_EN,
925 FIELD_PREP(OVRD_SB_AUX_EN, 0x1));
926
927 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN,
928 FIELD_PREP(BGR_EN, 0x1));
929 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN,
930 FIELD_PREP(BIAS_EN, 0x1));
931 udelay(20);
932
933 reset_control_deassert(hdptx->init_reset);
934 udelay(20);
935 reset_control_deassert(hdptx->cmn_reset);
936 udelay(20);
937
938 regmap_update_bits(hdptx->regmap, 0x040c, SB_RX_RESCAL_DONE,
939 FIELD_PREP(SB_RX_RESCAL_DONE, 0x1));
940 udelay(100);
941 regmap_update_bits(hdptx->regmap, 0x0410, SB_EN,
942 FIELD_PREP(SB_EN, 0x1));
943 udelay(100);
944 regmap_update_bits(hdptx->regmap, 0x0408, SB_RXRERM_EN,
945 FIELD_PREP(SB_RXRERM_EN, 0x1));
946 udelay(20);
947 regmap_update_bits(hdptx->regmap, 0x043c, SB_VREG_EN,
948 FIELD_PREP(SB_VREG_EN, 0x1));
949 udelay(20);
950 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN,
951 FIELD_PREP(SB_AUX_EN, 0x1));
952 udelay(100);
953
954 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
955 status, FIELD_GET(SB_RDY, status),
956 50, 1000);
957 if (ret) {
958 dev_err(hdptx->dev, "timeout waiting for sb_rdy\n");
959 return ret;
960 }
961
962 return 0;
963 }
964
rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy *hdptx)965 static void rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy *hdptx)
966 {
967 u32 lane;
968
969 reset_control_assert(hdptx->lane_reset);
970 reset_control_assert(hdptx->cmn_reset);
971 reset_control_assert(hdptx->init_reset);
972
973 reset_control_assert(hdptx->apb_reset);
974 udelay(10);
975 reset_control_deassert(hdptx->apb_reset);
976
977 for (lane = 0; lane < 4; lane++)
978 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c04),
979 OVRD_LN_TX_DRV_EI_EN | LN_TX_DRV_EI_EN,
980 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN, 1) |
981 FIELD_PREP(LN_TX_DRV_EI_EN, 0));
982
983 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
984 FIELD_PREP(PLL_EN, 0));
985 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN,
986 FIELD_PREP(BIAS_EN, 0));
987 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN,
988 FIELD_PREP(BGR_EN, 0));
989 }
990
rockchip_hdptx_phy_enabled(struct rockchip_hdptx_phy *hdptx)991 static bool rockchip_hdptx_phy_enabled(struct rockchip_hdptx_phy *hdptx)
992 {
993 u32 status;
994
995 regmap_read(hdptx->grf, HDPTXPHY_GRF_STATUS0, &status);
996
997 return FIELD_GET(SB_RDY, status);
998 }
999
rockchip_hdptx_phy_power_on(struct phy *phy)1000 static int rockchip_hdptx_phy_power_on(struct phy *phy)
1001 {
1002 struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
1003 enum phy_mode mode = phy_get_mode(phy);
1004 u32 lane;
1005 int ret;
1006
1007 ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks);
1008 if (ret)
1009 return ret;
1010
1011 if (rockchip_hdptx_phy_enabled(hdptx))
1012 return 0;
1013
1014 rockchip_hdptx_phy_reset(hdptx);
1015
1016 for (lane = 0; lane < 4; lane++) {
1017 u32 invert = hdptx->lane_polarity_invert[lane];
1018
1019 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c78),
1020 LN_POLARITY_INV,
1021 FIELD_PREP(LN_POLARITY_INV, invert));
1022 }
1023
1024 if (mode == PHY_MODE_DP) {
1025 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0,
1026 HDPTX_MODE_SEL,
1027 FIELD_PREP(HDPTX_MODE_SEL, 0x1));
1028
1029 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL,
1030 FIELD_PREP(PROTOCOL_SEL, 0x0));
1031 regmap_update_bits(hdptx->regmap, 0x0818, DATA_BUS_WIDTH,
1032 FIELD_PREP(DATA_BUS_WIDTH, 0x1));
1033 regmap_update_bits(hdptx->regmap, 0x0818, BUS_WIDTH_SEL,
1034 FIELD_PREP(BUS_WIDTH_SEL, 0x0));
1035
1036 rockchip_hdptx_phy_dp_pll_init(hdptx);
1037 rockchip_hdptx_phy_dp_aux_init(hdptx);
1038 } else {
1039 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0,
1040 HDPTX_MODE_SEL,
1041 FIELD_PREP(HDPTX_MODE_SEL, 0x0));
1042
1043 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL,
1044 FIELD_PREP(PROTOCOL_SEL, 0x1));
1045 }
1046
1047 return 0;
1048 }
1049
rockchip_hdptx_phy_power_off(struct phy *phy)1050 static int rockchip_hdptx_phy_power_off(struct phy *phy)
1051 {
1052 struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
1053
1054 rockchip_hdptx_phy_reset(hdptx);
1055
1056 clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks);
1057
1058 return 0;
1059 }
1060
1061 static const struct phy_ops rockchip_hdptx_phy_ops = {
1062 .set_mode = rockchip_hdptx_phy_set_mode,
1063 .configure = rockchip_hdptx_phy_configure,
1064 .power_on = rockchip_hdptx_phy_power_on,
1065 .power_off = rockchip_hdptx_phy_power_off,
1066 .owner = THIS_MODULE,
1067 };
1068
rockchip_hdptx_phy_is_accissible_reg(struct device *dev, unsigned int reg)1069 static bool rockchip_hdptx_phy_is_accissible_reg(struct device *dev,
1070 unsigned int reg)
1071 {
1072 switch (reg) {
1073 case 0x0000 ... 0x029c: /* CMN Register */
1074 case 0x0400 ... 0x04a4: /* Sideband Register */
1075 case 0x0800 ... 0x08a4: /* Lane Top Register */
1076 case 0x0c00 ... 0x0cb4: /* Lane 0 Register */
1077 case 0x1000 ... 0x10b4: /* Lane 1 Register */
1078 case 0x1400 ... 0x14b4: /* Lane 2 Register */
1079 case 0x1800 ... 0x18b4: /* Lane 3 Register */
1080 return true;
1081 default:
1082 return false;
1083 }
1084 }
1085
1086 static const struct regmap_config rockchip_hdptx_phy_regmap_config = {
1087 .reg_bits = 32,
1088 .reg_stride = 4,
1089 .val_bits = 32,
1090 .fast_io = true,
1091 .max_register = 0x18b4,
1092 .readable_reg = rockchip_hdptx_phy_is_accissible_reg,
1093 .writeable_reg = rockchip_hdptx_phy_is_accissible_reg,
1094 };
1095
rockchip_hdptx_phy_probe(struct platform_device *pdev)1096 static int rockchip_hdptx_phy_probe(struct platform_device *pdev)
1097 {
1098 struct device *dev = &pdev->dev;
1099 struct rockchip_hdptx_phy *hdptx;
1100 struct phy *phy;
1101 struct phy_provider *phy_provider;
1102 void __iomem *regs;
1103 int ret;
1104
1105 hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL);
1106 if (!hdptx)
1107 return -ENOMEM;
1108
1109 hdptx->dev = dev;
1110 platform_set_drvdata(pdev, hdptx);
1111
1112 regs = devm_platform_ioremap_resource(pdev, 0);
1113 if (IS_ERR(regs))
1114 return PTR_ERR(regs);
1115
1116 hdptx->regmap = devm_regmap_init_mmio(dev, regs,
1117 &rockchip_hdptx_phy_regmap_config);
1118 if (IS_ERR(hdptx->regmap))
1119 return dev_err_probe(dev, PTR_ERR(hdptx->regmap),
1120 "failed to create regmap\n");
1121
1122 ret = devm_clk_bulk_get_all(dev, &hdptx->clks);
1123 if (ret < 1)
1124 return dev_err_probe(dev, ret, "failed to get clocks\n");
1125
1126 hdptx->nr_clks = ret;
1127
1128 hdptx->apb_reset = devm_reset_control_get(dev, "apb");
1129 if (IS_ERR(hdptx->apb_reset))
1130 return dev_err_probe(dev, PTR_ERR(hdptx->apb_reset),
1131 "failed to get apb reset\n");
1132
1133 hdptx->init_reset = devm_reset_control_get(dev, "init");
1134 if (IS_ERR(hdptx->init_reset))
1135 return dev_err_probe(dev, PTR_ERR(hdptx->init_reset),
1136 "failed to get init reset\n");
1137
1138 hdptx->cmn_reset = devm_reset_control_get(dev, "cmn");
1139 if (IS_ERR(hdptx->cmn_reset))
1140 return dev_err_probe(dev, PTR_ERR(hdptx->cmn_reset),
1141 "failed to get cmn reset\n");
1142
1143 hdptx->lane_reset = devm_reset_control_get(dev, "lane");
1144 if (IS_ERR(hdptx->lane_reset))
1145 return dev_err_probe(dev, PTR_ERR(hdptx->lane_reset),
1146 "failed to get lane reset\n");
1147
1148 hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1149 "rockchip,grf");
1150 if (IS_ERR(hdptx->grf))
1151 return dev_err_probe(dev, PTR_ERR(hdptx->grf),
1152 "failed to get grf regmap\n");
1153
1154 device_property_read_u32_array(dev, "lane-polarity-invert",
1155 hdptx->lane_polarity_invert, 4);
1156
1157 phy = devm_phy_create(dev, NULL, &rockchip_hdptx_phy_ops);
1158 if (IS_ERR(phy)) {
1159 ret = PTR_ERR(phy);
1160 dev_err(dev, "failed to create PHY: %d\n", ret);
1161 return ret;
1162 }
1163
1164 phy_set_drvdata(phy, hdptx);
1165
1166 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1167
1168 return PTR_ERR_OR_ZERO(phy_provider);
1169 }
1170
1171 static const struct of_device_id rockchip_hdptx_phy_of_match[] = {
1172 { .compatible = "rockchip,rk3588-hdptx-phy", },
1173 {}
1174 };
1175 MODULE_DEVICE_TABLE(of, rockchip_hdptx_phy_of_match);
1176
1177 static struct platform_driver rockchip_hdptx_phy_driver = {
1178 .probe = rockchip_hdptx_phy_probe,
1179 .driver = {
1180 .name = "rockchip-hdptx-phy",
1181 .of_match_table = rockchip_hdptx_phy_of_match,
1182 }
1183 };
1184 module_platform_driver(rockchip_hdptx_phy_driver);
1185
1186 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
1187 MODULE_DESCRIPTION("Rockchip HDMI/DP Combo PHY with Samsung IP block");
1188 MODULE_LICENSE("GPL v2");
1189