1 /*
2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #include "mipi_rx_hi2121.h"
17 #include "hdf_log.h"
18 #include "mipi_rx_reg.h"
19 #include "osal_io.h"
20 #include "osal_irq.h"
21 #include "osal_time.h"
22
23 #ifdef __cplusplus
24 #if __cplusplus
25 extern "C" {
26 #endif
27 #endif /* End of #ifdef __cplusplus */
28
29 static unsigned long g_mipiRxCoreResetAddr;
30
31 typedef struct {
32 unsigned int phy_rg_en_2121;
33 unsigned int phy_rg_clk0_en;
34 unsigned int phy_rg_clk1_en;
35 unsigned int phy_rg_lp0_mode_en;
36 unsigned int phy_rg_lp1_mode_en;
37 } PhyModeLinkTag;
38
39 typedef enum {
40 MIPI_ESC_D0 = 0x1 << 0,
41 MIPI_ESC_D1 = 0x1 << 1,
42 MIPI_ESC_D2 = 0x1 << 2,
43 MIPI_ESC_D3 = 0x1 << 3,
44 MIPI_ESC_CLK0 = 0x1 << 4,
45 MIPI_ESC_CLK1 = 0x1 << 5,
46
47 MIPI_TIMEOUT_D0 = 0x1 << 8,
48 MIPI_TIMEOUT_D1 = 0x1 << 9,
49 MIPI_TIMEOUT_D2 = 0x1 << 10,
50 MIPI_TIMEOUT_D3 = 0x1 << 11,
51 MIPI_TIMEOUT_CLK0 = 0x1 << 12,
52 MIPI_TIMEOUT_CLK1 = 0x1 << 13,
53 } PhyErrIntState;
54
55 typedef enum {
56 MIPI_VC0_PKT_DATA_CRC = 0x1 << 0, /* VC0'S data CRC error */
57 MIPI_VC1_PKT_DATA_CRC = 0x1 << 1,
58 MIPI_VC2_PKT_DATA_CRC = 0x1 << 2,
59 MIPI_VC3_PKT_DATA_CRC = 0x1 << 3,
60
61 MIPI_PKT_HEADER_ERR = 0x1 << 16, /* Header has two error at least ,and ECC error correction is invalid */
62 } MipiPktIntState;
63
64 typedef enum {
65 MIPI_VC0_PKT_INVALID_DT = 0x1 << 0, /* do not support VC0'S data type */
66 MIPI_VC1_PKT_INVALID_DT = 0x1 << 1, /* do not support VC1'S data type */
67 MIPI_VC2_PKT_INVALID_DT = 0x1 << 2, /* do not support VC2'S data type */
68 MIPI_VC3_PKT_INVALID_DT = 0x1 << 3, /* do not support VC3'S data type */
69
70 MIPI_VC0_PKT_HEADER_ECC = 0x1 << 16, /* VC0'S header has errors,and ECC error correction is ok */
71 MIPI_VC1_PKT_HEADER_ECC = 0x1 << 17,
72 MIPI_VC2_PKT_HEADER_ECC = 0x1 << 18,
73 MIPI_VC3_PKT_HEADER_ECC = 0x1 << 19,
74 } MipiPkt2IntState;
75
76 typedef enum {
77 MIPI_VC0_NO_MATCH = 0x1 << 0, /* VC0,frame's start and frame's end do not match */
78 MIPI_VC1_NO_MATCH = 0x1 << 1, /* VC1,frame's start and frame's end do not match */
79 MIPI_VC2_NO_MATCH = 0x1 << 2, /* VC2,frame's start and frame's end do not match */
80 MIPI_VC3_NO_MATCH = 0x1 << 3, /* VC3,frame's start and frame's end do not match */
81
82 MIPI_VC0_ORDER_ERR = 0x1 << 8, /* VC0'S frame order error */
83 MIPI_VC1_ORDER_ERR = 0x1 << 9, /* VC1'S frame order error */
84 MIPI_VC2_ORDER_ERR = 0x1 << 10, /* VC2'S frame order error */
85 MIPI_VC3_ORDER_ERR = 0x1 << 11, /* VC3'S frame order error */
86
87 MIPI_VC0_FRAME_CRC = 0x1 << 16, /* in the last frame, VC0'S data has a CRC ERROR at least */
88 MIPI_VC1_FRAME_CRC = 0x1 << 17, /* in the last frame, VC1'S data has a CRC ERROR at least */
89 MIPI_VC2_FRAME_CRC = 0x1 << 18, /* in the last frame, VC2'S data has a CRC ERROR at least */
90 MIPI_VC3_FRAME_CRC = 0x1 << 19, /* in the last frame, VC3'S data has a CRC ERROR at least */
91 } MipiFrameIntState;
92
93 typedef enum {
94 CMD_FIFO_WRITE_ERR = 0x1 << 0, /* MIPI_CTRL write command FIFO error */
95 DATA_FIFO_WRITE_ERR = 0x1 << 1,
96 CMD_FIFO_READ_ERR = 0x1 << 16,
97 DATA_FIFO_READ_ERR = 0x1 << 17,
98 } MipiCtrlIntState;
99
100 typedef enum {
101 LINK0_WRITE_ERR = 0x1 << 16,
102 LINK0_READ_ERR = 0x1 << 20,
103 LVDS_STAT_ERR = 0x1 << 24,
104 LVDS_POP_ERR = 0x1 << 25,
105 CMD_WR_ERR = 0x1 << 26,
106 CMD_RD_ERR = 0x1 << 27,
107 } LvdsIntState;
108
109 typedef enum {
110 ALIGN_FIFO_FULL_ERR = 0x1 << 0,
111 ALIGN_LANE0_ERR = 0x1 << 1,
112 ALIGN_LANE1_ERR = 0x1 << 2,
113 ALIGN_LANE2_ERR = 0x1 << 3,
114 ALIGN_LANE3_ERR = 0x1 << 4,
115 } AlignIntState;
116
117 enum UserDefData {
118 DEF0_DATA = 0,
119 DEF1_DATA,
120 DEF2_DATA,
121 DEF3_DATA
122 };
123
124 #define HDF_LOG_TAG mipi_rx_hi2121
125 /* macro definition */
126 #define MIPI_RX_REGS_ADDR 0x113A0000
127 #define MIPI_RX_REGS_SIZE 0x10000
128
129 #define SNS_CRG_ADDR 0x120100F0
130 #define MIPI_RX_CRG_ADDR 0x120100F8
131
132 #define MIPI_RX_WORK_MODE_ADDR 0x12030018
133
134 #define MIPI_RX_IRQ 89
135
136 static unsigned int g_regMapFlag = 0;
137
138 #define SKEW_LINK 0x0
139 #define MIPI_FSMO_VALUE 0x000d1d0c
140 #define DOL_ID_CODE_OFFSET (1 << 4)
141
142 /* global variables definition */
143 MipiRxRegsTypeTag *g_mipiRxRegsVa = NULL;
144
145 unsigned int g_mipiRxIrqNum = MIPI_RX_IRQ;
146
147 static const PhyModeLinkTag g_phyMode[][MIPI_RX_MAX_PHY_NUM] = {
148 {{ 0, 1, 1, 1, 1 }},
149 {{ 1, 1, 1, 1, 1 }},
150 };
151
152 PhyErrIntCnt g_phyErrIntCnt[MIPI_RX_MAX_PHY_NUM];
153 MipiErrIntCnt g_mipiErrIntCnt[MIPI_RX_MAX_DEV_NUM];
154 LvdsErrIntCnt g_lvdsErrIntCnt[MIPI_RX_MAX_DEV_NUM];
155 AlignErrIntCnt g_alignErrIntCnt[MIPI_RX_MAX_DEV_NUM];
156
MipiRxHalGetPhyErrIntCnt(unsigned int phyId)157 PhyErrIntCnt *MipiRxHalGetPhyErrIntCnt(unsigned int phyId)
158 {
159 return &g_phyErrIntCnt[phyId];
160 }
161
MipiRxHalGetMipiErrInt(unsigned int phyId)162 MipiErrIntCnt *MipiRxHalGetMipiErrInt(unsigned int phyId)
163 {
164 return &g_mipiErrIntCnt[phyId];
165 }
166
MipiRxHalGetLvdsErrIntCnt(unsigned int phyId)167 LvdsErrIntCnt *MipiRxHalGetLvdsErrIntCnt(unsigned int phyId)
168 {
169 return &g_lvdsErrIntCnt[phyId];
170 }
171
MipiRxHalGetAlignErrIntCnt(unsigned int phyId)172 AlignErrIntCnt *MipiRxHalGetAlignErrIntCnt(unsigned int phyId)
173 {
174 return &g_alignErrIntCnt[phyId];
175 }
176
177 /* function definition */
SetBit(unsigned long value, unsigned long offset, unsigned long *addr)178 static void SetBit(unsigned long value, unsigned long offset, unsigned long *addr)
179 {
180 unsigned long t, mask;
181
182 mask = 1 << offset;
183 t = OSAL_READL(addr);
184 t &= ~mask;
185 t |= (value << offset) & mask;
186 OSAL_WRITEL(t, addr);
187 }
188
WriteReg32(unsigned long *addr, unsigned int value, unsigned int mask)189 static void WriteReg32(unsigned long *addr, unsigned int value, unsigned int mask)
190 {
191 unsigned int t;
192
193 t = OSAL_READL(addr);
194 t &= ~mask;
195 t |= value & mask;
196
197 OSAL_WRITEL(t, addr);
198 }
199
GetMipiRxPhyRegs(unsigned int phyId)200 static MipiRxPhyCfgTag *GetMipiRxPhyRegs(unsigned int phyId)
201 {
202 return &g_mipiRxRegsVa->mipiRxPhyCfg[phyId];
203 }
204
GetMipiRxSysRegs(void)205 static MipiRxSysRegsTag *GetMipiRxSysRegs(void)
206 {
207 return &g_mipiRxRegsVa->mipiRxSysRegs;
208 }
209
GetMipiCtrlRegs(uint8_t devno)210 static MipiCtrlRegsTag *GetMipiCtrlRegs(uint8_t devno)
211 {
212 return &g_mipiRxRegsVa->mipiRxCtrlRegs[devno].mipiCtrlRegs;
213 }
214
GetLvdsCtrlRegs(uint8_t devno)215 static LvdsCtrlRegsTag *GetLvdsCtrlRegs(uint8_t devno)
216 {
217 return &g_mipiRxRegsVa->mipiRxCtrlRegs[devno].lvdsCtrlRegs;
218 }
219
MipiRxSetCilIntMask(unsigned int phyId, unsigned int mask)220 void MipiRxSetCilIntMask(unsigned int phyId, unsigned int mask)
221 {
222 U_MIPI_INT_MSK mipiIntMsk;
223 volatile MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
224 volatile MipiRxSysRegsTag *mipiRxSysRegs = GetMipiRxSysRegs();
225
226 mipiIntMsk.u32 = mipiRxSysRegs->MIPI_INT_MSK.u32;
227
228 if (phyId == 0) {
229 mipiIntMsk.bits.int_phycil0_mask = 0x0;
230 }
231
232 mipiRxSysRegs->MIPI_INT_MSK.u32 = mipiIntMsk.u32;
233
234 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
235 mipiRxPhyCfg->MIPI_CIL_INT_MSK_LINK.u32 = mask;
236 }
237
MipiRxSetPhySkewLink(unsigned int phyId, unsigned int value)238 static void MipiRxSetPhySkewLink(unsigned int phyId, unsigned int value)
239 {
240 volatile U_PHY_SKEW_LINK phySkewLink;
241 volatile MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
242
243 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
244 phySkewLink.u32 = value;
245 mipiRxPhyCfg->PHY_SKEW_LINK.u32 = phySkewLink.u32;
246 }
247
MipiRxSetPhyFsmoLink(unsigned int phyId, unsigned int value)248 void MipiRxSetPhyFsmoLink(unsigned int phyId, unsigned int value)
249 {
250 volatile MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
251
252 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
253 mipiRxPhyCfg->CIL_FSM0_LINK.u32 = value;
254 }
255
MipiRxSetPhyRg2121En(unsigned int phyId, int enable)256 void MipiRxSetPhyRg2121En(unsigned int phyId, int enable)
257 {
258 volatile U_PHY_MODE_LINK phyModeLink;
259 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
260
261 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
262 phyModeLink.u32 = mipiRxPhyCfg->PHY_MODE_LINK.u32;
263 phyModeLink.bits.phy0_rg_en_2l2l = enable;
264 mipiRxPhyCfg->PHY_MODE_LINK.u32 = phyModeLink.u32;
265 }
266
MipiRxSetPhyRgClk0En(unsigned int phyId, int enable)267 void MipiRxSetPhyRgClk0En(unsigned int phyId, int enable)
268 {
269 volatile U_PHY_MODE_LINK phyModeLink;
270 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
271
272 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
273 phyModeLink.u32 = mipiRxPhyCfg->PHY_MODE_LINK.u32;
274 phyModeLink.bits.phy0_rg_faclk0_en = enable;
275 mipiRxPhyCfg->PHY_MODE_LINK.u32 = phyModeLink.u32;
276 }
277
MipiRxSetPhyRgClk1En(unsigned int phyId, int enable)278 void MipiRxSetPhyRgClk1En(unsigned int phyId, int enable)
279 {
280 volatile U_PHY_MODE_LINK phyModeLink;
281 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
282
283 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
284 phyModeLink.u32 = mipiRxPhyCfg->PHY_MODE_LINK.u32;
285 phyModeLink.bits.phy0_rg_faclk1_en = enable;
286 mipiRxPhyCfg->PHY_MODE_LINK.u32 = phyModeLink.u32;
287 }
288
MipiRxSetPhyRgLp0ModeEn(unsigned int phyId, int enable)289 void MipiRxSetPhyRgLp0ModeEn(unsigned int phyId, int enable)
290 {
291 volatile U_PHY_MODE_LINK phyModeLink;
292 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
293
294 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
295 phyModeLink.u32 = mipiRxPhyCfg->PHY_MODE_LINK.u32;
296 phyModeLink.bits.phy0_rg_en_lp0 = enable;
297 mipiRxPhyCfg->PHY_MODE_LINK.u32 = phyModeLink.u32;
298 }
299
MipiRxSetPhyRgLp1ModeEn(unsigned int phyId, int enable)300 void MipiRxSetPhyRgLp1ModeEn(unsigned int phyId, int enable)
301 {
302 volatile U_PHY_MODE_LINK phyModeLink;
303 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
304
305 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
306 phyModeLink.u32 = mipiRxPhyCfg->PHY_MODE_LINK.u32;
307 phyModeLink.bits.phy0_rg_en_lp1 = enable;
308 mipiRxPhyCfg->PHY_MODE_LINK.u32 = phyModeLink.u32;
309 }
310
MipiRxDrvSetWorkMode(uint8_t devno, InputMode inputMode)311 void MipiRxDrvSetWorkMode(uint8_t devno, InputMode inputMode)
312 {
313 unsigned long *mipiRxWorkModeAddr = (unsigned long *)OsalIoRemap(MIPI_RX_WORK_MODE_ADDR, (unsigned long)0x4);
314
315 if (mipiRxWorkModeAddr == 0) {
316 HDF_LOGE("%s: MipiRx work mode reg ioremap failed!", __func__);
317 return;
318 }
319
320 if (inputMode == INPUT_MODE_MIPI) {
321 WriteReg32(mipiRxWorkModeAddr, 0x0 << (2 * devno), 0x1 << (2 * devno)); /* 2 bit, [1:0] */
322 } else if ((inputMode == INPUT_MODE_SUBLVDS) ||
323 (inputMode == INPUT_MODE_LVDS) || (inputMode == INPUT_MODE_HISPI)) {
324 WriteReg32(mipiRxWorkModeAddr, 0x1 << (2 * devno), 0x1 << (2 * devno)); /* 2 bit, [1:0] */
325 } else {
326 }
327
328 OsalIoUnmap((void *)mipiRxWorkModeAddr);
329 }
330
MipiRxDrvSetMipiImageRect(uint8_t devno, const ImgRect *pImgRect)331 void MipiRxDrvSetMipiImageRect(uint8_t devno, const ImgRect *pImgRect)
332 {
333 U_MIPI_CROP_START_CHN0 cropStartChn0;
334 U_MIPI_CROP_START_CHN1 cropStartChn1;
335 U_MIPI_CROP_START_CHN2 cropStartChn2;
336 U_MIPI_CROP_START_CHN3 cropStartChn3;
337 U_MIPI_IMGSIZE mipiImgsize;
338
339 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
340
341 cropStartChn0.u32 = mipiCtrlRegs->MIPI_CROP_START_CHN0.u32;
342 cropStartChn1.u32 = mipiCtrlRegs->MIPI_CROP_START_CHN1.u32;
343 cropStartChn2.u32 = mipiCtrlRegs->MIPI_CROP_START_CHN2.u32;
344 cropStartChn3.u32 = mipiCtrlRegs->MIPI_CROP_START_CHN3.u32;
345 mipiImgsize.u32 = mipiCtrlRegs->MIPI_IMGSIZE.u32;
346
347 mipiImgsize.bits.mipi_imgwidth = pImgRect->width - 1;
348 mipiImgsize.bits.mipi_imgheight = pImgRect->height - 1;
349
350 cropStartChn0.bits.mipi_start_x_chn0 = pImgRect->x;
351 cropStartChn0.bits.mipi_start_y_chn0 = pImgRect->y;
352
353 cropStartChn1.bits.mipi_start_x_chn1 = pImgRect->x;
354 cropStartChn1.bits.mipi_start_y_chn1 = pImgRect->y;
355
356 cropStartChn2.bits.mipi_start_x_chn2 = pImgRect->x;
357 cropStartChn2.bits.mipi_start_y_chn2 = pImgRect->y;
358
359 cropStartChn3.bits.mipi_start_x_chn3 = pImgRect->x;
360 cropStartChn3.bits.mipi_start_y_chn3 = pImgRect->y;
361
362 mipiCtrlRegs->MIPI_CROP_START_CHN0.u32 = cropStartChn0.u32;
363 mipiCtrlRegs->MIPI_CROP_START_CHN1.u32 = cropStartChn1.u32;
364 mipiCtrlRegs->MIPI_CROP_START_CHN2.u32 = cropStartChn2.u32;
365 mipiCtrlRegs->MIPI_CROP_START_CHN3.u32 = cropStartChn3.u32;
366 mipiCtrlRegs->MIPI_IMGSIZE.u32 = mipiImgsize.u32;
367 }
368
MipiRxDrvSetMipiCropEn(uint8_t devno, int enable)369 void MipiRxDrvSetMipiCropEn(uint8_t devno, int enable)
370 {
371 U_MIPI_CTRL_MODE_PIXEL mipiCtrlModePixel;
372 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
373
374 mipiCtrlModePixel.u32 = mipiCtrlRegs->MIPI_CTRL_MODE_PIXEL.u32;
375 mipiCtrlModePixel.bits.crop_en = enable;
376 mipiCtrlRegs->MIPI_CTRL_MODE_PIXEL.u32 = mipiCtrlModePixel.u32;
377 }
378
MipiRxDrvGetDataType(DataType inputDataType)379 short MipiRxDrvGetDataType(DataType inputDataType)
380 {
381 if (inputDataType == DATA_TYPE_RAW_8BIT) {
382 return 0x2a;
383 } else if (inputDataType == DATA_TYPE_RAW_10BIT) {
384 return 0x2b;
385 } else if (inputDataType == DATA_TYPE_RAW_12BIT) {
386 return 0x2c;
387 } else if (inputDataType == DATA_TYPE_RAW_14BIT) {
388 return 0x2d;
389 } else if (inputDataType == DATA_TYPE_RAW_16BIT) {
390 return 0x2e;
391 } else if (inputDataType == DATA_TYPE_YUV420_8BIT_NORMAL) {
392 return 0x18;
393 } else if (inputDataType == DATA_TYPE_YUV420_8BIT_LEGACY) {
394 return 0x1a;
395 } else if (inputDataType == DATA_TYPE_YUV422_8BIT) {
396 return 0x1e;
397 } else if (inputDataType == DATA_TYPE_YUV422_PACKED) {
398 return 0x1e;
399 } else {
400 return 0x0;
401 }
402 }
403
MipiRxDrvGetDataBitWidth(DataType inputDataType)404 short MipiRxDrvGetDataBitWidth(DataType inputDataType)
405 {
406 if (inputDataType == DATA_TYPE_RAW_8BIT) {
407 return 0x0;
408 } else if (inputDataType == DATA_TYPE_RAW_10BIT) {
409 return 0x1;
410 } else if (inputDataType == DATA_TYPE_RAW_12BIT) {
411 return 0x2;
412 } else if (inputDataType == DATA_TYPE_RAW_14BIT) {
413 return 0x3;
414 } else if (inputDataType == DATA_TYPE_RAW_16BIT) {
415 return 0x4;
416 } else if (inputDataType == DATA_TYPE_YUV420_8BIT_NORMAL) {
417 return 0x0;
418 } else if (inputDataType == DATA_TYPE_YUV420_8BIT_LEGACY) {
419 return 0x0;
420 } else if (inputDataType == DATA_TYPE_YUV422_8BIT) {
421 return 0x0;
422 } else if (inputDataType == DATA_TYPE_YUV422_PACKED) {
423 return 0x4;
424 } else {
425 return 0x0;
426 }
427 }
428
429 /* magic num mean bit width, convert to register condfig */
MipiRxDrvGetExtDataBitWidth(unsigned int extDataBitWidth)430 short MipiRxDrvGetExtDataBitWidth(unsigned int extDataBitWidth)
431 {
432 if (extDataBitWidth == 8) { /* 8:magic bit width */
433 return 0x0;
434 } else if (extDataBitWidth == 10) { /* 10:magic bit width */
435 return 0x1;
436 } else if (extDataBitWidth == 12) { /* 12:magic bit width */
437 return 0x2;
438 } else if (extDataBitWidth == 14) { /* 14:magic bit width */
439 return 0x3;
440 } else if (extDataBitWidth == 16) { /* 16:magic bit width */
441 return 0x4;
442 } else {
443 return 0x0;
444 }
445 }
446
MipiRxDrvSetDiDt(uint8_t devno, DataType inputDataType)447 void MipiRxDrvSetDiDt(uint8_t devno, DataType inputDataType)
448 {
449 U_MIPI_DI_1 mipiDi1;
450 U_MIPI_DI_2 mipiDi2;
451 unsigned int tempDataType;
452 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
453
454 tempDataType = MipiRxDrvGetDataType(inputDataType);
455
456 mipiDi1.u32 = mipiCtrlRegs->MIPI_DI_1.u32;
457 mipiDi1.bits.di0_dt = tempDataType;
458 mipiDi1.bits.di1_dt = tempDataType;
459 mipiDi1.bits.di2_dt = tempDataType;
460 mipiDi1.bits.di3_dt = tempDataType;
461 mipiCtrlRegs->MIPI_DI_1.u32 = mipiDi1.u32;
462
463 mipiDi2.u32 = mipiCtrlRegs->MIPI_DI_2.u32;
464 mipiDi2.bits.di4_dt = tempDataType;
465 mipiDi2.bits.di5_dt = tempDataType;
466 mipiDi2.bits.di6_dt = tempDataType;
467 mipiDi2.bits.di7_dt = tempDataType;
468 mipiCtrlRegs->MIPI_DI_2.u32 = mipiDi2.u32;
469 }
470
MipiRxDrvSetModePixel(uint8_t devno, DataType inputDataType)471 static void MipiRxDrvSetModePixel(uint8_t devno, DataType inputDataType)
472 {
473 U_MIPI_CTRL_MODE_PIXEL mipiCtrlModePixel;
474 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
475
476 mipiCtrlModePixel.u32 = mipiCtrlRegs->MIPI_CTRL_MODE_PIXEL.u32;
477
478 if (inputDataType == DATA_TYPE_YUV420_8BIT_NORMAL) {
479 mipiCtrlModePixel.bits.mipi_yuv420_even_detect = 1;
480 mipiCtrlModePixel.bits.mipi_yuv_420_nolegacy_en = 1;
481 mipiCtrlModePixel.bits.mipi_yuv_420_legacy_en = 0;
482 mipiCtrlModePixel.bits.mipi_yuv_422_en = 0;
483 } else if (inputDataType == DATA_TYPE_YUV420_8BIT_LEGACY) {
484 mipiCtrlModePixel.bits.mipi_yuv_420_nolegacy_en = 0;
485 mipiCtrlModePixel.bits.mipi_yuv_420_legacy_en = 1;
486 mipiCtrlModePixel.bits.mipi_yuv_422_en = 0;
487 } else if (inputDataType == DATA_TYPE_YUV422_8BIT) {
488 mipiCtrlModePixel.bits.mipi_yuv_420_nolegacy_en = 0;
489 mipiCtrlModePixel.bits.mipi_yuv_420_legacy_en = 0;
490 mipiCtrlModePixel.bits.mipi_yuv_422_en = 1;
491 } else {
492 mipiCtrlModePixel.bits.mipi_yuv_420_nolegacy_en = 0;
493 mipiCtrlModePixel.bits.mipi_yuv_420_legacy_en = 0;
494 mipiCtrlModePixel.bits.mipi_yuv_422_en = 0;
495 }
496
497 mipiCtrlRegs->MIPI_CTRL_MODE_PIXEL.u32 = mipiCtrlModePixel.u32;
498 }
499
MipiRxDrvSetUserDef(uint8_t devno, DataType inputDataType)500 static void MipiRxDrvSetUserDef(uint8_t devno, DataType inputDataType)
501 {
502 unsigned char bitWidth;
503 unsigned int tempDataType;
504 U_MIPI_USERDEF_DT userDefDt;
505 U_MIPI_USER_DEF userDef;
506 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
507
508 if (inputDataType == DATA_TYPE_YUV420_8BIT_NORMAL) {
509 bitWidth = 0;
510 tempDataType = 0x18;
511 } else if (inputDataType == DATA_TYPE_YUV420_8BIT_LEGACY) {
512 bitWidth = 0;
513 tempDataType = 0x1a;
514 } else if (inputDataType == DATA_TYPE_YUV422_8BIT) {
515 bitWidth = 0; /* 0 -- 8bit */
516 tempDataType = 0x1e;
517 } else if (inputDataType == DATA_TYPE_YUV422_PACKED) {
518 bitWidth = 4; /* 4 -- 16bit */
519 tempDataType = 0x1e;
520 } else {
521 return;
522 }
523
524 userDefDt.u32 = mipiCtrlRegs->MIPI_USERDEF_DT.u32;
525 userDef.u32 = mipiCtrlRegs->MIPI_USER_DEF.u32;
526
527 userDefDt.bits.user_def0_dt = bitWidth;
528 userDefDt.bits.user_def1_dt = bitWidth;
529 userDefDt.bits.user_def2_dt = bitWidth;
530 userDefDt.bits.user_def3_dt = bitWidth;
531
532 userDef.bits.user_def0 = tempDataType;
533 userDef.bits.user_def1 = tempDataType;
534 userDef.bits.user_def2 = tempDataType;
535 userDef.bits.user_def3 = tempDataType;
536
537 mipiCtrlRegs->MIPI_USERDEF_DT.u32 = userDefDt.u32;
538 mipiCtrlRegs->MIPI_USER_DEF.u32 = userDef.u32;
539
540 return;
541 }
542
MipiRxDrvCtrlModeHs(uint8_t devno, DataType inputDataType)543 static void MipiRxDrvCtrlModeHs(uint8_t devno, DataType inputDataType)
544 {
545 unsigned char userDefEn;
546 U_MIPI_CTRL_MODE_HS mipiCtrlModeHs;
547 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
548
549 if ((inputDataType == DATA_TYPE_YUV420_8BIT_NORMAL) ||
550 (inputDataType == DATA_TYPE_YUV420_8BIT_LEGACY) ||
551 (inputDataType == DATA_TYPE_YUV422_8BIT) ||
552 (inputDataType == DATA_TYPE_YUV422_PACKED)) {
553 userDefEn = 1;
554 } else {
555 userDefEn = 0;
556 }
557
558 mipiCtrlModeHs.u32 = mipiCtrlRegs->MIPI_CTRL_MODE_HS.u32;
559
560 mipiCtrlModeHs.bits.user_def_en = userDefEn;
561
562 mipiCtrlRegs->MIPI_CTRL_MODE_HS.u32 = mipiCtrlModeHs.u32;
563 }
564
MipiRxDrvSetMipiUserDt(uint8_t devno, int index, short dataType, short bitWidth)565 void MipiRxDrvSetMipiUserDt(uint8_t devno, int index, short dataType, short bitWidth)
566 {
567 U_MIPI_USERDEF_DT userDefDt;
568 U_MIPI_USER_DEF userDef;
569 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
570
571 if (mipiCtrlRegs != NULL) {
572 userDefDt.u32 = mipiCtrlRegs->MIPI_USERDEF_DT.u32;
573 userDef.u32 = mipiCtrlRegs->MIPI_USER_DEF.u32;
574
575 if (index == DEF0_DATA) {
576 userDefDt.bits.user_def0_dt = bitWidth;
577 userDef.bits.user_def0 = dataType;
578 } else if (index == DEF1_DATA) {
579 userDefDt.bits.user_def1_dt = bitWidth;
580 userDef.bits.user_def1 = dataType;
581 } else if (index == DEF2_DATA) {
582 userDefDt.bits.user_def2_dt = bitWidth;
583 userDef.bits.user_def2 = dataType;
584 } else if (index == DEF3_DATA) {
585 userDefDt.bits.user_def3_dt = bitWidth;
586 userDef.bits.user_def3 = dataType;
587 }
588
589 mipiCtrlRegs->MIPI_USERDEF_DT.u32 = userDefDt.u32;
590 mipiCtrlRegs->MIPI_USER_DEF.u32 = userDef.u32;
591 }
592 }
593
MipiRxDrvSetMipiYuvDt(uint8_t devno, DataType inputDataType)594 void MipiRxDrvSetMipiYuvDt(uint8_t devno, DataType inputDataType)
595 {
596 MipiRxDrvCtrlModeHs(devno, inputDataType);
597 MipiRxDrvSetUserDef(devno, inputDataType);
598 MipiRxDrvSetModePixel(devno, inputDataType);
599 }
600
MipiRxDrvSetMipiWdrUserDt(uint8_t devno, DataType inputDataType, const short dataType[WDR_VC_NUM])601 void MipiRxDrvSetMipiWdrUserDt(uint8_t devno, DataType inputDataType, const short dataType[WDR_VC_NUM])
602 {
603 U_MIPI_USERDEF_DT userDefDt;
604 U_MIPI_USER_DEF userDef;
605 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
606
607 userDefDt.u32 = mipiCtrlRegs->MIPI_USERDEF_DT.u32;
608 userDef.u32 = mipiCtrlRegs->MIPI_USER_DEF.u32;
609
610 userDefDt.bits.user_def0_dt = inputDataType;
611 userDefDt.bits.user_def1_dt = inputDataType;
612
613 userDef.bits.user_def0 = dataType[0];
614 userDef.bits.user_def1 = dataType[1];
615
616 mipiCtrlRegs->MIPI_USERDEF_DT.u32 = userDefDt.u32;
617 mipiCtrlRegs->MIPI_USER_DEF.u32 = userDef.u32;
618 }
619
MipiRxDrvSetMipiDolId(uint8_t devno, DataType inputDataType, const short dolId[])620 void MipiRxDrvSetMipiDolId(uint8_t devno, DataType inputDataType, const short dolId[])
621 {
622 U_MIPI_DOL_ID_CODE0 dolId0;
623 U_MIPI_DOL_ID_CODE1 dolId1;
624 U_MIPI_DOL_ID_CODE2 dolId2;
625 short lef, sef1, sef2;
626 short nxtLef, nxtSef1, nxtSef2;
627 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
628
629 (void)inputDataType;
630 (void)dolId;
631 dolId0.u32 = mipiCtrlRegs->MIPI_DOL_ID_CODE0.u32;
632 dolId1.u32 = mipiCtrlRegs->MIPI_DOL_ID_CODE1.u32;
633 dolId2.u32 = mipiCtrlRegs->MIPI_DOL_ID_CODE2.u32;
634
635 lef = 0x241;
636 sef1 = 0x242;
637 sef2 = 0x244;
638
639 nxtLef = lef + DOL_ID_CODE_OFFSET; /* 4:The LEF frame ID code of the N+1 frame is larger than the LEF frame
640 * ID code of the Nth frame(1 << 4)
641 */
642 nxtSef1 = sef1 + DOL_ID_CODE_OFFSET; /* 4:The SEF1 frame ID code of the N+1 frame is larger than the LEF frame
643 * ID code of the Nth frame(1 << 4)
644 */
645 nxtSef2 = sef2 + DOL_ID_CODE_OFFSET; /* 4:The SEF2 frame ID code of the N+1 frame is larger than the LEF frame
646 * ID code of the Nth frame(1 << 4)
647 */
648
649 dolId0.bits.id_code_reg0 = lef;
650 dolId0.bits.id_code_reg1 = sef1;
651 dolId1.bits.id_code_reg2 = sef2;
652
653 dolId1.bits.id_code_reg3 = nxtLef;
654 dolId2.bits.id_code_reg4 = nxtSef1;
655 dolId2.bits.id_code_reg5 = nxtSef2;
656
657 mipiCtrlRegs->MIPI_DOL_ID_CODE0.u32 = dolId0.u32;
658 mipiCtrlRegs->MIPI_DOL_ID_CODE1.u32 = dolId1.u32;
659 mipiCtrlRegs->MIPI_DOL_ID_CODE2.u32 = dolId2.u32;
660 }
661
MipiRxDrvSetMipiWdrMode(uint8_t devno, MipiWdrMode wdrMode)662 void MipiRxDrvSetMipiWdrMode(uint8_t devno, MipiWdrMode wdrMode)
663 {
664 U_MIPI_CTRL_MODE_HS modeHs;
665 U_MIPI_CTRL_MODE_PIXEL modePixel;
666 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
667
668 modeHs.u32 = mipiCtrlRegs->MIPI_CTRL_MODE_HS.u32;
669 modePixel.u32 = mipiCtrlRegs->MIPI_CTRL_MODE_PIXEL.u32;
670
671 if (wdrMode == HI_MIPI_WDR_MODE_NONE) {
672 modePixel.bits.mipi_dol_mode = 0;
673 }
674
675 if (wdrMode == HI_MIPI_WDR_MODE_VC) {
676 modePixel.bits.mipi_dol_mode = 0;
677 } else if (wdrMode == HI_MIPI_WDR_MODE_DT) {
678 modeHs.bits.user_def_en = 1;
679 } else if (wdrMode == HI_MIPI_WDR_MODE_DOL) {
680 modePixel.bits.mipi_dol_mode = 1;
681 }
682
683 mipiCtrlRegs->MIPI_CTRL_MODE_HS.u32 = modeHs.u32;
684 mipiCtrlRegs->MIPI_CTRL_MODE_PIXEL.u32 = modePixel.u32;
685 }
686
MipiRxDrvEnableUserDefineDt(uint8_t devno, int enable)687 void MipiRxDrvEnableUserDefineDt(uint8_t devno, int enable)
688 {
689 U_MIPI_CTRL_MODE_HS modeHs;
690 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
691
692 if (mipiCtrlRegs != NULL) {
693 modeHs.u32 = mipiCtrlRegs->MIPI_CTRL_MODE_HS.u32;
694 modeHs.bits.user_def_en = enable;
695
696 mipiCtrlRegs->MIPI_CTRL_MODE_HS.u32 = modeHs.u32;
697 }
698 }
699
MipiRxDrvSetExtDataType(const ExtDataType* dataType, DataType inputDataType)700 void MipiRxDrvSetExtDataType(const ExtDataType* dataType, DataType inputDataType)
701 {
702 unsigned int i;
703 uint8_t devno;
704 short inputDt;
705 short bitWidth;
706 short extBitWidth;
707
708 devno = dataType->devno;
709 inputDt = MipiRxDrvGetDataType(inputDataType);
710 bitWidth = MipiRxDrvGetDataBitWidth(inputDataType);
711
712 MipiRxDrvSetMipiUserDt(devno, 0, inputDt, bitWidth);
713
714 for (i = 0; i < dataType->num; i++) {
715 extBitWidth = MipiRxDrvGetExtDataBitWidth(dataType->extDataBitWidth[i]);
716 MipiRxDrvSetMipiUserDt(devno, i + 1, dataType->extDataType[i], extBitWidth);
717 }
718
719 MipiRxDrvEnableUserDefineDt(devno, 1);
720 }
721
MipiRxDrvGetPhyData(int phyId, int laneId)722 unsigned int MipiRxDrvGetPhyData(int phyId, int laneId)
723 {
724 volatile U_PHY_DATA_LINK phyDataLink;
725 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
726 unsigned int laneData = 0x0;
727
728 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
729 phyDataLink.u32 = mipiRxPhyCfg->PHY_DATA_LINK.u32;
730
731 if (laneId == 0) { /* 0 -- laneId 0 */
732 laneData = phyDataLink.bits.phy_data0_mipi;
733 } else if (laneId == 1) { /* 1 -- laneId 1 */
734 laneData = phyDataLink.bits.phy_data1_mipi;
735 } else if (laneId == 2) { /* 2 -- laneId 2 */
736 laneData = phyDataLink.bits.phy_data2_mipi;
737 } else if (laneId == 3) { /* 3 -- laneId 3 */
738 laneData = phyDataLink.bits.phy_data3_mipi;
739 }
740
741 return laneData;
742 }
743
MipiRxDrvGetPhyMipiLinkData(int phyId, int laneId)744 unsigned int MipiRxDrvGetPhyMipiLinkData(int phyId, int laneId)
745 {
746 volatile U_PHY_DATA_MIPI_LINK phyDataMipiLink;
747 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
748 unsigned int laneData = 0x0;
749
750 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
751 phyDataMipiLink.u32 = mipiRxPhyCfg->PHY_DATA_MIPI_LINK.u32;
752
753 if (laneId == 0) { /* 0 -- laneId 0 */
754 laneData = phyDataMipiLink.bits.phy_data0_mipi_hs;
755 } else if (laneId == 1) { /* 1 -- laneId 1 */
756 laneData = phyDataMipiLink.bits.phy_data1_mipi_hs;
757 } else if (laneId == 2) { /* 2 -- laneId 2 */
758 laneData = phyDataMipiLink.bits.phy_data2_mipi_hs;
759 } else if (laneId == 3) { /* 3 -- laneId 3 */
760 laneData = phyDataMipiLink.bits.phy_data3_mipi_hs;
761 }
762
763 return laneData;
764 }
765
766
MipiRxDrvGetPhyLvdsLinkData(int phyId, int laneId)767 unsigned int MipiRxDrvGetPhyLvdsLinkData(int phyId, int laneId)
768 {
769 volatile U_PHY_DATA_LVDS_LINK phyDataLvdsLink;
770 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
771 unsigned int laneData = 0x0;
772
773 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
774 phyDataLvdsLink.u32 = mipiRxPhyCfg->PHY_DATA_LVDS_LINK.u32;
775
776 if (laneId == 0) { /* 0 -- laneId 0 */
777 laneData = phyDataLvdsLink.bits.phy_data0_lvds_hs;
778 } else if (laneId == 1) { /* 1 -- laneId 1 */
779 laneData = phyDataLvdsLink.bits.phy_data1_lvds_hs;
780 } else if (laneId == 2) { /* 2 -- laneId 2 */
781 laneData = phyDataLvdsLink.bits.phy_data2_lvds_hs;
782 } else if (laneId == 3) { /* 3 -- laneId 3 */
783 laneData = phyDataLvdsLink.bits.phy_data3_lvds_hs;
784 }
785
786 return laneData;
787 }
788
MipiRxDrvSetDataRate(uint8_t devno, MipiDataRate dataRate)789 void MipiRxDrvSetDataRate(uint8_t devno, MipiDataRate dataRate)
790 {
791 U_MIPI_CTRL_MODE_PIXEL mipiCtrlModePixel;
792 unsigned int mipiDoublePixEn = 0;
793 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
794
795 if (dataRate == MIPI_DATA_RATE_X1) {
796 mipiDoublePixEn = 0;
797 } else if (dataRate == MIPI_DATA_RATE_X2) {
798 mipiDoublePixEn = 1;
799 } else {
800 HDF_LOGE("%s: unsupported dataRate:%d devno %hhu", __func__, dataRate, devno);
801 return;
802 }
803
804 mipiCtrlModePixel.u32 = mipiCtrlRegs->MIPI_CTRL_MODE_PIXEL.u32;
805 mipiCtrlModePixel.bits.mipi_double_pix_en = mipiDoublePixEn;
806 mipiCtrlModePixel.bits.sync_clear_en = 0x1;
807 mipiCtrlRegs->MIPI_CTRL_MODE_PIXEL.u32 = mipiCtrlModePixel.u32;
808 }
809
MipiRxSetLaneId(uint8_t devno, int laneIdx, short laneId, unsigned int laneBitmap, LaneDivideMode mode)810 void MipiRxSetLaneId(uint8_t devno, int laneIdx, short laneId,
811 unsigned int laneBitmap, LaneDivideMode mode)
812 {
813 U_LANE_ID0_CHN laneId0Ch0;
814
815 volatile LvdsCtrlRegsTag *lvdsCtrlRegs = GetLvdsCtrlRegs(devno);
816
817 laneId0Ch0.u32 = lvdsCtrlRegs->LANE_ID0_CHN0.u32;
818
819 switch (laneId) {
820 case 0: /* 0 -- laneId 0 */
821 laneId0Ch0.bits.lane0_id = laneIdx;
822 break;
823
824 case 1: /* 1 -- laneId 1 */
825 laneId0Ch0.bits.lane1_id = laneIdx;
826 break;
827
828 case 2: /* 2 -- laneId 2 */
829 laneId0Ch0.bits.lane2_id = laneIdx;
830 break;
831
832 case 3: /* 3 -- laneId 3 */
833 laneId0Ch0.bits.lane3_id = laneIdx;
834 break;
835
836 default:
837 break;
838 }
839
840 if (laneBitmap == 0xa && mode == 1 && devno == 1) {
841 laneId0Ch0.u32 = 0x3210;
842 }
843
844 lvdsCtrlRegs->LANE_ID0_CHN0.u32 = laneId0Ch0.u32;
845 }
846
MipiRxDrvSetLinkLaneId(uint8_t devno, InputMode inputMode, const short *pLaneId, unsigned int laneBitmap, LaneDivideMode mode)847 void MipiRxDrvSetLinkLaneId(uint8_t devno, InputMode inputMode, const short *pLaneId,
848 unsigned int laneBitmap, LaneDivideMode mode)
849 {
850 int i;
851 int laneNum;
852
853 if (inputMode == INPUT_MODE_MIPI) {
854 laneNum = MIPI_LANE_NUM;
855 } else {
856 laneNum = LVDS_LANE_NUM;
857 }
858
859 for (i = 0; i < laneNum; i++) {
860 if (pLaneId[i] != -1) {
861 MipiRxSetLaneId(devno, i, pLaneId[i], laneBitmap, mode);
862 }
863 }
864 }
865
MipiRxDrvSetMemCken(uint8_t devno, int enable)866 void MipiRxDrvSetMemCken(uint8_t devno, int enable)
867 {
868 U_CHN0_MEM_CTRL chn0MemCtrl;
869 U_CHN1_MEM_CTRL chn1MemCtrl;
870 MipiRxSysRegsTag *mipiRxSysRegs = NULL;
871
872 mipiRxSysRegs = GetMipiRxSysRegs();
873
874 switch (devno) {
875 case 0: /* 0 -- mipi dev 0 */
876 chn0MemCtrl.u32 = mipiRxSysRegs->CHN0_MEM_CTRL.u32;
877 chn0MemCtrl.bits.chn0_mem_ck_gt = enable;
878 mipiRxSysRegs->CHN0_MEM_CTRL.u32 = chn0MemCtrl.u32;
879 break;
880 case 1: /* 1 -- mipi dev 1 */
881 chn1MemCtrl.u32 = mipiRxSysRegs->CHN1_MEM_CTRL.u32;
882 chn1MemCtrl.bits.chn1_mem_ck_gt = enable;
883 mipiRxSysRegs->CHN1_MEM_CTRL.u32 = chn1MemCtrl.u32;
884 break;
885 default:
886 break;
887 }
888 }
889
MipiRxDrvSetClrCken(uint8_t devno, int enable)890 void MipiRxDrvSetClrCken(uint8_t devno, int enable)
891 {
892 U_CHN0_CLR_EN chn0ClrEn;
893 U_CHN1_CLR_EN chn1ClrEn;
894 MipiRxSysRegsTag *mipiRxSysRegs = NULL;
895
896 mipiRxSysRegs = GetMipiRxSysRegs();
897
898 switch (devno) {
899 case 0: /* 0 -- mipi dev 0 */
900 chn0ClrEn.u32 = mipiRxSysRegs->CHN0_CLR_EN.u32;
901 chn0ClrEn.bits.chn0_clr_en_lvds = enable;
902 chn0ClrEn.bits.chn0_clr_en_align = enable;
903 mipiRxSysRegs->CHN0_CLR_EN.u32 = chn0ClrEn.u32;
904 break;
905 case 1: /* 1 -- mipi dev 1 */
906 chn1ClrEn.u32 = mipiRxSysRegs->CHN1_CLR_EN.u32;
907 chn1ClrEn.bits.chn1_clr_en_lvds = enable;
908 chn1ClrEn.bits.chn1_clr_en_align = enable;
909 mipiRxSysRegs->CHN1_CLR_EN.u32 = chn1ClrEn.u32;
910 break;
911
912 default:
913 break;
914 }
915 }
916
MipiRxDrvSetLaneNum(uint8_t devno, unsigned int laneNum)917 void MipiRxDrvSetLaneNum(uint8_t devno, unsigned int laneNum)
918 {
919 U_MIPI_LANES_NUM mipiLanesNum;
920 MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
921
922 mipiLanesNum.u32 = mipiCtrlRegs->MIPI_LANES_NUM.u32;
923 mipiLanesNum.bits.lane_num = laneNum - 1;
924 mipiCtrlRegs->MIPI_LANES_NUM.u32 = mipiLanesNum.u32;
925 }
926
MipiRxDrvSetPhyEnLink(unsigned int phyId, unsigned int laneBitmap)927 void MipiRxDrvSetPhyEnLink(unsigned int phyId, unsigned int laneBitmap)
928 {
929 U_PHY_EN_LINK phyEnLink;
930 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
931
932 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
933 phyEnLink.u32 = mipiRxPhyCfg->PHY_EN_LINK.u32;
934
935 if (laneBitmap & 0x5) {
936 phyEnLink.bits.phy_da_d0_valid = laneBitmap & 0x1; /* 0 -- lane0 */
937 phyEnLink.bits.phy_da_d2_valid = (laneBitmap & 0x4) >> 2; /* 2 -- lane2 */
938 phyEnLink.bits.phy_d0_term_en = laneBitmap & 0x1;
939 phyEnLink.bits.phy_d2_term_en = (laneBitmap & 0x4) >> 2; /* 2 -- lane2 */
940 phyEnLink.bits.phy_clk0_term_en = 1;
941 }
942
943 if (laneBitmap & 0xa) {
944 phyEnLink.bits.phy_da_d1_valid = (laneBitmap & 0x2) >> 1; /* 1 -- lane1 */
945 phyEnLink.bits.phy_da_d3_valid = (laneBitmap & 0x8) >> 3; /* 3 -- lane3 */
946 phyEnLink.bits.phy_d1_term_en = (laneBitmap & 0x2) >> 1; /* 1 -- lane1 */
947 phyEnLink.bits.phy_d3_term_en = (laneBitmap & 0x8) >> 3; /* 3 -- lane3 */
948 phyEnLink.bits.phy_clk1_term_en = 1;
949 }
950
951 mipiRxPhyCfg->PHY_EN_LINK.u32 = phyEnLink.u32;
952 }
953
MipiRxDrvSetPhyMode(unsigned int phyId, InputMode inputMode, unsigned int laneBitmap)954 void MipiRxDrvSetPhyMode(unsigned int phyId, InputMode inputMode, unsigned int laneBitmap)
955 {
956 U_PHY_MODE_LINK phyModeLink;
957 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
958 int cmosEn = 0;
959
960 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
961 phyModeLink.u32 = mipiRxPhyCfg->PHY_MODE_LINK.u32;
962
963 if (inputMode == INPUT_MODE_CMOS ||
964 inputMode == INPUT_MODE_BT1120 ||
965 inputMode == INPUT_MODE_BYPASS) {
966 cmosEn = 1;
967 }
968
969 phyModeLink.bits.phy0_rg_en_d = phyModeLink.bits.phy0_rg_en_d | (laneBitmap & 0xf);
970 phyModeLink.bits.phy0_rg_en_cmos = cmosEn;
971 phyModeLink.bits.phy0_rg_en_clk0 = 1;
972 phyModeLink.bits.phy0_rg_mipi_mode0 = 1;
973
974 if (laneBitmap & 0xa) {
975 phyModeLink.bits.phy0_rg_en_clk1 = 1;
976 phyModeLink.bits.phy0_rg_mipi_mode1 = 1;
977 }
978
979 mipiRxPhyCfg->PHY_MODE_LINK.u32 = phyModeLink.u32;
980 }
981
MipiRxDrvSetCmosEn(unsigned int phyId, int enable)982 void MipiRxDrvSetCmosEn(unsigned int phyId, int enable)
983 {
984 volatile U_PHY_MODE_LINK phyModeLink;
985 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
986
987 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
988 phyModeLink.u32 = mipiRxPhyCfg->PHY_MODE_LINK.u32;
989 phyModeLink.bits.phy0_rg_en_cmos = enable;
990 mipiRxPhyCfg->PHY_MODE_LINK.u32 = phyModeLink.u32;
991 }
992
MipiRxDrvSetPhyEn(unsigned int laneBitmap)993 void MipiRxDrvSetPhyEn(unsigned int laneBitmap)
994 {
995 U_PHY_EN phyEn;
996 MipiRxSysRegsTag *mipiRxSysRegs = NULL;
997
998 mipiRxSysRegs = GetMipiRxSysRegs();
999 phyEn.u32 = mipiRxSysRegs->PHY_EN.u32;
1000
1001 if (laneBitmap & 0xf) {
1002 phyEn.bits.phy0_en = 1;
1003 }
1004
1005 mipiRxSysRegs->PHY_EN.u32 = phyEn.u32;
1006 }
1007
MipiRxDrvSetLaneEn(unsigned int laneBitmap)1008 void MipiRxDrvSetLaneEn(unsigned int laneBitmap)
1009 {
1010 U_LANE_EN laneEn;
1011 MipiRxSysRegsTag *mipiRxSysRegs = NULL;
1012
1013 mipiRxSysRegs = GetMipiRxSysRegs();
1014 laneEn.u32 = mipiRxSysRegs->LANE_EN.u32;
1015 laneEn.u32 = laneEn.u32 | (laneBitmap & 0xf);
1016 mipiRxSysRegs->LANE_EN.u32 = laneEn.u32;
1017 }
1018
MipiRxDrvSetPhyCilEn(unsigned int laneBitmap, int enable)1019 void MipiRxDrvSetPhyCilEn(unsigned int laneBitmap, int enable)
1020 {
1021 U_PHY_CIL_CTRL phyCilCtrl;
1022 MipiRxSysRegsTag *mipiRxSysRegs = NULL;
1023
1024 mipiRxSysRegs = GetMipiRxSysRegs();
1025 phyCilCtrl.u32 = mipiRxSysRegs->PHY_CIL_CTRL.u32;
1026
1027 if (laneBitmap & 0xf) {
1028 phyCilCtrl.bits.phycil0_cken = enable;
1029 }
1030
1031 mipiRxSysRegs->PHY_CIL_CTRL.u32 = phyCilCtrl.u32;
1032 }
1033
MipiRxDrvSetPhyCfgMode(InputMode inputMode, unsigned int laneBitmap)1034 void MipiRxDrvSetPhyCfgMode(InputMode inputMode, unsigned int laneBitmap)
1035 {
1036 U_PHYCFG_MODE phycfgMode;
1037 MipiRxSysRegsTag *mipiRxSysRegs = NULL;
1038 unsigned int cfgMode;
1039 unsigned int cfgModeSel;
1040
1041 mipiRxSysRegs = GetMipiRxSysRegs();
1042 phycfgMode.u32 = mipiRxSysRegs->PHYCFG_MODE.u32;
1043
1044 if (inputMode == INPUT_MODE_MIPI) {
1045 cfgMode = 0;
1046 cfgModeSel = 0;
1047 } else if (inputMode == INPUT_MODE_SUBLVDS ||
1048 inputMode == INPUT_MODE_LVDS ||
1049 inputMode == INPUT_MODE_HISPI) {
1050 cfgMode = 1;
1051 cfgModeSel = 0; /* RAW */
1052 } else {
1053 cfgMode = 2; /* 2 -- PHY cfg is controlled by register value */
1054 cfgModeSel = 1; /* CMOS */
1055 }
1056
1057 if (laneBitmap & 0xf) {
1058 phycfgMode.bits.phycil0_0_cfg_mode = cfgMode;
1059 phycfgMode.bits.phycil0_1_cfg_mode = cfgMode;
1060 phycfgMode.bits.phycil0_cfg_mode_sel = cfgModeSel;
1061 } else if (laneBitmap & 0x5) {
1062 phycfgMode.bits.phycil0_0_cfg_mode = cfgMode;
1063 phycfgMode.bits.phycil0_cfg_mode_sel = cfgModeSel;
1064 } else if (laneBitmap & 0xa) {
1065 phycfgMode.bits.phycil0_1_cfg_mode = cfgMode;
1066 phycfgMode.bits.phycil0_cfg_mode_sel = cfgModeSel;
1067 }
1068
1069 mipiRxSysRegs->PHYCFG_MODE.u32 = phycfgMode.u32;
1070 }
1071
MipiRxDrvSetPhyCfgEn(unsigned int laneBitmap, int enable)1072 void MipiRxDrvSetPhyCfgEn(unsigned int laneBitmap, int enable)
1073 {
1074 U_PHYCFG_EN phycfgEn;
1075 MipiRxSysRegsTag *mipiRxSysRegs = NULL;
1076
1077 mipiRxSysRegs = GetMipiRxSysRegs();
1078 phycfgEn.u32 = mipiRxSysRegs->PHYCFG_EN.u32;
1079
1080 if (laneBitmap & 0xf) {
1081 phycfgEn.bits.phycil0_cfg_en = enable;
1082 }
1083
1084 mipiRxSysRegs->PHYCFG_EN.u32 = phycfgEn.u32;
1085 }
1086
MipiRxDrvSetPhyConfig(InputMode inputMode, unsigned int laneBitmap)1087 void MipiRxDrvSetPhyConfig(InputMode inputMode, unsigned int laneBitmap)
1088 {
1089 unsigned int i;
1090 unsigned int mask;
1091 unsigned int phyLaneBitmap;
1092
1093 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
1094 mask = 0xf << (4 * i); /* 4 -- 4bit */
1095 if (laneBitmap & mask) {
1096 phyLaneBitmap = (laneBitmap & mask) >> (4 * i); /* 4 -- 4bit */
1097 MipiRxDrvSetPhyEnLink(i, phyLaneBitmap);
1098 MipiRxDrvSetPhyMode(i, inputMode, phyLaneBitmap);
1099 }
1100 }
1101
1102 MipiRxDrvSetPhyEn(laneBitmap);
1103 MipiRxDrvSetLaneEn(laneBitmap);
1104 MipiRxDrvSetPhyCilEn(laneBitmap, 1);
1105 MipiRxDrvSetPhyCfgMode(inputMode, laneBitmap);
1106 MipiRxDrvSetPhyCfgEn(laneBitmap, 1);
1107 }
1108
MipiRxDrvSetPhyCmv(unsigned int phyId, PhyCmvMode cmvMode, unsigned int laneBitmap)1109 static void MipiRxDrvSetPhyCmv(unsigned int phyId, PhyCmvMode cmvMode, unsigned int laneBitmap)
1110 {
1111 int mipiCmvMode = 0;
1112 U_PHY_MODE_LINK phyModeLink;
1113 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
1114
1115 if (cmvMode == PHY_CMV_GE1200MV) {
1116 mipiCmvMode = 0;
1117 } else if (cmvMode == PHY_CMV_LT1200MV) {
1118 mipiCmvMode = 1;
1119 }
1120
1121 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
1122 phyModeLink.u32 = mipiRxPhyCfg->PHY_MODE_LINK.u32;
1123
1124 if (laneBitmap & 0xa) {
1125 phyModeLink.bits.phy0_rg_mipi_mode1 = mipiCmvMode;
1126 }
1127
1128 if (laneBitmap & 0x5) {
1129 phyModeLink.bits.phy0_rg_mipi_mode0 = mipiCmvMode;
1130 }
1131
1132 mipiRxPhyCfg->PHY_MODE_LINK.u32 = phyModeLink.u32;
1133 }
1134
MipiRxDrvSetPhyCmvmode(InputMode inputMode, PhyCmvMode cmvMode, unsigned int laneBitmap)1135 void MipiRxDrvSetPhyCmvmode(InputMode inputMode, PhyCmvMode cmvMode, unsigned int laneBitmap)
1136 {
1137 unsigned int i;
1138 unsigned int mask;
1139 unsigned int phyLaneBitmap;
1140
1141 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
1142 mask = 0xf << (4 * i); /* 4 -- 4bit */
1143 if (laneBitmap & mask) {
1144 phyLaneBitmap = (laneBitmap & mask) >> (4 * i); /* 4 -- 4bit */
1145 MipiRxDrvSetPhyCmv(i, cmvMode, phyLaneBitmap);
1146 }
1147 }
1148
1149 MipiRxDrvSetPhyCfgMode(inputMode, laneBitmap);
1150 MipiRxDrvSetPhyCfgEn(laneBitmap, 1);
1151 }
1152
MipiRxDrvSetLvdsImageRect(uint8_t devno, const ImgRect *pImgRect, short totalLaneNum)1153 void MipiRxDrvSetLvdsImageRect(uint8_t devno, const ImgRect *pImgRect, short totalLaneNum)
1154 {
1155 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1156 U_LVDS_IMGSIZE lvdsImgSize;
1157 U_LVDS_CROP_START0 cropStart0;
1158 U_LVDS_CROP_START1 cropStart1;
1159 U_LVDS_CROP_START2 cropStart2;
1160 U_LVDS_CROP_START3 cropStart3;
1161 unsigned int widthPerLane, xPerLane;
1162
1163 ctrlReg = GetLvdsCtrlRegs(devno);
1164
1165 if (totalLaneNum == 0) {
1166 return;
1167 }
1168
1169 widthPerLane = (pImgRect->width / totalLaneNum);
1170 xPerLane = (pImgRect->x / totalLaneNum);
1171
1172 lvdsImgSize.u32 = ctrlReg->LVDS_IMGSIZE.u32;
1173 cropStart0.u32 = ctrlReg->LVDS_CROP_START0.u32;
1174 cropStart1.u32 = ctrlReg->LVDS_CROP_START1.u32;
1175 cropStart2.u32 = ctrlReg->LVDS_CROP_START2.u32;
1176 cropStart3.u32 = ctrlReg->LVDS_CROP_START3.u32;
1177
1178 lvdsImgSize.bits.lvds_imgwidth_lane = widthPerLane - 1;
1179 lvdsImgSize.bits.lvds_imgheight = pImgRect->height - 1;
1180
1181 cropStart0.bits.lvds_start_x0_lane = xPerLane;
1182 cropStart0.bits.lvds_start_y0 = pImgRect->y;
1183
1184 cropStart1.bits.lvds_start_x1_lane = xPerLane;
1185 cropStart1.bits.lvds_start_y1 = pImgRect->y;
1186
1187 cropStart2.bits.lvds_start_x2_lane = xPerLane;
1188 cropStart2.bits.lvds_start_y2 = pImgRect->y;
1189
1190 cropStart3.bits.lvds_start_x3_lane = xPerLane;
1191 cropStart3.bits.lvds_start_y3 = pImgRect->y;
1192
1193 ctrlReg->LVDS_IMGSIZE.u32 = lvdsImgSize.u32;
1194 ctrlReg->LVDS_CROP_START0.u32 = cropStart0.u32;
1195 ctrlReg->LVDS_CROP_START1.u32 = cropStart1.u32;
1196 ctrlReg->LVDS_CROP_START2.u32 = cropStart2.u32;
1197 ctrlReg->LVDS_CROP_START3.u32 = cropStart3.u32;
1198 }
1199
MipiRxDrvSetLvdsCropEn(uint8_t devno, int enable)1200 void MipiRxDrvSetLvdsCropEn(uint8_t devno, int enable)
1201 {
1202 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1203 U_LVDS_CTRL lvdsCtrl;
1204
1205 ctrlReg = GetLvdsCtrlRegs(devno);
1206 if (ctrlReg == NULL) {
1207 return;
1208 }
1209
1210 lvdsCtrl.u32 = ctrlReg->LVDS_CTRL.u32;
1211 lvdsCtrl.bits.lvds_crop_en = enable;
1212 ctrlReg->LVDS_CTRL.u32 = lvdsCtrl.u32;
1213 }
1214
MipiRxHalSetLvdsWdrEn(uint8_t devno, WdrMode wdrMode)1215 static int MipiRxHalSetLvdsWdrEn(uint8_t devno, WdrMode wdrMode)
1216 {
1217 int ret = HDF_SUCCESS;
1218 U_LVDS_WDR lvdsWdr;
1219 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1220
1221 ctrlReg = GetLvdsCtrlRegs(devno);
1222 lvdsWdr.u32 = ctrlReg->LVDS_WDR.u32;
1223
1224 if (wdrMode == HI_WDR_MODE_NONE) {
1225 lvdsWdr.bits.lvds_wdr_en = 0;
1226 lvdsWdr.bits.lvds_wdr_num = 0;
1227 } else {
1228 lvdsWdr.bits.lvds_wdr_en = 1;
1229
1230 switch (wdrMode) {
1231 case HI_WDR_MODE_2F:
1232 case HI_WDR_MODE_DOL_2F:
1233 lvdsWdr.bits.lvds_wdr_num = 1; /* 1 -- 2_wdr */
1234 break;
1235
1236 case HI_WDR_MODE_3F:
1237 case HI_WDR_MODE_DOL_3F:
1238 lvdsWdr.bits.lvds_wdr_num = 2; /* 2 -- 3_wdr */
1239 break;
1240
1241 case HI_WDR_MODE_4F:
1242 case HI_WDR_MODE_DOL_4F:
1243 lvdsWdr.bits.lvds_wdr_num = 3; /* 3 -- 4_wdr */
1244 break;
1245
1246 default:
1247 ret = HDF_FAILURE;
1248 HDF_LOGE("%s: not support WDR_MODE: %d", __func__, wdrMode);
1249 break;
1250 }
1251 }
1252
1253 ctrlReg->LVDS_WDR.u32 = lvdsWdr.u32;
1254
1255 return ret;
1256 }
1257
MipiRxHalSetLvdsSofWdr(uint8_t devno, WdrMode wdrMode, const LvdsVsyncAttr *vsyncAttr)1258 static int MipiRxHalSetLvdsSofWdr(uint8_t devno, WdrMode wdrMode,
1259 const LvdsVsyncAttr *vsyncAttr)
1260 {
1261 U_LVDS_WDR lvdsWdr;
1262 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1263
1264 (void)wdrMode;
1265 ctrlReg = GetLvdsCtrlRegs(devno);
1266 lvdsWdr.u32 = ctrlReg->LVDS_WDR.u32;
1267
1268 if (vsyncAttr->syncType == LVDS_VSYNC_NORMAL) {
1269 /* SOF-EOF WDR, long exposure frame and short exposure frame has independent sync code */
1270 lvdsWdr.bits.lvds_wdr_mode = 0x0;
1271 } else if (vsyncAttr->syncType == LVDS_VSYNC_SHARE) {
1272 /* SOF-EOF WDR, long exposure frame and short exposure frame share the SOF and EOF */
1273 lvdsWdr.bits.lvds_wdr_mode = 0x2;
1274 } else {
1275 HDF_LOGE("%s: not support vsync type: %d", __func__, vsyncAttr->syncType);
1276 return HDF_ERR_INVALID_PARAM;
1277 }
1278
1279 ctrlReg->LVDS_WDR.u32 = lvdsWdr.u32;
1280
1281 return HDF_SUCCESS;
1282 }
1283
MipiRxHalSetLvdsDolWdr(uint8_t devno, WdrMode wdrMode, const LvdsVsyncAttr *vsyncAttr, const LvdsFidAttr *fidAttr)1284 static int MipiRxHalSetLvdsDolWdr(uint8_t devno, WdrMode wdrMode,
1285 const LvdsVsyncAttr *vsyncAttr, const LvdsFidAttr *fidAttr)
1286 {
1287 U_LVDS_WDR lvdsWdr;
1288 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1289
1290 (void)wdrMode;
1291 ctrlReg = GetLvdsCtrlRegs(devno);
1292 lvdsWdr.u32 = ctrlReg->LVDS_WDR.u32;
1293
1294 /* Sony DOL WDR */
1295 if (vsyncAttr->syncType == LVDS_VSYNC_NORMAL) {
1296 /*
1297 * SAV-EAV WDR, 4 sync code, fid embedded in 4th sync code
1298 * long exposure fame and short exposure frame has independent sync code
1299 */
1300 if (fidAttr->fidType == LVDS_FID_IN_SAV) {
1301 lvdsWdr.bits.lvds_wdr_mode = 0x4;
1302 } else if (fidAttr->fidType == LVDS_FID_IN_DATA) {
1303 /*
1304 * SAV-EAV WDR, 5 sync code(Line Information), fid in the fist DATA,
1305 * fid in data, line information
1306 */
1307 if (fidAttr->outputFil) {
1308 /* Frame Information Line is included in the image data */
1309 lvdsWdr.bits.lvds_wdr_mode = 0xd;
1310 } else {
1311 /* Frame Information Line is not included in the image data */
1312 lvdsWdr.bits.lvds_wdr_mode = 0x6;
1313 }
1314 } else {
1315 HDF_LOGE("%s: not support fid type: %d", __func__, fidAttr->fidType);
1316 return HDF_ERR_INVALID_PARAM;
1317 }
1318 } else if (vsyncAttr->syncType == LVDS_VSYNC_HCONNECT) {
1319 /*
1320 * SAV-EAV H-Connection DOL, long exposure frame and short exposure frame
1321 * share the same SAV EAV, the H-Blank is assigned by the dol_hblank1 and dol_hblank2
1322 */
1323 if (fidAttr->fidType == LVDS_FID_NONE) {
1324 lvdsWdr.bits.lvds_wdr_mode = 0x5;
1325 } else {
1326 HDF_LOGE("%s: not support fid type: %d", __func__, fidAttr->fidType);
1327 return HDF_ERR_INVALID_PARAM;
1328 }
1329 } else {
1330 HDF_LOGE("%s: not support vsync type: %d", __func__, vsyncAttr->syncType);
1331 return HDF_ERR_INVALID_PARAM;
1332 }
1333
1334 ctrlReg->LVDS_WDR.u32 = lvdsWdr.u32;
1335 return HDF_SUCCESS;
1336 }
1337
MipiRxHalSetLvdsWdrType(uint8_t devno, WdrMode wdrMode, const LvdsVsyncAttr *vsyncAttr, const LvdsFidAttr *fidAttr)1338 static int MipiRxHalSetLvdsWdrType(uint8_t devno, WdrMode wdrMode,
1339 const LvdsVsyncAttr *vsyncAttr, const LvdsFidAttr *fidAttr)
1340 {
1341 int ret = HDF_SUCCESS;
1342
1343 if (wdrMode >= HI_WDR_MODE_2F && wdrMode <= HI_WDR_MODE_4F) {
1344 ret = MipiRxHalSetLvdsSofWdr(devno, wdrMode, vsyncAttr);
1345 } else if (wdrMode >= HI_WDR_MODE_DOL_2F && wdrMode <= HI_WDR_MODE_DOL_4F) {
1346 ret = MipiRxHalSetLvdsDolWdr(devno, wdrMode, vsyncAttr, fidAttr);
1347 } else {
1348 }
1349
1350 return ret;
1351 }
1352
MipiRxHalSetScdHblk(uint8_t devno, WdrMode wdrMode, const LvdsVsyncAttr *vsyncAttr)1353 static void MipiRxHalSetScdHblk(uint8_t devno, WdrMode wdrMode, const LvdsVsyncAttr *vsyncAttr)
1354 {
1355 U_LVDS_DOLSCD_HBLK scdHblk;
1356 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1357
1358 ctrlReg = GetLvdsCtrlRegs(devno);
1359 scdHblk.u32 = ctrlReg->LVDS_DOLSCD_HBLK.u32;
1360
1361 if ((wdrMode >= HI_WDR_MODE_DOL_2F && wdrMode <= HI_WDR_MODE_DOL_4F) &&
1362 (vsyncAttr->syncType == LVDS_VSYNC_HCONNECT)) {
1363 scdHblk.bits.dol_hblank1 = vsyncAttr->hblank1;
1364 scdHblk.bits.dol_hblank2 = vsyncAttr->hblank2;
1365 }
1366
1367 ctrlReg->LVDS_DOLSCD_HBLK.u32 = scdHblk.u32;
1368 }
1369
MipiRxDrvSetLvdsWdrMode(uint8_t devno, WdrMode wdrMode, const LvdsVsyncAttr *vsyncAttr, const LvdsFidAttr *fidAttr)1370 int MipiRxDrvSetLvdsWdrMode(uint8_t devno, WdrMode wdrMode, const LvdsVsyncAttr *vsyncAttr,
1371 const LvdsFidAttr *fidAttr)
1372 {
1373 int ret;
1374
1375 if (wdrMode == HI_WDR_MODE_BUTT) {
1376 HDF_LOGE("%s: not support WDR_MODE: %d", __func__, wdrMode);
1377 return HDF_ERR_NOT_SUPPORT;
1378 }
1379
1380 ret = MipiRxHalSetLvdsWdrEn(devno, wdrMode);
1381 if (ret != HDF_SUCCESS) {
1382 HDF_LOGE("%s: [MipiRxHalSetLvdsWdrEn] failed.", __func__);
1383 return ret;
1384 }
1385
1386 if (wdrMode != HI_WDR_MODE_NONE) {
1387 ret = MipiRxHalSetLvdsWdrType(devno, wdrMode, vsyncAttr, fidAttr);
1388 if (ret != HDF_SUCCESS) {
1389 HDF_LOGE("%s: [MipiRxHalSetLvdsWdrType] failed.", __func__);
1390 return ret;
1391 }
1392
1393 MipiRxHalSetScdHblk(devno, wdrMode, vsyncAttr);
1394 }
1395
1396 return ret;
1397 }
1398
MipiRxDrvSetLvdsCtrlMode(uint8_t devno, LvdsSyncMode syncMode, DataType inputDataType, LvdsBitEndian dataEndian, LvdsBitEndian syncCodeEndian)1399 void MipiRxDrvSetLvdsCtrlMode(uint8_t devno, LvdsSyncMode syncMode, DataType inputDataType,
1400 LvdsBitEndian dataEndian, LvdsBitEndian syncCodeEndian)
1401 {
1402 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1403 U_LVDS_CTRL lvdsCtrl;
1404 unsigned short rawType;
1405
1406 ctrlReg = GetLvdsCtrlRegs(devno);
1407
1408 lvdsCtrl.u32 = ctrlReg->LVDS_CTRL.u32;
1409
1410 switch (inputDataType) {
1411 case DATA_TYPE_RAW_8BIT:
1412 rawType = 0x1;
1413 break;
1414
1415 case DATA_TYPE_RAW_10BIT:
1416 rawType = 0x2;
1417 break;
1418
1419 case DATA_TYPE_RAW_12BIT:
1420 rawType = 0x3;
1421 break;
1422
1423 case DATA_TYPE_RAW_14BIT:
1424 rawType = 0x4;
1425 break;
1426
1427 case DATA_TYPE_RAW_16BIT:
1428 rawType = 0x5;
1429 break;
1430
1431 default:
1432 return;
1433 }
1434
1435 lvdsCtrl.bits.lvds_sync_mode = syncMode;
1436 lvdsCtrl.bits.lvds_raw_type = rawType;
1437 lvdsCtrl.bits.lvds_pix_big_endian = dataEndian;
1438 lvdsCtrl.bits.lvds_code_big_endian = syncCodeEndian;
1439
1440 ctrlReg->LVDS_CTRL.u32 = lvdsCtrl.u32;
1441 }
1442
MipiRxDrvSetLvdsDataRate(uint8_t devno, MipiDataRate dataRate)1443 void MipiRxDrvSetLvdsDataRate(uint8_t devno, MipiDataRate dataRate)
1444 {
1445 U_LVDS_OUTPUT_PIX_NUM lvdsOutputPixelNum;
1446 unsigned int lvdsDoublePixEn = 0;
1447 volatile LvdsCtrlRegsTag *lvdsCtrlRegs = GetLvdsCtrlRegs(devno);
1448
1449 if (dataRate == MIPI_DATA_RATE_X1) {
1450 lvdsDoublePixEn = 0;
1451 } else if (dataRate == MIPI_DATA_RATE_X2) {
1452 lvdsDoublePixEn = 0x1;
1453 } else {
1454 HDF_LOGE("%s: unsupported dataRate:%d devno %hhu", __func__, dataRate, devno);
1455 return;
1456 }
1457
1458 lvdsOutputPixelNum.u32 = lvdsCtrlRegs->LVDS_OUTPUT_PIX_NUM.u32;
1459 lvdsOutputPixelNum.bits.lvds_double_pix_en = lvdsDoublePixEn;
1460 lvdsCtrlRegs->LVDS_OUTPUT_PIX_NUM.u32 = lvdsOutputPixelNum.u32;
1461 }
1462
MipiRxDrvSetDolLineInformation(uint8_t devno, WdrMode wdrMode)1463 void MipiRxDrvSetDolLineInformation(uint8_t devno, WdrMode wdrMode)
1464 {
1465 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1466
1467 ctrlReg = GetLvdsCtrlRegs(devno);
1468
1469 if (wdrMode >= HI_WDR_MODE_DOL_2F) {
1470 ctrlReg->LVDS_LI_WORD0.bits.li_word0_0 = 0x0201;
1471 ctrlReg->LVDS_LI_WORD0.bits.li_word0_1 = 0x0211;
1472 ctrlReg->LVDS_LI_WORD1.bits.li_word1_0 = 0x0202;
1473 ctrlReg->LVDS_LI_WORD1.bits.li_word1_1 = 0x0212;
1474 }
1475
1476 if (wdrMode >= HI_WDR_MODE_DOL_3F) {
1477 ctrlReg->LVDS_LI_WORD2.bits.li_word2_0 = 0x0204;
1478 ctrlReg->LVDS_LI_WORD2.bits.li_word2_1 = 0x0214;
1479 }
1480
1481 if (wdrMode >= HI_WDR_MODE_DOL_4F) {
1482 ctrlReg->LVDS_LI_WORD3.bits.li_word3_0 = 0x0208;
1483 ctrlReg->LVDS_LI_WORD3.bits.li_word3_1 = 0x0218;
1484 }
1485 }
1486
SetLvdsLaneSof(uint8_t devno, int nFrame, int i, const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])1487 static void SetLvdsLaneSof(uint8_t devno, int nFrame, int i,
1488 const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])
1489 {
1490 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1491 volatile LvdsSyncCodeCfgTag *pSyncCode = NULL;
1492
1493 ctrlReg = GetLvdsCtrlRegs(devno);
1494
1495 if (nFrame == TRUE) {
1496 pSyncCode = &ctrlReg->lvds_this_frame_sync_code[i];
1497 } else {
1498 pSyncCode = &ctrlReg->lvds_next_frame_sync_code[i];
1499 }
1500
1501 {
1502 U_LVDS_LANE_SOF_01 lvdsSof01;
1503 lvdsSof01.u32 = pSyncCode->LVDS_LANE_SOF_01.u32;
1504 lvdsSof01.bits.lane_sof_0 = syncCode[i][0][0]; /* 0 -- frame0 sof */
1505 lvdsSof01.bits.lane_sof_1 = syncCode[i][1][0]; /* 1 -- frame1 sof */
1506 pSyncCode->LVDS_LANE_SOF_01.u32 = lvdsSof01.u32;
1507 }
1508 {
1509 U_LVDS_LANE_SOF_23 lvdsSof23;
1510 lvdsSof23.u32 = pSyncCode->LVDS_LANE_SOF_23.u32;
1511 lvdsSof23.bits.lane_sof_2 = syncCode[i][2][0]; /* 2 -- frame2 sof */
1512 lvdsSof23.bits.lane_sof_3 = syncCode[i][3][0]; /* 3 -- frame3 sof */
1513 pSyncCode->LVDS_LANE_SOF_23.u32 = lvdsSof23.u32;
1514 }
1515 }
1516
SetLvdsLaneEof(uint8_t devno, int nFrame, int i, const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])1517 static void SetLvdsLaneEof(uint8_t devno, int nFrame, int i,
1518 const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])
1519 {
1520 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1521 volatile LvdsSyncCodeCfgTag *pSyncCode = NULL;
1522
1523 ctrlReg = GetLvdsCtrlRegs(devno);
1524
1525 if (nFrame == TRUE) {
1526 pSyncCode = &ctrlReg->lvds_this_frame_sync_code[i];
1527 } else {
1528 pSyncCode = &ctrlReg->lvds_next_frame_sync_code[i];
1529 }
1530
1531 {
1532 U_LVDS_LANE_EOF_01 lvdsEof01;
1533 lvdsEof01.u32 = pSyncCode->LVDS_LANE_EOF_01.u32;
1534 lvdsEof01.bits.lane_eof_0 = syncCode[i][0][1]; /* 0 -- frame0 eof */
1535 lvdsEof01.bits.lane_eof_1 = syncCode[i][1][1]; /* 1 -- frame1 eof */
1536 pSyncCode->LVDS_LANE_EOF_01.u32 = lvdsEof01.u32;
1537 }
1538 {
1539 U_LVDS_LANE_EOF_23 lvdsEof23;
1540 lvdsEof23.u32 = pSyncCode->LVDS_LANE_EOF_23.u32;
1541 lvdsEof23.bits.lane_eof_2 = syncCode[i][2][1]; /* 2 -- frame2 eof */
1542 lvdsEof23.bits.lane_eof_3 = syncCode[i][3][1]; /* 3 -- frame3 eof */
1543 pSyncCode->LVDS_LANE_EOF_23.u32 = lvdsEof23.u32;
1544 }
1545 }
1546
SetLvdsLaneSol(uint8_t devno, int nFrame, int i, const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])1547 static void SetLvdsLaneSol(uint8_t devno, int nFrame, int i,
1548 const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])
1549 {
1550 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1551 volatile LvdsSyncCodeCfgTag *pSyncCode = NULL;
1552
1553 ctrlReg = GetLvdsCtrlRegs(devno);
1554
1555 if (nFrame == TRUE) {
1556 pSyncCode = &ctrlReg->lvds_this_frame_sync_code[i];
1557 } else {
1558 pSyncCode = &ctrlReg->lvds_next_frame_sync_code[i];
1559 }
1560
1561 {
1562 U_LVDS_LANE_SOL_01 lvdsSol01;
1563 lvdsSol01.u32 = pSyncCode->LVDS_LANE_SOL_01.u32;
1564 lvdsSol01.bits.lane_sol_0 = syncCode[i][0][2]; /* [0][2] -- frame0 sol bit */
1565 lvdsSol01.bits.lane_sol_1 = syncCode[i][1][2]; /* [1][2] -- frame1 sol bit */
1566 pSyncCode->LVDS_LANE_SOL_01.u32 = lvdsSol01.u32;
1567 }
1568 {
1569 U_LVDS_LANE_SOL_23 lvdsSol23;
1570 lvdsSol23.u32 = pSyncCode->LVDS_LANE_SOL_23.u32;
1571 lvdsSol23.bits.lane_sol_2 = syncCode[i][2][2]; /* [2][2] -- frame2 sol bit */
1572 lvdsSol23.bits.lane_sol_3 = syncCode[i][3][2]; /* [3][2] -- frame3 sol bit */
1573 pSyncCode->LVDS_LANE_SOL_23.u32 = lvdsSol23.u32;
1574 }
1575 }
1576
SetLvdsLaneEol(uint8_t devno, int nFrame, int i, const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])1577 static void SetLvdsLaneEol(uint8_t devno, int nFrame, int i,
1578 const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])
1579 {
1580 volatile LvdsCtrlRegsTag *ctrlReg = NULL;
1581 volatile LvdsSyncCodeCfgTag *pSyncCode = NULL;
1582
1583 ctrlReg = GetLvdsCtrlRegs(devno);
1584
1585 if (nFrame == TRUE) {
1586 pSyncCode = &ctrlReg->lvds_this_frame_sync_code[i];
1587 } else {
1588 pSyncCode = &ctrlReg->lvds_next_frame_sync_code[i];
1589 }
1590
1591 {
1592 U_LVDS_LANE_EOL_01 lvdsEol01;
1593 lvdsEol01.u32 = pSyncCode->LVDS_LANE_EOL_01.u32;
1594 lvdsEol01.bits.lane_eol_0 = syncCode[i][0][3]; /* [0][3] -- frame0 sol */
1595 lvdsEol01.bits.lane_eol_1 = syncCode[i][1][3]; /* [1][3] -- frame1 sol */
1596 pSyncCode->LVDS_LANE_EOL_01.u32 = lvdsEol01.u32;
1597 }
1598 {
1599 U_LVDS_LANE_EOL_23 lvdsEol23;
1600 lvdsEol23.u32 = pSyncCode->LVDS_LANE_EOL_23.u32;
1601 lvdsEol23.bits.lane_eol_2 = syncCode[i][2][3]; /* [2][3] -- frame2 sol */
1602 lvdsEol23.bits.lane_eol_3 = syncCode[i][3][3]; /* [3][3] -- frame3 sol */
1603 pSyncCode->LVDS_LANE_EOL_23.u32 = lvdsEol23.u32;
1604 }
1605 }
1606
SetLvdsSyncCode(uint8_t devno, int nFrame, unsigned int laneCnt, const short laneId[LVDS_LANE_NUM], const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])1607 void SetLvdsSyncCode(uint8_t devno, int nFrame, unsigned int laneCnt,
1608 const short laneId[LVDS_LANE_NUM], const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])
1609 {
1610 int i;
1611
1612 (void)laneCnt;
1613 for (i = 0; i < LVDS_LANE_NUM; i++) {
1614 if (laneId[i] == -1) {
1615 continue;
1616 }
1617
1618 SetLvdsLaneSof(devno, nFrame, i, syncCode);
1619 SetLvdsLaneEof(devno, nFrame, i, syncCode);
1620 SetLvdsLaneSol(devno, nFrame, i, syncCode);
1621 SetLvdsLaneEol(devno, nFrame, i, syncCode);
1622 }
1623 }
1624
MipiRxDrvSetLvdsSyncCode(uint8_t devno, unsigned int laneCnt, const short laneId[LVDS_LANE_NUM], const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])1625 void MipiRxDrvSetLvdsSyncCode(uint8_t devno, unsigned int laneCnt, const short laneId[LVDS_LANE_NUM],
1626 const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])
1627 {
1628 SetLvdsSyncCode(devno, TRUE, laneCnt, laneId, syncCode);
1629 }
1630
MipiRxDrvSetLvdsNxtSyncCode(uint8_t devno, unsigned int laneCnt, const short laneId[LVDS_LANE_NUM], const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])1631 void MipiRxDrvSetLvdsNxtSyncCode(uint8_t devno, unsigned int laneCnt, const short laneId[LVDS_LANE_NUM],
1632 const unsigned short syncCode[][WDR_VC_NUM][SYNC_CODE_NUM])
1633 {
1634 SetLvdsSyncCode(devno, FALSE, laneCnt, laneId, syncCode);
1635 }
1636
MipiRxDrvSetPhySyncDct(unsigned int phyId, int rawType, LvdsBitEndian codeEndian, unsigned int phyLaneBitmap)1637 void MipiRxDrvSetPhySyncDct(unsigned int phyId, int rawType, LvdsBitEndian codeEndian, unsigned int phyLaneBitmap)
1638 {
1639 U_PHY_SYNC_DCT_LINK phySyncDctLink;
1640 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
1641
1642 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
1643 phySyncDctLink.u32 = mipiRxPhyCfg->PHY_SYNC_DCT_LINK.u32;
1644
1645 if (phyLaneBitmap & 0x5) {
1646 phySyncDctLink.bits.cil_raw_type0 = rawType;
1647 phySyncDctLink.bits.cil_code_big_endian0 = codeEndian;
1648 }
1649
1650 if (phyLaneBitmap & 0xa) {
1651 phySyncDctLink.bits.cil_raw_type1 = rawType;
1652 phySyncDctLink.bits.cil_code_big_endian1 = codeEndian;
1653 }
1654
1655 mipiRxPhyCfg->PHY_SYNC_DCT_LINK.u32 = phySyncDctLink.u32;
1656 }
1657
GetSensorLaneIndex(short lane, const short laneId[LVDS_LANE_NUM])1658 short GetSensorLaneIndex(short lane, const short laneId[LVDS_LANE_NUM])
1659 {
1660 int i;
1661
1662 for (i = 0; i < LVDS_LANE_NUM; i++) {
1663 if (laneId[i] == lane) {
1664 break;
1665 }
1666 }
1667
1668 return i;
1669 }
1670
MipiRxDrvSetLvdsPhySyncCode(unsigned int phyId, const short laneId[LVDS_LANE_NUM], const unsigned short nSyncCode[][WDR_VC_NUM][SYNC_CODE_NUM], const unsigned short nxtSyncCode[][WDR_VC_NUM][SYNC_CODE_NUM], unsigned int phyLaneBitmap)1671 void MipiRxDrvSetLvdsPhySyncCode(unsigned int phyId, const short laneId[LVDS_LANE_NUM],
1672 const unsigned short nSyncCode[][WDR_VC_NUM][SYNC_CODE_NUM],
1673 const unsigned short nxtSyncCode[][WDR_VC_NUM][SYNC_CODE_NUM], unsigned int phyLaneBitmap)
1674 {
1675 U_PHY_SYNC_SOF0_LINK phySyncSof0Link;
1676 U_PHY_SYNC_SOF1_LINK phySyncSof1Link;
1677 U_PHY_SYNC_SOF2_LINK phySyncSof2Link;
1678 U_PHY_SYNC_SOF3_LINK phySyncSof3Link;
1679 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
1680 short sensorLaneIdx;
1681 short lane;
1682
1683 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
1684 phySyncSof0Link.u32 = mipiRxPhyCfg->PHY_SYNC_SOF0_LINK.u32;
1685 phySyncSof1Link.u32 = mipiRxPhyCfg->PHY_SYNC_SOF1_LINK.u32;
1686 phySyncSof2Link.u32 = mipiRxPhyCfg->PHY_SYNC_SOF2_LINK.u32;
1687 phySyncSof3Link.u32 = mipiRxPhyCfg->PHY_SYNC_SOF3_LINK.u32;
1688
1689 if (phyLaneBitmap & 0x1) {
1690 lane = 0 + 4 * phyId; /* 4 -- 1 phy have 4 lane */
1691 sensorLaneIdx = GetSensorLaneIndex(lane, laneId);
1692 phySyncSof0Link.bits.cil_sof0_word4_0 = nSyncCode[sensorLaneIdx][0][0];
1693 phySyncSof0Link.bits.cil_sof1_word4_0 = nxtSyncCode[sensorLaneIdx][0][0];
1694 }
1695
1696 if (phyLaneBitmap & 0x2) {
1697 lane = 1 + 4 * phyId; /* 4 -- 1 phy have 4 lane */
1698 sensorLaneIdx = GetSensorLaneIndex(lane, laneId);
1699 phySyncSof1Link.bits.cil_sof0_word4_1 = nSyncCode[sensorLaneIdx][0][0];
1700 phySyncSof1Link.bits.cil_sof1_word4_1 = nxtSyncCode[sensorLaneIdx][0][0];
1701 }
1702
1703 if (phyLaneBitmap & 0x4) {
1704 lane = 2 + 4 * phyId; /* 4 -- 1 phy have 4 lane, 2 -- laneId 2 */
1705 sensorLaneIdx = GetSensorLaneIndex(lane, laneId);
1706 phySyncSof2Link.bits.cil_sof0_word4_2 = nSyncCode[sensorLaneIdx][0][0];
1707 phySyncSof2Link.bits.cil_sof1_word4_2 = nxtSyncCode[sensorLaneIdx][0][0];
1708 }
1709
1710 if (phyLaneBitmap & 0x8) {
1711 lane = 3 + 4 * phyId; /* 4 -- 1 phy have 4 lane, 3 -- laneId 3 */
1712 sensorLaneIdx = GetSensorLaneIndex(lane, laneId);
1713 phySyncSof3Link.bits.cil_sof0_word4_3 = nSyncCode[sensorLaneIdx][0][0];
1714 phySyncSof3Link.bits.cil_sof1_word4_3 = nxtSyncCode[sensorLaneIdx][0][0];
1715 }
1716
1717 mipiRxPhyCfg->PHY_SYNC_SOF0_LINK.u32 = phySyncSof0Link.u32;
1718 mipiRxPhyCfg->PHY_SYNC_SOF1_LINK.u32 = phySyncSof1Link.u32;
1719 mipiRxPhyCfg->PHY_SYNC_SOF2_LINK.u32 = phySyncSof2Link.u32;
1720 mipiRxPhyCfg->PHY_SYNC_SOF3_LINK.u32 = phySyncSof3Link.u32;
1721 }
1722
MipiRxDrvSetPhySyncConfig(const LvdsDevAttr *pAttr, unsigned int laneBitmap, const unsigned short nxtSyncCode[][WDR_VC_NUM][SYNC_CODE_NUM])1723 void MipiRxDrvSetPhySyncConfig(const LvdsDevAttr *pAttr, unsigned int laneBitmap,
1724 const unsigned short nxtSyncCode[][WDR_VC_NUM][SYNC_CODE_NUM])
1725 {
1726 int rawType;
1727 unsigned int i;
1728 unsigned int mask;
1729 unsigned int phyLaneBitmap;
1730
1731 switch (pAttr->inputDataType) {
1732 case DATA_TYPE_RAW_8BIT:
1733 rawType = 0x1;
1734 break;
1735
1736 case DATA_TYPE_RAW_10BIT:
1737 rawType = 0x2;
1738 break;
1739
1740 case DATA_TYPE_RAW_12BIT:
1741 rawType = 0x3;
1742 break;
1743
1744 case DATA_TYPE_RAW_14BIT:
1745 rawType = 0x4;
1746 break;
1747
1748 case DATA_TYPE_RAW_16BIT:
1749 rawType = 0x5;
1750 break;
1751
1752 default:
1753 return;
1754 }
1755
1756 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
1757 mask = 0xf << (4 * i); /* 4 -- 4bit */
1758 if (laneBitmap & mask) {
1759 phyLaneBitmap = (laneBitmap & mask) >> (4 * i); /* 4 -- 4bit */
1760 MipiRxDrvSetPhySyncDct(i, rawType, pAttr->syncCodeEndian, phyLaneBitmap);
1761 MipiRxDrvSetLvdsPhySyncCode(i, pAttr->laneId, pAttr->syncCode, nxtSyncCode, phyLaneBitmap);
1762 }
1763 }
1764 }
1765
MipiRxDrvIsLaneValid(uint8_t devno, short laneId, LaneDivideMode mode)1766 int MipiRxDrvIsLaneValid(uint8_t devno, short laneId, LaneDivideMode mode)
1767 {
1768 int laneValid = 0;
1769
1770 switch (mode) {
1771 case LANE_DIVIDE_MODE_0:
1772 if (devno == 0) {
1773 if (laneId >= 0 && laneId <= 3) { /* 3 -- laneId max value */
1774 laneValid = 1;
1775 }
1776 }
1777 break;
1778
1779 case LANE_DIVIDE_MODE_1:
1780 if ((devno == 0) || (devno == 1)) {
1781 if (laneId >= 0 && laneId <= 3) { /* 3 -- laneId max value */
1782 laneValid = 1;
1783 }
1784 }
1785 break;
1786
1787 default:
1788 break;
1789 }
1790
1791 return laneValid;
1792 }
1793
1794 static void MipiRxDrvHwInit(void);
MipiRxDrvSetHsMode(LaneDivideMode mode)1795 void MipiRxDrvSetHsMode(LaneDivideMode mode)
1796 {
1797 U_HS_MODE_SELECT hsModeSel;
1798 MipiRxSysRegsTag *mipiRxSysRegs = NULL;
1799 int i;
1800
1801 MipiRxDrvHwInit();
1802
1803 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
1804 MipiRxSetPhyRg2121En(i, g_phyMode[mode][i].phy_rg_en_2121);
1805 MipiRxSetPhyRgClk0En(i, g_phyMode[mode][i].phy_rg_clk0_en);
1806 MipiRxSetPhyRgClk1En(i, g_phyMode[mode][i].phy_rg_clk1_en);
1807 MipiRxSetPhyRgLp0ModeEn(i, g_phyMode[mode][i].phy_rg_lp0_mode_en);
1808 MipiRxSetPhyRgLp1ModeEn(i, g_phyMode[mode][i].phy_rg_lp1_mode_en);
1809 }
1810
1811 mipiRxSysRegs = GetMipiRxSysRegs();
1812 hsModeSel.u32 = mipiRxSysRegs->HS_MODE_SELECT.u32;
1813 hsModeSel.bits.hs_mode = mode;
1814 mipiRxSysRegs->HS_MODE_SELECT.u32 = hsModeSel.u32;
1815 }
1816
MipiRxDrvSetMipiIntMask(uint8_t devno)1817 void MipiRxDrvSetMipiIntMask(uint8_t devno)
1818 {
1819 U_MIPI_INT_MSK mipiIntMsk;
1820 volatile MipiRxSysRegsTag *mipiRxSysRegs = GetMipiRxSysRegs();
1821
1822 mipiIntMsk.u32 = mipiRxSysRegs->MIPI_INT_MSK.u32;
1823
1824 if (devno == 0) {
1825 mipiIntMsk.bits.int_chn0_mask = 0x1;
1826 } else if (devno == 1) {
1827 mipiIntMsk.bits.int_chn1_mask = 0x1;
1828 }
1829
1830 mipiRxSysRegs->MIPI_INT_MSK.u32 = mipiIntMsk.u32;
1831 }
1832
MipiRxDrvSetLvdsCtrlIntMask(uint8_t devno, unsigned int mask)1833 void MipiRxDrvSetLvdsCtrlIntMask(uint8_t devno, unsigned int mask)
1834 {
1835 volatile LvdsCtrlRegsTag *lvdsCtrlRegs = GetLvdsCtrlRegs(devno);
1836
1837 lvdsCtrlRegs->LVDS_CTRL_INT_MSK.u32 = mask;
1838 }
1839
MipiRxDrvSetMipiCtrlIntMask(uint8_t devno, unsigned int mask)1840 void MipiRxDrvSetMipiCtrlIntMask(uint8_t devno, unsigned int mask)
1841 {
1842 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
1843
1844 mipiCtrlRegs->MIPI_CTRL_INT_MSK.u32 = mask;
1845 }
1846
MipiRxDrvSetMipiPkt1IntMask(uint8_t devno, unsigned int mask)1847 void MipiRxDrvSetMipiPkt1IntMask(uint8_t devno, unsigned int mask)
1848 {
1849 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
1850
1851 mipiCtrlRegs->MIPI_PKT_INTR_MSK.u32 = mask;
1852 }
1853
MipiRxDrvSetMipiPkt2IntMask(uint8_t devno, unsigned int mask)1854 void MipiRxDrvSetMipiPkt2IntMask(uint8_t devno, unsigned int mask)
1855 {
1856 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
1857
1858 mipiCtrlRegs->MIPI_PKT_INTR2_MSK.u32 = mask;
1859 }
1860
MipiRxDrvSetMipiFrameIntMask(uint8_t devno, unsigned int mask)1861 void MipiRxDrvSetMipiFrameIntMask(uint8_t devno, unsigned int mask)
1862 {
1863 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
1864
1865 mipiCtrlRegs->MIPI_FRAME_INTR_MSK.u32 = mask;
1866 }
1867
MipiRxDrvSetAlignIntMask(uint8_t devno, unsigned int mask)1868 void MipiRxDrvSetAlignIntMask(uint8_t devno, unsigned int mask)
1869 {
1870 volatile LvdsCtrlRegsTag *lvdsCtrlRegs = GetLvdsCtrlRegs(devno);
1871
1872 lvdsCtrlRegs->ALIGN0_INT_MSK.u32 = mask;
1873 lvdsCtrlRegs->CHN_INT_MASK.u32 = 0xf;
1874 }
1875
MipiRxEnableDisableClock(uint8_t comboDev, int enable)1876 void MipiRxEnableDisableClock(uint8_t comboDev, int enable)
1877 {
1878 unsigned long *mipiRxClockAddr = (unsigned long *)OsalIoRemap(MIPI_RX_CRG_ADDR, (unsigned long)0x4);
1879
1880 if (mipiRxClockAddr == 0) {
1881 HDF_LOGE("%s: MipiRx clock ioremap failed!", __func__);
1882 return;
1883 }
1884 SetBit(enable, 1 + comboDev, mipiRxClockAddr);
1885 OsalIoUnmap((void *)mipiRxClockAddr);
1886 }
1887
MipiRxDrvEnableClock(uint8_t comboDev)1888 void MipiRxDrvEnableClock(uint8_t comboDev)
1889 {
1890 MipiRxEnableDisableClock(comboDev, 1);
1891 }
1892
MipiRxDrvDisableClock(uint8_t comboDev)1893 void MipiRxDrvDisableClock(uint8_t comboDev)
1894 {
1895 MipiRxEnableDisableClock(comboDev, 0);
1896 }
1897
SensorEnableDisableClock(uint8_t snsClkSource, int enable)1898 void SensorEnableDisableClock(uint8_t snsClkSource, int enable)
1899 {
1900 unsigned long *sensorClockAddr = NULL;
1901 unsigned offset;
1902
1903 if (snsClkSource == 0) {
1904 offset = 0; /* 0 -- sensor0_cken is bit[0] */
1905 } else if (snsClkSource == 1) {
1906 offset = 6; /* 6 -- sensor1_cken is bit[6] */
1907 } else {
1908 HDF_LOGE("%s: invalid sensor clock source!", __func__);
1909 return;
1910 }
1911
1912 sensorClockAddr = (unsigned long *)OsalIoRemap(SNS_CRG_ADDR, (unsigned long)0x4);
1913 if (sensorClockAddr == 0) {
1914 HDF_LOGE("%s: sensor clock ioremap failed!", __func__);
1915 return;
1916 }
1917 SetBit(enable, offset, sensorClockAddr);
1918 OsalIoUnmap((void *)sensorClockAddr);
1919 }
1920
SensorDrvEnableClock(uint8_t snsClkSource)1921 void SensorDrvEnableClock(uint8_t snsClkSource)
1922 {
1923 SensorEnableDisableClock(snsClkSource, 1);
1924 }
1925
SensorDrvDisableClock(uint8_t snsClkSource)1926 void SensorDrvDisableClock(uint8_t snsClkSource)
1927 {
1928 SensorEnableDisableClock(snsClkSource, 0);
1929 }
1930
MipiRxCoreResetUnreset(uint8_t comboDev, int reset)1931 void MipiRxCoreResetUnreset(uint8_t comboDev, int reset)
1932 {
1933 /* 4 -- mipi_pix0_core_srst_req bit[4] */
1934 SetBit(reset, (comboDev + 4), (unsigned long *)(uintptr_t)g_mipiRxCoreResetAddr);
1935 }
1936
MipiRxDrvCoreReset(uint8_t comboDev)1937 void MipiRxDrvCoreReset(uint8_t comboDev)
1938 {
1939 MipiRxCoreResetUnreset(comboDev, 1);
1940 }
1941
MipiRxDrvCoreUnreset(uint8_t comboDev)1942 void MipiRxDrvCoreUnreset(uint8_t comboDev)
1943 {
1944 MipiRxCoreResetUnreset(comboDev, 0);
1945 }
1946
SensorResetUnreset(uint8_t snsResetSource, int reset)1947 void SensorResetUnreset(uint8_t snsResetSource, int reset)
1948 {
1949 unsigned long *sensorResetAddr = NULL;
1950 unsigned offset;
1951
1952 if (snsResetSource == 0) {
1953 offset = 1; /* 1 -- sensor0_srst_req is bit[1] */
1954 } else if (snsResetSource == 1) {
1955 offset = 7; /* 7 -- sensor1_srst_req is bit[7] */
1956 } else {
1957 HDF_LOGE("%s: invalid sensor reset source!", __func__);
1958 return;
1959 }
1960
1961 sensorResetAddr = (unsigned long *)OsalIoRemap(SNS_CRG_ADDR, (unsigned long)0x4);
1962 if (sensorResetAddr == 0) {
1963 HDF_LOGE("%s: sensor reset ioremap failed!", __func__);
1964 return;
1965 }
1966 SetBit(reset, offset, sensorResetAddr);
1967 OsalIoUnmap((void *)sensorResetAddr);
1968 }
1969
SensorDrvReset(uint8_t snsResetSource)1970 void SensorDrvReset(uint8_t snsResetSource)
1971 {
1972 SensorResetUnreset(snsResetSource, 1);
1973 }
1974
SensorDrvUnreset(uint8_t snsResetSource)1975 void SensorDrvUnreset(uint8_t snsResetSource)
1976 {
1977 SensorResetUnreset(snsResetSource, 0);
1978 }
1979
MipiRxDrvGetMipiImgsizeStatis(uint8_t devno, short vc, ImgSize *pSize)1980 void MipiRxDrvGetMipiImgsizeStatis(uint8_t devno, short vc, ImgSize *pSize)
1981 {
1982 U_MIPI_IMGSIZE0_STATIS mipiImgsize0Statis;
1983 U_MIPI_IMGSIZE1_STATIS mipiImgsize1Statis;
1984 U_MIPI_IMGSIZE2_STATIS mipiImgsize2Statis;
1985 U_MIPI_IMGSIZE3_STATIS mipiImgsize3Statis;
1986
1987 volatile MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
1988
1989 if (vc == 0) { /* 0 -- vc0 */
1990 mipiImgsize0Statis.u32 = mipiCtrlRegs->MIPI_IMGSIZE0_STATIS.u32;
1991 pSize->width = mipiImgsize0Statis.bits.imgwidth_statis_vc0;
1992 pSize->height = mipiImgsize0Statis.bits.imgheight_statis_vc0;
1993 } else if (vc == 1) { /* 1 -- vc1 */
1994 mipiImgsize1Statis.u32 = mipiCtrlRegs->MIPI_IMGSIZE1_STATIS.u32;
1995 pSize->width = mipiImgsize1Statis.bits.imgwidth_statis_vc1;
1996 pSize->height = mipiImgsize1Statis.bits.imgheight_statis_vc1;
1997 } else if (vc == 2) { /* 2 -- vc2 */
1998 mipiImgsize2Statis.u32 = mipiCtrlRegs->MIPI_IMGSIZE2_STATIS.u32;
1999 pSize->width = mipiImgsize2Statis.bits.imgwidth_statis_vc2;
2000 pSize->height = mipiImgsize2Statis.bits.imgheight_statis_vc2;
2001 } else if (vc == 3) { /* 3 -- vc3 */
2002 mipiImgsize3Statis.u32 = mipiCtrlRegs->MIPI_IMGSIZE3_STATIS.u32;
2003 pSize->width = mipiImgsize3Statis.bits.imgwidth_statis_vc3;
2004 pSize->height = mipiImgsize3Statis.bits.imgheight_statis_vc3;
2005 } else {
2006 pSize->width = 0;
2007 pSize->height = 0;
2008 }
2009 }
2010
MipiRxDrvGetLvdsImgsizeStatis(uint8_t devno, short vc, ImgSize *pSize)2011 void MipiRxDrvGetLvdsImgsizeStatis(uint8_t devno, short vc, ImgSize *pSize)
2012 {
2013 U_LVDS_IMGSIZE0_STATIS lvdsImgSize0Statis;
2014 U_LVDS_IMGSIZE1_STATIS lvdsImgSize1Statis;
2015
2016 volatile LvdsCtrlRegsTag *lvdsCtrlRegs = GetLvdsCtrlRegs(devno);
2017
2018 if (vc == 0) {
2019 lvdsImgSize0Statis.u32 = lvdsCtrlRegs->LVDS_IMGSIZE0_STATIS.u32;
2020 pSize->width = lvdsImgSize0Statis.bits.lvds_imgwidth0;
2021 pSize->height = lvdsImgSize0Statis.bits.lvds_imgheight0;
2022 } else if (vc == 1) {
2023 lvdsImgSize1Statis.u32 = lvdsCtrlRegs->LVDS_IMGSIZE1_STATIS.u32;
2024 pSize->width = lvdsImgSize1Statis.bits.lvds_imgwidth1;
2025 pSize->height = lvdsImgSize1Statis.bits.lvds_imgheight1;
2026 }
2027 }
2028
MipiRxDrvGetLvdsLaneImgsizeStatis(uint8_t devno, short lane, ImgSize *pSize)2029 void MipiRxDrvGetLvdsLaneImgsizeStatis(uint8_t devno, short lane, ImgSize *pSize)
2030 {
2031 U_LVDS_LANE_IMGSIZE_STATIS statis;
2032
2033 volatile LvdsCtrlRegsTag *lvdsCtrlRegs = GetLvdsCtrlRegs(devno);
2034
2035 statis.u32 = lvdsCtrlRegs->LVDS_LANE_IMGSIZE_STATIS[lane].u32;
2036 pSize->width = statis.bits.lane_imgwidth + 1;
2037 pSize->height = statis.bits.lane_imgheight;
2038 }
2039
MipiRxPhyCilIntStatis(int phyId)2040 static void MipiRxPhyCilIntStatis(int phyId)
2041 {
2042 unsigned int phyIntStatus;
2043
2044 MipiRxPhyCfgTag *mipiRxPhyCfg = NULL;
2045
2046 mipiRxPhyCfg = GetMipiRxPhyRegs(phyId);
2047 phyIntStatus = mipiRxPhyCfg->MIPI_CIL_INT_LINK.u32;
2048
2049 if (phyIntStatus) {
2050 mipiRxPhyCfg->MIPI_CIL_INT_RAW_LINK.u32 = 0xffffffff;
2051
2052 if (phyIntStatus & MIPI_ESC_CLK1) {
2053 g_phyErrIntCnt[phyId].clk1FsmEscapeErrCnt++;
2054 }
2055
2056 if (phyIntStatus & MIPI_ESC_CLK0) {
2057 g_phyErrIntCnt[phyId].clk0FsmEscapeErrCnt++;
2058 }
2059
2060 if (phyIntStatus & MIPI_ESC_D0) {
2061 g_phyErrIntCnt[phyId].d0FsmEscapeErrCnt++;
2062 }
2063
2064 if (phyIntStatus & MIPI_ESC_D1) {
2065 g_phyErrIntCnt[phyId].d1FsmEscapeErrCnt++;
2066 }
2067
2068 if (phyIntStatus & MIPI_ESC_D2) {
2069 g_phyErrIntCnt[phyId].d2FsmEscapeErrCnt++;
2070 }
2071
2072 if (phyIntStatus & MIPI_ESC_D3) {
2073 g_phyErrIntCnt[phyId].d3FsmEscapeErrCnt++;
2074 }
2075
2076 if (phyIntStatus & MIPI_TIMEOUT_CLK1) {
2077 g_phyErrIntCnt[phyId].clk1FsmTimeoutErrCnt++;
2078 }
2079
2080 if (phyIntStatus & MIPI_TIMEOUT_CLK0) {
2081 g_phyErrIntCnt[phyId].clk0FsmTimeoutErrCnt++;
2082 }
2083
2084 if (phyIntStatus & MIPI_TIMEOUT_D0) {
2085 g_phyErrIntCnt[phyId].d0FsmTimeoutErrCnt++;
2086 }
2087
2088 if (phyIntStatus & MIPI_TIMEOUT_D1) {
2089 g_phyErrIntCnt[phyId].d1FsmTimeoutErrCnt++;
2090 }
2091
2092 if (phyIntStatus & MIPI_TIMEOUT_D2) {
2093 g_phyErrIntCnt[phyId].d2FsmTimeoutErrCnt++;
2094 }
2095
2096 if (phyIntStatus & MIPI_TIMEOUT_D3) {
2097 g_phyErrIntCnt[phyId].d3FsmTimeoutErrCnt++;
2098 }
2099 }
2100 }
2101
MipiRxPktInt1Statics(uint8_t devno)2102 static void MipiRxPktInt1Statics(uint8_t devno)
2103 {
2104 unsigned int pktInt1;
2105 MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
2106
2107 pktInt1 = mipiCtrlRegs->MIPI_PKT_INTR_ST.u32;
2108 if (pktInt1) {
2109 if (pktInt1 & MIPI_PKT_HEADER_ERR) {
2110 g_mipiErrIntCnt[devno].errEccDoubleCnt++;
2111 }
2112
2113 if (pktInt1 & MIPI_VC0_PKT_DATA_CRC) {
2114 g_mipiErrIntCnt[devno].vc0ErrCrcCnt++;
2115 }
2116
2117 if (pktInt1 & MIPI_VC1_PKT_DATA_CRC) {
2118 g_mipiErrIntCnt[devno].vc1ErrCrcCnt++;
2119 }
2120
2121 if (pktInt1 & MIPI_VC2_PKT_DATA_CRC) {
2122 g_mipiErrIntCnt[devno].vc2ErrCrcCnt++;
2123 }
2124
2125 if (pktInt1 & MIPI_VC3_PKT_DATA_CRC) {
2126 g_mipiErrIntCnt[devno].vc3ErrCrcCnt++;
2127 }
2128 }
2129 }
2130
MipiRxPktInt2Statics(uint8_t devno)2131 static void MipiRxPktInt2Statics(uint8_t devno)
2132 {
2133 unsigned int pktInt2;
2134 MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
2135
2136 pktInt2 = mipiCtrlRegs->MIPI_PKT_INTR2_ST.u32;
2137 if (pktInt2) {
2138 if (pktInt2 & MIPI_VC0_PKT_INVALID_DT) {
2139 g_mipiErrIntCnt[devno].errIdVc0Cnt++;
2140 }
2141
2142 if (pktInt2 & MIPI_VC1_PKT_INVALID_DT) {
2143 g_mipiErrIntCnt[devno].errIdVc1Cnt++;
2144 }
2145
2146 if (pktInt2 & MIPI_VC2_PKT_INVALID_DT) {
2147 g_mipiErrIntCnt[devno].errIdVc2Cnt++;
2148 }
2149
2150 if (pktInt2 & MIPI_VC3_PKT_INVALID_DT) {
2151 g_mipiErrIntCnt[devno].errIdVc3Cnt++;
2152 }
2153
2154 if (pktInt2 & MIPI_VC0_PKT_HEADER_ECC) {
2155 g_mipiErrIntCnt[devno].vc0ErrEccCorrectedCnt++;
2156 }
2157
2158 if (pktInt2 & MIPI_VC1_PKT_HEADER_ECC) {
2159 g_mipiErrIntCnt[devno].vc1ErrEccCorrectedCnt++;
2160 }
2161
2162 if (pktInt2 & MIPI_VC2_PKT_HEADER_ECC) {
2163 g_mipiErrIntCnt[devno].vc2ErrEccCorrectedCnt++;
2164 }
2165
2166 if (pktInt2 & MIPI_VC3_PKT_HEADER_ECC) {
2167 g_mipiErrIntCnt[devno].vc3ErrEccCorrectedCnt++;
2168 }
2169 }
2170 }
2171
MipiRxFrameIntrStatics(uint8_t devno)2172 static void MipiRxFrameIntrStatics(uint8_t devno)
2173 {
2174 unsigned int frameInt;
2175 MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
2176
2177 frameInt = mipiCtrlRegs->MIPI_FRAME_INTR_ST.u32;
2178 if (frameInt) {
2179 if (frameInt & MIPI_VC0_FRAME_CRC) {
2180 g_mipiErrIntCnt[devno].errFrameDataVc0Cnt++;
2181 }
2182
2183 if (frameInt & MIPI_VC1_FRAME_CRC) {
2184 g_mipiErrIntCnt[devno].errFrameDataVc1Cnt++;
2185 }
2186
2187 if (frameInt & MIPI_VC2_FRAME_CRC) {
2188 g_mipiErrIntCnt[devno].errFrameDataVc2Cnt++;
2189 }
2190
2191 if (frameInt & MIPI_VC3_FRAME_CRC) {
2192 g_mipiErrIntCnt[devno].errFrameDataVc3Cnt++;
2193 }
2194
2195 if (frameInt & MIPI_VC0_ORDER_ERR) {
2196 g_mipiErrIntCnt[devno].errFSeqVc0Cnt++;
2197 }
2198
2199 if (frameInt & MIPI_VC1_ORDER_ERR) {
2200 g_mipiErrIntCnt[devno].errFSeqVc1Cnt++;
2201 }
2202
2203 if (frameInt & MIPI_VC2_ORDER_ERR) {
2204 g_mipiErrIntCnt[devno].errFSeqVc2Cnt++;
2205 }
2206
2207 if (frameInt & MIPI_VC3_ORDER_ERR) {
2208 g_mipiErrIntCnt[devno].errFSeqVc3Cnt++;
2209 }
2210
2211 if (frameInt & MIPI_VC0_NO_MATCH) {
2212 g_mipiErrIntCnt[devno].errFBndryMatchVc0Cnt++;
2213 }
2214
2215 if (frameInt & MIPI_VC1_NO_MATCH) {
2216 g_mipiErrIntCnt[devno].errFBndryMatchVc1Cnt++;
2217 }
2218
2219 if (frameInt & MIPI_VC2_NO_MATCH) {
2220 g_mipiErrIntCnt[devno].errFBndryMatchVc2Cnt++;
2221 }
2222
2223 if (frameInt & MIPI_VC3_NO_MATCH) {
2224 g_mipiErrIntCnt[devno].errFBndryMatchVc3Cnt++;
2225 }
2226 }
2227 }
2228
MipiRxMainIntStatics(uint8_t devno)2229 static void MipiRxMainIntStatics(uint8_t devno)
2230 {
2231 unsigned int lineInt;
2232 unsigned int mipiMainInt;
2233 unsigned int mipiCtrlInt;
2234 MipiCtrlRegsTag *mipiCtrlRegs = GetMipiCtrlRegs(devno);
2235
2236 mipiCtrlInt = mipiCtrlRegs->MIPI_CTRL_INT.u32;
2237
2238 /* Need read mipiMainInt and lineInt, to clear MIPI_MAIN_INT_ST and MIPI_LINE_INTR_ST interrupt. */
2239 mipiMainInt = mipiCtrlRegs->MIPI_MAIN_INT_ST.u32;
2240 lineInt = mipiCtrlRegs->MIPI_LINE_INTR_ST.u32;
2241
2242 if (mipiMainInt) {
2243 mipiCtrlRegs->MIPI_MAIN_INT_ST.u32 = 0xffffffff;
2244 }
2245
2246 if (lineInt) {
2247 mipiCtrlRegs->MIPI_LINE_INTR_ST.u32 = 0xffffffff;
2248 }
2249
2250 if (mipiCtrlInt) {
2251 mipiCtrlRegs->MIPI_CTRL_INT_RAW.u32 = 0xffffffff;
2252 }
2253
2254 if (mipiCtrlInt) {
2255 if (mipiCtrlInt & CMD_FIFO_READ_ERR) {
2256 g_mipiErrIntCnt[devno].cmdFifoRderrCnt++;
2257 }
2258
2259 if (mipiCtrlInt & DATA_FIFO_READ_ERR) {
2260 g_mipiErrIntCnt[devno].dataFifoRderrCnt++;
2261 }
2262
2263 if (mipiCtrlInt & CMD_FIFO_WRITE_ERR) {
2264 g_mipiErrIntCnt[devno].cmdFifoWrerrCnt++;
2265 }
2266
2267 if (mipiCtrlInt & DATA_FIFO_WRITE_ERR) {
2268 g_mipiErrIntCnt[devno].dataFifoWrerrCnt++;
2269 }
2270 }
2271 }
2272
MipiIntStatics(uint8_t devno)2273 static void MipiIntStatics(uint8_t devno)
2274 {
2275 MipiRxMainIntStatics(devno);
2276 MipiRxPktInt1Statics(devno);
2277 MipiRxPktInt2Statics(devno);
2278 MipiRxFrameIntrStatics(devno);
2279 }
2280
LvdsIntStatics(uint8_t devno)2281 static void LvdsIntStatics(uint8_t devno)
2282 {
2283 unsigned int lvdsCtrlInt;
2284 volatile LvdsCtrlRegsTag *lvdsCtrlRegs = GetLvdsCtrlRegs(devno);
2285
2286 lvdsCtrlInt = lvdsCtrlRegs->LVDS_CTRL_INT.u32;
2287
2288 if (lvdsCtrlInt) {
2289 lvdsCtrlRegs->LVDS_CTRL_INT_RAW.u32 = 0xffffffff;
2290 }
2291
2292 if (lvdsCtrlInt & CMD_RD_ERR) {
2293 g_lvdsErrIntCnt[devno].cmdRdErrCnt++;
2294 }
2295
2296 if (lvdsCtrlInt & CMD_WR_ERR) {
2297 g_lvdsErrIntCnt[devno].cmdWrErrCnt++;
2298 }
2299
2300 if (lvdsCtrlInt & LVDS_POP_ERR) {
2301 g_lvdsErrIntCnt[devno].popErrCnt++;
2302 }
2303
2304 if (lvdsCtrlInt & LVDS_STAT_ERR) {
2305 g_lvdsErrIntCnt[devno].lvdsStateErrCnt++;
2306 }
2307
2308 if (lvdsCtrlInt & LINK0_READ_ERR) {
2309 g_lvdsErrIntCnt[devno].link0RdErrCnt++;
2310 }
2311
2312 if (lvdsCtrlInt & LINK0_WRITE_ERR) {
2313 g_lvdsErrIntCnt[devno].link0WrErrCnt++;
2314 }
2315 }
2316
AlignIntStatis(uint8_t devno)2317 static void AlignIntStatis(uint8_t devno)
2318 {
2319 unsigned int alignInt;
2320 volatile LvdsCtrlRegsTag *lvdsCtrlRegs = GetLvdsCtrlRegs(devno);
2321
2322 alignInt = lvdsCtrlRegs->ALIGN0_INT.u32;
2323
2324 if (alignInt) {
2325 lvdsCtrlRegs->ALIGN0_INT_RAW.u32 = 0xffffffff;
2326 }
2327
2328 if (alignInt & ALIGN_FIFO_FULL_ERR) {
2329 g_alignErrIntCnt[devno].fifoFullErrCnt++;
2330 }
2331
2332 if (alignInt & ALIGN_LANE0_ERR) {
2333 g_alignErrIntCnt[devno].lane0AlignErrCnt++;
2334 }
2335
2336 if (alignInt & ALIGN_LANE1_ERR) {
2337 g_alignErrIntCnt[devno].lane1AlignErrCnt++;
2338 }
2339
2340 if (alignInt & ALIGN_LANE2_ERR) {
2341 g_alignErrIntCnt[devno].lane2AlignErrCnt++;
2342 }
2343
2344 if (alignInt & ALIGN_LANE3_ERR) {
2345 g_alignErrIntCnt[devno].lane3AlignErrCnt++;
2346 }
2347 }
2348
MipiRxInterruptRoute(uint32_t irq, void *devId)2349 static uint32_t MipiRxInterruptRoute(uint32_t irq, void *devId)
2350 {
2351 volatile MipiRxSysRegsTag *mipiRxSysRegs = GetMipiRxSysRegs();
2352 volatile LvdsCtrlRegsTag *lvdsCtrlRegs = NULL;
2353 int i;
2354
2355 (void)irq;
2356 (void)devId;
2357 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; i++) {
2358 MipiRxPhyCilIntStatis(i);
2359 }
2360
2361 for (i = 0; i < MIPI_RX_MAX_DEV_NUM; i++) {
2362 lvdsCtrlRegs = GetLvdsCtrlRegs(i);
2363 if (lvdsCtrlRegs->CHN_INT_RAW.u32) {
2364 MipiRxDrvCoreReset(i);
2365 MipiRxDrvCoreUnreset(i);
2366 } else {
2367 continue;
2368 }
2369
2370 MipiIntStatics(i);
2371 LvdsIntStatics(i);
2372 AlignIntStatis(i);
2373 lvdsCtrlRegs->CHN_INT_RAW.u32 = 0xf;
2374 }
2375
2376 mipiRxSysRegs->MIPI_INT_RAW.u32 = 0xff;
2377
2378 return HDF_SUCCESS;
2379 }
2380
MipiRxDrvRegInit(void)2381 static int MipiRxDrvRegInit(void)
2382 {
2383 if (g_mipiRxRegsVa == NULL) {
2384 g_mipiRxRegsVa = (MipiRxRegsTypeTag *)OsalIoRemap(MIPI_RX_REGS_ADDR, (unsigned int)MIPI_RX_REGS_SIZE);
2385 if (g_mipiRxRegsVa == NULL) {
2386 HDF_LOGE("%s: remap mipi_rx reg addr fail", __func__);
2387 return -1;
2388 }
2389 g_regMapFlag = 1;
2390 }
2391
2392 return 0;
2393 }
2394
MipiRxDrvRegExit(void)2395 static void MipiRxDrvRegExit(void)
2396 {
2397 if (g_regMapFlag == 1) {
2398 if (g_mipiRxRegsVa != NULL) {
2399 OsalIoUnmap((void *)g_mipiRxRegsVa);
2400 g_mipiRxRegsVa = NULL;
2401 }
2402 g_regMapFlag = 0;
2403 }
2404 }
2405
MipiRxRegisterIrq(void)2406 static int MipiRxRegisterIrq(void)
2407 {
2408 int ret;
2409
2410 // This function needs to be verified.
2411 ret = OsalRegisterIrq(g_mipiRxIrqNum, 0, MipiRxInterruptRoute, "MIPI_RX", NULL);
2412 if (ret < 0) {
2413 HDF_LOGE("%s: MipiRx: failed to register irq.", __func__);
2414 return -1;
2415 }
2416
2417 return 0;
2418 }
2419
MipiRxUnregisterIrq(void)2420 static void MipiRxUnregisterIrq(void)
2421 {
2422 OsalUnregisterIrq(g_mipiRxIrqNum, MipiRxInterruptRoute);
2423 }
2424
MipiRxDrvHwInit(void)2425 static void MipiRxDrvHwInit(void)
2426 {
2427 unsigned long *mipiRxCrgAddr = (unsigned long *)OsalIoRemap(MIPI_RX_CRG_ADDR, (unsigned long)0x4);
2428 int i;
2429
2430 WriteReg32(mipiRxCrgAddr, 1 << 0, 0x1 << 0); /* 0 -- cil_cken bit[0] */
2431 WriteReg32(mipiRxCrgAddr, 1 << 3, 0x1 << 3); /* 3 -- mipi_bus_cken bit[3] */
2432 WriteReg32(mipiRxCrgAddr, 1 << 6, 0x1 << 6); /* 6 -- mipi_bus_srst_req bit[6] */
2433 OsalUDelay(10); /* 10 -- udelay 10ns */
2434 WriteReg32(mipiRxCrgAddr, 0, 0x1 << 6); /* 6 -- mipi_bus_srst_req bit[6] */
2435
2436 OsalIoUnmap((void *)mipiRxCrgAddr);
2437
2438 for (i = 0; i < MIPI_RX_MAX_PHY_NUM; ++i) {
2439 MipiRxSetCilIntMask(i, MIPI_CIL_INT_MASK);
2440 MipiRxSetPhySkewLink(i, SKEW_LINK);
2441 MipiRxSetPhyFsmoLink(i, MIPI_FSMO_VALUE);
2442 }
2443 }
2444
MipiRxDrvHwExit(void)2445 static void MipiRxDrvHwExit(void)
2446 {
2447 unsigned long *mipiRxCrgAddr = (unsigned long *)OsalIoRemap(MIPI_RX_CRG_ADDR, (unsigned long)0x4);
2448
2449 WriteReg32(mipiRxCrgAddr, 1 << 6, 0x1 << 6); /* 6 -- mipi_bus_srst_req bit[6] */
2450 WriteReg32(mipiRxCrgAddr, 0, 0x1 << 0); /* 0 -- cil_cken bit[0] */
2451 WriteReg32(mipiRxCrgAddr, 0, 0x1 << 3); /* 3 -- mipi_bus_cken bit[3] */
2452
2453 OsalIoUnmap((void *)mipiRxCrgAddr);
2454 }
2455
MipiRxDrvInit(void)2456 int MipiRxDrvInit(void)
2457 {
2458 int ret;
2459
2460 ret = MipiRxDrvRegInit();
2461 if (ret < 0) {
2462 HDF_LOGE("%s: MipiRxDrvRegInit fail!", __func__);
2463 goto fail0;
2464 }
2465
2466 ret = MipiRxRegisterIrq();
2467 if (ret < 0) {
2468 HDF_LOGE("%s: MipiRxRegisterIrq fail!", __func__);
2469 goto fail1;
2470 }
2471
2472 g_mipiRxCoreResetAddr = (unsigned long)(uintptr_t)OsalIoRemap(MIPI_RX_CRG_ADDR, (unsigned long)0x4);
2473 if (g_mipiRxCoreResetAddr == 0) {
2474 HDF_LOGE("%s: MipiRx reset ioremap failed!", __func__);
2475 goto fail2;
2476 }
2477
2478 MipiRxDrvHwInit();
2479
2480 return HDF_SUCCESS;
2481
2482 fail2:
2483 MipiRxUnregisterIrq();
2484 fail1:
2485 MipiRxDrvRegExit();
2486 fail0:
2487 return HDF_FAILURE;
2488 }
2489
MipiRxDrvExit(void)2490 void MipiRxDrvExit(void)
2491 {
2492 MipiRxUnregisterIrq();
2493 MipiRxDrvRegExit();
2494 MipiRxDrvHwExit();
2495 OsalIoUnmap((void *)(uintptr_t)g_mipiRxCoreResetAddr);
2496 }
2497
2498 #ifdef __cplusplus
2499 #if __cplusplus
2500 }
2501
2502 #endif
2503 #endif /* End of #ifdef __cplusplus */
2504