Home
last modified time | relevance | path

Searched refs:base (Results 1 - 25 of 350) sorted by relevance

12345678910>>...14

/device/qemu/riscv32_virt/liteos_m/board/driver/
H A Dvirtmmio.c26 return GET_UINT32(dev->base + VIRTMMIO_REG_STATUS); in VirtioGetStatus()
31 FENCE_WRITE_UINT32(VirtioGetStatus(dev) | val, dev->base + VIRTMMIO_REG_STATUS); in VirtioAddStatus()
36 FENCE_WRITE_UINT32(VIRTIO_STATUS_RESET, dev->base + VIRTMMIO_REG_STATUS); in VirtioResetStatus()
41 VADDR_T base; in VirtmmioDiscover() local
44 base = IO_DEVICE_ADDR(VIRTMMIO_BASE_ADDR) + VIRTMMIO_BASE_SIZE * (NUM_VIRTIO_TRANSPORTS - 1); in VirtmmioDiscover()
46 if ((GET_UINT32(base + VIRTMMIO_REG_MAGICVALUE) == VIRTMMIO_MAGIC) && in VirtmmioDiscover()
47 (GET_UINT32(base + VIRTMMIO_REG_VERSION) == VIRTMMIO_VERSION) && in VirtmmioDiscover()
48 (GET_UINT32(base + VIRTMMIO_REG_DEVICEID) == devId)) { in VirtmmioDiscover()
49 dev->base = base; in VirtmmioDiscover()
171 CalculateQueueAddr(VADDR_T base, uint16_t qsz, struct Virtq *q) CalculateQueueAddr() argument
184 VirtmmioConfigQueue(struct VirtmmioDev *dev, VADDR_T base, uint16_t qsz[], int num) VirtmmioConfigQueue() argument
[all...]
/device/qemu/drivers/virtio/
H A Dvirtmmio.c21 return GET_UINT32(dev->base + VIRTMMIO_REG_STATUS); in VirtioGetStatus()
26 WRITE_UINT32(VirtioGetStatus(dev) | val, dev->base + VIRTMMIO_REG_STATUS); in VirtioAddStatus()
31 WRITE_UINT32(VIRTIO_STATUS_RESET, dev->base + VIRTMMIO_REG_STATUS); in VirtioResetStatus()
36 VADDR_T base; in VirtmmioDiscover() local
39 base = IO_DEVICE_ADDR(VIRTMMIO_BASE_ADDR) + VIRTMMIO_BASE_SIZE * (NUM_VIRTIO_TRANSPORTS - 1); in VirtmmioDiscover()
41 if ((GET_UINT32(base + VIRTMMIO_REG_MAGICVALUE) == VIRTMMIO_MAGIC) && in VirtmmioDiscover()
42 (GET_UINT32(base + VIRTMMIO_REG_VERSION) == VIRTMMIO_VERSION) && in VirtmmioDiscover()
43 (GET_UINT32(base + VIRTMMIO_REG_DEVICEID) == devId)) { in VirtmmioDiscover()
44 dev->base = base; in VirtmmioDiscover()
163 CalculateQueueAddr(VADDR_T base, uint16_t qsz, struct Virtq *q) CalculateQueueAddr() argument
176 VirtmmioConfigQueue(struct VirtmmioDev *dev, VADDR_T base, uint16_t qsz[], int num) VirtmmioConfigQueue() argument
[all...]
/device/soc/rockchip/rk2206/sdk_liteos/platform/system/
H A Dsystem.c68 const char *_parse_integer_fixup_radix(const char *str, unsigned int *base) in _parse_integer_fixup_radix() argument
72 if (*base == BASE_0) { in _parse_integer_fixup_radix()
75 *base = BASE_16; in _parse_integer_fixup_radix()
77 *base = BASE_8; in _parse_integer_fixup_radix()
80 *base = BASE_10; in _parse_integer_fixup_radix()
83 if (*base == BASE_16 && s[INDEX_0] == '0' && tolower_re(s[INDEX_1]) == 'x') { in _parse_integer_fixup_radix()
89 unsigned int _parse_integer(const char *str, unsigned int base, unsigned long long *p) in _parse_integer() argument
109 if (val >= base) { in _parse_integer()
114 * it in the max base we support (16) in _parse_integer()
117 if (res > div_u64(ULLONG_MAX - val, base)) { in _parse_integer()
152 simple_strtoull(const char *cp_temp, char **endp, unsigned int base) simple_strtoull() argument
178 simple_strtoul(const char *cp, char **endp, unsigned int base) simple_strtoul() argument
189 simple_strtoll(const char *cp, char **endp, unsigned int base) simple_strtoll() argument
197 simple_strtol(const char *cp, char **endp, unsigned int base) simple_strtol() argument
218 unsigned char base; pre_vsscanf() local
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/nvmem/
H A Drockchip-efuse.c98 void __iomem *base; member
105 static void rk1808_efuse_timing_init(void __iomem *base) in rk1808_efuse_timing_init() argument
108 writel(readl(base + RK1808_MOD) & (~RK1808_USER_MODE), base + RK1808_MOD); in rk1808_efuse_timing_init()
111 writel((T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P); in rk1808_efuse_timing_init()
112 writel((T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P); in rk1808_efuse_timing_init()
113 writel((T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P); in rk1808_efuse_timing_init()
114 writel((T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P); in rk1808_efuse_timing_init()
115 writel((T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P); in rk1808_efuse_timing_init()
116 writel((T_CSB_R_S << 16) | T_CSB_R_L, base in rk1808_efuse_timing_init()
123 rk1808_efuse_timing_deinit(void __iomem *base) rk1808_efuse_timing_deinit() argument
[all...]
H A Drockchip-otp.c62 void __iomem *base; member
105 ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status, (status & flag), 1, OTPC_TIMEOUT); in rockchip_otp_wait_status()
111 writel(flag, otp->base + OTPC_INT_STATUS); in rockchip_otp_wait_status()
120 writel(SBPI_DAP_ADDR_MASK | (SBPI_DAP_ADDR << SBPI_DAP_ADDR_SHIFT), otp->base + OTPC_SBPI_CTRL); in rockchip_otp_ecc_enable()
122 writel(SBPI_CMD_VALID_MASK | 0x1, otp->base + OTPC_SBPI_CMD_VALID_PRE); in rockchip_otp_ecc_enable()
123 writel(SBPI_DAP_CMD_WRF | SBPI_DAP_REG_ECC, otp->base + OTPC_SBPI_CMD0_OFFSET); in rockchip_otp_ecc_enable()
125 writel(SBPI_ECC_ENABLE, otp->base + OTPC_SBPI_CMD1_OFFSET); in rockchip_otp_ecc_enable()
127 writel(SBPI_ECC_DISABLE, otp->base + OTPC_SBPI_CMD1_OFFSET); in rockchip_otp_ecc_enable()
130 writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL); in rockchip_otp_ecc_enable()
164 writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base in rockchip_otp_read()
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/linux/
H A Dmali_osk_mali.c76 /* {.description = "Mali_GP", .base = MALI_OFFSET_GP, .irq_name = "IRQGP",}, */
77 {.description = "Mali_GP", .base = MALI_OFFSET_GP, .irq_name = "Mali_GP_IRQ",},
78 /* {.description = "Mali_GP_MMU", .base = MALI_OFFSET_GP_MMU, .irq_name = "IRQGPMMU",}, */
79 {.description = "Mali_GP_MMU", .base = MALI_OFFSET_GP_MMU, .irq_name = "Mali_GP_MMU_IRQ",},
80 /* {.description = "Mali_PP0", .base = MALI_OFFSET_PP0, .irq_name = "IRQPP0",}, */
81 {.description = "Mali_PP0", .base = MALI_OFFSET_PP0, .irq_name = "Mali_PP0_IRQ",},
82 /* {.description = "Mali_PP0_MMU", .base = MALI_OFFSET_PP0_MMU, .irq_name = "IRQPPMMU0",}, */
83 {.description = "Mali_PP0_MMU", .base = MALI_OFFSET_PP0_MMU, .irq_name = "Mali_PP0_MMU_IRQ",},
84 /* {.description = "Mali_PP1", .base = MALI_OFFSET_PP1, .irq_name = "IRQPP1",}, */
85 {.description = "Mali_PP1", .base
[all...]
/device/soc/rockchip/common/vendor/drivers/rockchip/
H A Drockchip-cpuinfo.c131 void __iomem *base; in rk3288_init() local
135 base = ioremap(RK3288_HDMI_PHYS, SZ_4K); in rk3288_init()
136 if (base) { in rk3288_init()
138 if (readl_relaxed(base + 0x4) == 0x1A) { in rk3288_init()
141 iounmap(base); in rk3288_init()
147 void __iomem *base; in rk3126_init() local
153 base = ioremap(RK312X_GRF_PHYS, SZ_4K); in rk3126_init()
154 if (base) { in rk3126_init()
155 if (readl_relaxed(base + RK312X_GRF_CHIP_TAG) == 0x3136) { in rk3126_init()
156 if (readl_relaxed(base in rk3126_init()
168 void __iomem *base; rk3308_init() local
187 void __iomem *base; rk356x_set_cpu_version() local
[all...]
H A Drockchip_debug.c88 void IO_MEM *base; in rockchip_debug_dump_edpcsr() local
92 base = rockchip_cpu_debug[i]; in rockchip_debug_dump_edpcsr()
94 pu = (u32)readl(base + EDPRSR) & EDPRSR_PU; in rockchip_debug_dump_edpcsr()
100 writel(EDLAR_UNLOCK, base + EDLAR); in rockchip_debug_dump_edpcsr()
107 edpcsr = ((u64)readl(base + EDPCSR_LO)) | ((u64)readl(base + EDPCSR_HI) << 0x20); in rockchip_debug_dump_edpcsr()
109 edpcsr = (u32)readl(base + EDPCSR_LO); in rockchip_debug_dump_edpcsr()
138 void IO_MEM *base; in rockchip_debug_dump_pmpcsr() local
141 base = rockchip_cs_pmu[i]; in rockchip_debug_dump_pmpcsr()
147 pmpcsr = ((u64)readl(base in rockchip_debug_dump_pmpcsr()
204 void IO_MEM *base; rockchip_panic_notify_edpcsr() local
261 void IO_MEM *base; rockchip_panic_notify_pmpcsr() local
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/
H A Drockchip-cpuinfo.c123 void __iomem *base; in rk3288_init() local
127 base = ioremap(RK3288_HDMI_PHYS, SZ_4K); in rk3288_init()
128 if (base) { in rk3288_init()
130 if (readl_relaxed(base + 4) == 0x1A) in rk3288_init()
132 iounmap(base); in rk3288_init()
138 void __iomem *base; in rk3126_init() local
144 base = ioremap(RK312X_GRF_PHYS, SZ_4K); in rk3126_init()
145 if (base) { in rk3126_init()
146 if (readl_relaxed(base + RK312X_GRF_CHIP_TAG) == 0x3136) { in rk3126_init()
147 if (readl_relaxed(base in rk3126_init()
158 void __iomem *base; rk3308_init() local
176 void __iomem *base; rk356x_set_cpu_version() local
[all...]
H A Drockchip_debug.c88 void __iomem *base; in rockchip_debug_dump_edpcsr() local
92 base = rockchip_cpu_debug[i]; in rockchip_debug_dump_edpcsr()
94 pu = (u32)readl(base + EDPRSR) & EDPRSR_PU; in rockchip_debug_dump_edpcsr()
101 writel(EDLAR_UNLOCK, base + EDLAR); in rockchip_debug_dump_edpcsr()
110 edpcsr = ((u64)readl(base + EDPCSR_LO)) | in rockchip_debug_dump_edpcsr()
111 ((u64)readl(base + EDPCSR_HI) << 32); in rockchip_debug_dump_edpcsr()
113 edpcsr = (u32)readl(base + EDPCSR_LO); in rockchip_debug_dump_edpcsr()
142 void __iomem *base; in rockchip_debug_dump_pmpcsr() local
145 base = rockchip_cs_pmu[i]; in rockchip_debug_dump_pmpcsr()
153 pmpcsr = ((u64)readl(base in rockchip_debug_dump_pmpcsr()
211 void __iomem *base; rockchip_panic_notify_edpcsr() local
271 void __iomem *base; rockchip_panic_notify_pmpcsr() local
[all...]
/device/qemu/arm_virt/liteos_a_mini/board/amba_pl011/
H A Damba_pl011.c47 #define UARTREG(base, reg) (*REG32((base) + (reg)))
50 STATIC VOID UartPutcReg(UINTPTR base, CHAR c) in UartPutcReg() argument
53 while (UARTREG(base, UART_FR) & UART_FR_TXFF) {} in UartPutcReg()
54 UARTREG(base, UART_DR) = c; in UartPutcReg()
65 UINTPTR base = uart_to_ptr((UINT32)port); in uart_putc() local
66 UartPutcReg(base, c); in uart_putc()
85 STATIC VOID UartPutStr(UINTPTR base, const CHAR *s, UINT32 len) in UartPutStr() argument
91 UartPutcReg(base, '\r'); in UartPutStr()
93 UartPutcReg(base, *( in UartPutStr()
97 UartPutsReg(UINTPTR base, const CHAR *s, UINT32 len, BOOL isLock) UartPutsReg() argument
118 UINTPTR base = uart_to_ptr(0); UartPuts() local
143 UINTPTR base = uart_to_ptr(0); uart_handler() local
[all...]
/device/qemu/arm_virt/liteos_a/board/amba_pl011/
H A Damba_pl011.c47 #define UARTREG(base, reg) (*REG32((base) + (reg)))
50 STATIC VOID UartPutcReg(UINTPTR base, CHAR c) in UartPutcReg() argument
53 while (UARTREG(base, UART_FR) & UART_FR_TXFF) {} in UartPutcReg()
54 UARTREG(base, UART_DR) = c; in UartPutcReg()
65 UINTPTR base = uart_to_ptr((UINT32)port); in uart_putc() local
66 UartPutcReg(base, c); in uart_putc()
85 STATIC VOID UartPutStr(UINTPTR base, const CHAR *s, UINT32 len) in UartPutStr() argument
91 UartPutcReg(base, '\r'); in UartPutStr()
93 UartPutcReg(base, *( in UartPutStr()
97 UartPutsReg(UINTPTR base, const CHAR *s, UINT32 len, BOOL isLock) UartPutsReg() argument
118 UINTPTR base = uart_to_ptr(0); UartPuts() local
143 UINTPTR base = uart_to_ptr(0); uart_handler() local
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/linux/
H A Dmali_osk_mali.c77 .base = MALI_OFFSET_GP,
82 .base = MALI_OFFSET_GP_MMU,
87 .base = MALI_OFFSET_PP0,
92 .base = MALI_OFFSET_PP0_MMU,
97 .base = MALI_OFFSET_PP1,
102 .base = MALI_OFFSET_PP1_MMU,
108 .base = MALI_OFFSET_PP2,
113 .base = MALI_OFFSET_PP2_MMU,
118 .base = MALI_OFFSET_PP3,
123 .base
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c136 struct rockchip_usb_phy_base *base; member
228 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val); in otg_mode_store()
253 return regmap_write(phy->base->reg_base, phy->reg_offset, val); in rockchip_usb_phy_power()
287 ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val); in rockchip_usb_phy480m_is_enabled()
314 ret = regmap_write(phy->base->reg_base, RK3288_UOC0_CON4, val); in rk3288_usb_phy_init()
316 dev_err(phy->base->dev, "failed to enable bvalid irq\n"); in rk3288_usb_phy_init()
407 static int rockchip_usb_phy_extcon_register(struct rockchip_usb_phy_base *base) in rockchip_usb_phy_extcon_register() argument
410 struct device_node *node = base->dev->of_node; in rockchip_usb_phy_extcon_register()
414 edev = extcon_get_edev_by_phandle(base->dev, 0); in rockchip_usb_phy_extcon_register()
417 dev_err(base in rockchip_usb_phy_extcon_register()
736 rockchip_usb_phy_init(struct rockchip_usb_phy_base *base, struct device_node *child) rockchip_usb_phy_init() argument
[all...]
H A Dphy-rockchip-typec.c386 * @reg: the base address for usb3-phy config.
413 void __iomem *base; member
556 reg = readl(tcphy->base + PMA_CMN_CTRL1); in tcphy_dp_set_power_state()
562 reg = readl(tcphy->base + PHY_DP_MODE_CTL); in tcphy_dp_set_power_state()
565 writel(reg, tcphy->base + PHY_DP_MODE_CTL); in tcphy_dp_set_power_state()
567 ret = readl_poll_timeout(tcphy->base + PHY_DP_MODE_CTL, ack, in tcphy_dp_set_power_state()
630 tcphy->base + PHY_PMA_LANE_CFG); in tcphy_set_lane_mapping()
636 tcphy->base + PHY_PMA_LANE_CFG); in tcphy_set_lane_mapping()
648 writel(0x830, tcphy->base + PMA_CMN_CTRL1); in tcphy_cfg_24m()
654 writel(0x90, tcphy->base in tcphy_cfg_24m()
[all...]
/device/soc/hisilicon/common/platform/mmc/himci_v200/
H A Dhimci.c29 HIMCI_READL((uintptr_t)host->base + MMC_CTRL), HIMCI_READL((uintptr_t)host->base + MMC_PWREN)); in HimciDumpRegs()
31 HIMCI_READL((uintptr_t)host->base + MMC_CLKDIV), HIMCI_READL((uintptr_t)host->base + MMC_CLKENA)); in HimciDumpRegs()
33 HIMCI_READL((uintptr_t)host->base + MMC_TMOUT), HIMCI_READL((uintptr_t)host->base + MMC_CTYPE)); in HimciDumpRegs()
35 HIMCI_READL((uintptr_t)host->base + MMC_BLKSIZ), HIMCI_READL((uintptr_t)host->base + MMC_BYTCNT)); in HimciDumpRegs()
37 HIMCI_READL((uintptr_t)host->base + MMC_CMD), HIMCI_READL((uintptr_t)host->base in HimciDumpRegs()
[all...]
/device/qemu/SmartL_E802/liteos_m/board/hals/csky_driver/src/
H A Ddevices.c32 uint32_t base; member
56 int32_t target_usart_init(int32_t idx, uint32_t *base, uint32_t *irq) in target_usart_init() argument
62 *base = sg_usart_config[s_usart_pin_map[idx].cfg_idx].base; in target_usart_init()
69 uint32_t base; member
84 int32_t target_get_timer(int32_t idx, uint32_t *base, uint32_t *irq) in target_get_timer() argument
90 *base = sg_timer_config[idx].base; in target_get_timer()
96 uint32_t base; member
127 int32_t target_gpio_port_init(port_name_e port, uint32_t *base, uint32_ argument
[all...]
H A Ddw_timer.c42 uint32_t base; member
50 extern int32_t target_get_timer(int32_t idx, uint32_t *base, uint32_t *irq);
55 \param[in] pointer to timer register base
70 dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base); in dw_timer_irqhandler()
93 uint32_t *tbase = (uint32_t *)(timer_priv->base); in do_prepare_sleep_action()
101 uint32_t *tbase = (uint32_t *)(timer_priv->base); in do_wakeup_sleep_action()
119 uint32_t base = 0u; in csi_timer_initialize() local
122 int32_t real_idx = target_get_timer(idx, &base, &irq); in csi_timer_initialize()
129 timer_priv->base = base; in csi_timer_initialize()
[all...]
/device/soc/rockchip/rk3588/kernel/arch/arm64/boot/
H A Dinstall.sh44 base=vmlinuz
48 base=vmlinux
51 if [ -f $4/$base-$1 ]; then
52 mv $4/$base-$1 $4/$base-$1.old
54 cat $2 > $4/$base-$1
/device/soc/rockchip/common/sdk_linux/include/linux/
H A Dmemblock.h48 * @base: base address of the region
54 phys_addr_t base; member
108 int memblock_add_node(phys_addr_t base, phys_addr_t size, int nid);
109 int memblock_add(phys_addr_t base, phys_addr_t size);
110 int memblock_remove(phys_addr_t base, phys_addr_t size);
111 int memblock_free(phys_addr_t base, phys_addr_t size);
112 int memblock_reserve(phys_addr_t base, phys_addr_t size);
114 int memblock_physmem_add(phys_addr_t base, phys_addr_t size);
117 bool memblock_overlaps_region(struct memblock_type *type, phys_addr_t base, phys_addr_
398 memblock_free_early(phys_addr_t base, phys_addr_t size) memblock_free_early() argument
403 memblock_free_early_nid(phys_addr_t base, phys_addr_t size, int nid) memblock_free_early_nid() argument
408 memblock_free_late(phys_addr_t base, phys_addr_t size) memblock_free_late() argument
[all...]
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/cif/
H A Dhw.h27 #define write_cif_reg(base, addr, val) writel(val, (addr) + (base))
28 #define read_cif_reg(base, addr) readl((addr) + (base))
29 #define write_cif_reg_or(base, addr, val) writel(readl((addr) + (base)) | (val), (addr) + (base))
30 #define write_cif_reg_and(base, addr, val) writel(readl((addr) + (base)) & (val), (addr) + (base))
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/cif/
H A Dhw.h27 #define write_cif_reg(base, addr, val) \
28 writel(val, (addr) + (base))
29 #define read_cif_reg(base, addr) \
30 readl((addr) + (base))
31 #define write_cif_reg_or(base, addr, val) \
32 writel(readl((addr) + (base)) | (val), (addr) + (base))
33 #define write_cif_reg_and(base, addr, val) \
34 writel(readl((addr) + (base)) & (val), (addr) + (base))
[all...]
/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-inno-usb3.c127 void __iomem *base; member
152 static inline int param_write(void __iomem *base, const struct u3phy_reg *reg, bool desired) in param_write() argument
160 ret = regmap_write(base, reg->offset, val); in param_write()
165 static inline bool param_exped(void __iomem *base, const struct u3phy_reg *reg, unsigned int value) in param_exped() argument
171 ret = regmap_read(base, reg->offset, &orig); in param_exped()
246 writel(0x30, u3phy_port->base + 0xd8); in rockchip_u3phy_usb2_only_write()
265 writel(0x20, u3phy_port->base + 0xd8); in rockchip_u3phy_usb2_only_write()
748 u3phy_port->base = devm_ioremap_resource(&u3phy_port->phy->dev, &res); in rockchip_u3phy_port_init()
749 if (IS_ERR(u3phy_port->base)) { in rockchip_u3phy_port_init()
751 return PTR_ERR(u3phy_port->base); in rockchip_u3phy_port_init()
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-usb3.c129 void __iomem *base; member
154 static inline int param_write(void __iomem *base, in param_write() argument
163 ret = regmap_write(base, reg->offset, val); in param_write()
168 static inline bool param_exped(void __iomem *base, in param_exped() argument
176 ret = regmap_read(base, reg->offset, &orig); in param_exped()
254 writel(0x30, u3phy_port->base + 0xd8); in rockchip_u3phy_usb2_only_write()
276 writel(0x20, u3phy_port->base + 0xd8); in rockchip_u3phy_usb2_only_write()
768 u3phy_port->base = devm_ioremap_resource(&u3phy_port->phy->dev, &res); in rockchip_u3phy_port_init()
769 if (IS_ERR(u3phy_port->base)) { in rockchip_u3phy_port_init()
771 return PTR_ERR(u3phy_port->base); in rockchip_u3phy_port_init()
[all...]
/device/qemu/arm_mps3_an547/liteos_m/board/driver/
H A Darm_uart_drv.c58 (struct _arm_uart_reg_map_t*)dev->cfg->base; in arm_uart_init()
83 (struct _arm_uart_reg_map_t*)dev->cfg->base; in arm_uart_set_baudrate()
116 (struct _arm_uart_reg_map_t*)dev->cfg->base; in arm_uart_set_clock()
139 (struct _arm_uart_reg_map_t*)dev->cfg->base; in arm_uart_read()
153 (struct _arm_uart_reg_map_t*)dev->cfg->base; in arm_uart_write()
168 (struct _arm_uart_reg_map_t*)dev->cfg->base; in arm_uart_irq_tx_enable()
182 (struct _arm_uart_reg_map_t*)dev->cfg->base; in arm_uart_irq_tx_disable()
192 (struct _arm_uart_reg_map_t*)dev->cfg->base; in arm_uart_tx_ready()
204 (struct _arm_uart_reg_map_t*)dev->cfg->base; in arm_uart_irq_rx_enable()
218 (struct _arm_uart_reg_map_t*)dev->cfg->base; in arm_uart_irq_rx_disable()
[all...]

Completed in 19 milliseconds

12345678910>>...14