1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip eFuse Driver
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Caesar Wang <wxt@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-provider.h>
16 #include <linux/slab.h>
17 #include <linux/of.h>
18 #include <linux/of_platform.h>
19 #include <linux/platform_device.h>
20 #include <linux/rockchip/rockchip_sip.h>
21
22 #define T_CSB_P_S 0
23 #define T_PGENB_P_S 0
24 #define T_LOAD_P_S 0
25 #define T_ADDR_P_S 0
26 #define T_STROBE_P_S (0 + 110) /* 1.1us */
27 #define T_CSB_P_L (0 + 110 + 1000 + 20) /* 200ns */
28 #define T_PGENB_P_L (0 + 110 + 1000 + 20)
29 #define T_LOAD_P_L (0 + 110 + 1000 + 20)
30 #define T_ADDR_P_L (0 + 110 + 1000 + 20)
31 #define T_STROBE_P_L (0 + 110 + 1000) /* 10us */
32 #define T_CSB_R_S 0
33 #define T_PGENB_R_S 0
34 #define T_LOAD_R_S 0
35 #define T_ADDR_R_S 2
36 #define T_STROBE_R_S (2 + 3)
37 #define T_CSB_R_L (2 + 3 + 3 + 3)
38 #define T_PGENB_R_L (2 + 3 + 3 + 3)
39 #define T_LOAD_R_L (2 + 3 + 3 + 3)
40 #define T_ADDR_R_L (2 + 3 + 3 + 2)
41 #define T_STROBE_R_L (2 + 3 + 3)
42
43 #define T_CSB_P 0x28
44 #define T_PGENB_P 0x2c
45 #define T_LOAD_P 0x30
46 #define T_ADDR_P 0x34
47 #define T_STROBE_P 0x38
48 #define T_CSB_R 0x3c
49 #define T_PGENB_R 0x40
50 #define T_LOAD_R 0x44
51 #define T_ADDR_R 0x48
52 #define T_STROBE_R 0x4c
53
54 #define RK1808_MOD 0x00
55 #define RK1808_INT_STATUS RK3328_INT_STATUS
56 #define RK1808_DOUT RK3328_DOUT
57 #define RK1808_AUTO_CTRL RK3328_AUTO_CTRL
58 #define RK1808_USER_MODE BIT(0)
59 #define RK1808_INT_FINISH RK3328_INT_FINISH
60 #define RK1808_AUTO_ENB RK3328_AUTO_ENB
61 #define RK1808_AUTO_RD RK3328_AUTO_RD
62 #define RK1808_A_SHIFT RK3399_A_SHIFT
63 #define RK1808_A_MASK RK3399_A_MASK
64 #define RK1808_NBYTES RK3399_NBYTES
65
66 #define RK3128_A_SHIFT 7
67 #define RK3288_A_SHIFT 6
68 #define RK3288_A_MASK 0x3ff
69 #define RK3288_PGENB BIT(3)
70 #define RK3288_LOAD BIT(2)
71 #define RK3288_STROBE BIT(1)
72 #define RK3288_CSB BIT(0)
73
74 #define RK3328_SECURE_SIZES 96
75 #define RK3328_INT_STATUS 0x0018
76 #define RK3328_DOUT 0x0020
77 #define RK3328_AUTO_CTRL 0x0024
78 #define RK3328_INT_FINISH BIT(0)
79 #define RK3328_AUTO_ENB BIT(0)
80 #define RK3328_AUTO_RD BIT(1)
81
82 #define RK3399_A_SHIFT 16
83 #define RK3399_A_MASK 0x3ff
84 #define RK3399_NBYTES 4
85 #define RK3399_STROBSFTSEL BIT(9)
86 #define RK3399_RSB BIT(7)
87 #define RK3399_PD BIT(5)
88 #define RK3399_PGENB BIT(3)
89 #define RK3399_LOAD BIT(2)
90 #define RK3399_STROBE BIT(1)
91 #define RK3399_CSB BIT(0)
92
93 #define REG_EFUSE_CTRL 0x0000
94 #define REG_EFUSE_DOUT 0x0004
95
96 struct rockchip_efuse_chip {
97 struct device *dev;
98 void __iomem *base;
99 struct clk_bulk_data *clks;
100 int num_clks;
101 phys_addr_t phys;
102 struct mutex mutex;
103 };
104
rk1808_efuse_timing_init(void __iomem *base)105 static void rk1808_efuse_timing_init(void __iomem *base)
106 {
107 /* enable auto mode */
108 writel(readl(base + RK1808_MOD) & (~RK1808_USER_MODE), base + RK1808_MOD);
109
110 /* setup efuse timing */
111 writel((T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P);
112 writel((T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P);
113 writel((T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P);
114 writel((T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P);
115 writel((T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P);
116 writel((T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R);
117 writel((T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R);
118 writel((T_LOAD_R_S << 16) | T_LOAD_R_L, base + T_LOAD_R);
119 writel((T_ADDR_R_S << 16) | T_ADDR_R_L, base + T_ADDR_R);
120 writel((T_STROBE_R_S << 16) | T_STROBE_R_L, base + T_STROBE_R);
121 }
122
rk1808_efuse_timing_deinit(void __iomem *base)123 static void rk1808_efuse_timing_deinit(void __iomem *base)
124 {
125 /* disable auto mode */
126 writel(readl(base + RK1808_MOD) | RK1808_USER_MODE, base + RK1808_MOD);
127
128 /* clear efuse timing */
129 writel(0, base + T_CSB_P);
130 writel(0, base + T_PGENB_P);
131 writel(0, base + T_LOAD_P);
132 writel(0, base + T_ADDR_P);
133 writel(0, base + T_STROBE_P);
134 writel(0, base + T_CSB_R);
135 writel(0, base + T_PGENB_R);
136 writel(0, base + T_LOAD_R);
137 writel(0, base + T_ADDR_R);
138 writel(0, base + T_STROBE_R);
139 }
140
rockchip_rk1808_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)141 static int rockchip_rk1808_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)
142 {
143 struct rockchip_efuse_chip *efuse = context;
144 unsigned int addr_start, addr_end, addr_offset, addr_len;
145 u32 out_value, status;
146 u8 *buf;
147 int ret, i = 0;
148
149 mutex_lock(&efuse->mutex);
150
151 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
152 if (ret < 0) {
153 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
154 goto out;
155 }
156
157 addr_start = rounddown(offset, RK1808_NBYTES) / RK1808_NBYTES;
158 addr_end = roundup(offset + bytes, RK1808_NBYTES) / RK1808_NBYTES;
159 addr_offset = offset % RK1808_NBYTES;
160 addr_len = addr_end - addr_start;
161
162 buf = kzalloc(sizeof(*buf) * addr_len * RK1808_NBYTES, GFP_KERNEL);
163 if (!buf) {
164 ret = -ENOMEM;
165 goto nomem;
166 }
167
168 rk1808_efuse_timing_init(efuse->base);
169
170 while (addr_len--) {
171 writel(RK1808_AUTO_RD | RK1808_AUTO_ENB | ((addr_start++ & RK1808_A_MASK) << RK1808_A_SHIFT),
172 efuse->base + RK1808_AUTO_CTRL);
173 udelay(0x2);
174 status = readl(efuse->base + RK1808_INT_STATUS);
175 if (!(status & RK1808_INT_FINISH)) {
176 ret = -EIO;
177 goto err;
178 }
179 out_value = readl(efuse->base + RK1808_DOUT);
180 writel(RK1808_INT_FINISH, efuse->base + RK1808_INT_STATUS);
181
182 memcpy(&buf[i], &out_value, RK1808_NBYTES);
183 i += RK1808_NBYTES;
184 }
185 memcpy(val, buf + addr_offset, bytes);
186 err:
187 rk1808_efuse_timing_deinit(efuse->base);
188 kfree(buf);
189 nomem:
190 rk1808_efuse_timing_deinit(efuse->base);
191 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
192 out:
193 mutex_unlock(&efuse->mutex);
194
195 return ret;
196 }
197
rockchip_rk3128_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)198 static int rockchip_rk3128_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)
199 {
200 struct rockchip_efuse_chip *efuse = context;
201 u8 *buf = val;
202 int ret;
203
204 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
205 if (ret < 0) {
206 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
207 return ret;
208 }
209
210 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
211 udelay(1);
212 while (bytes--) {
213 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3128_A_SHIFT)),
214 efuse->base + REG_EFUSE_CTRL);
215 writel(readl(efuse->base + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3128_A_SHIFT),
216 efuse->base + REG_EFUSE_CTRL);
217 udelay(1);
218 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
219 udelay(1);
220 *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
221 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
222 udelay(1);
223 }
224
225 /* Switch to standby mode */
226 writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
227
228 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
229
230 return 0;
231 }
232
rockchip_rk3288_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)233 static int rockchip_rk3288_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)
234 {
235 struct rockchip_efuse_chip *efuse = context;
236 u8 *buf = val;
237 int ret;
238
239 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
240 if (ret < 0) {
241 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
242 return ret;
243 }
244
245 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
246 udelay(1);
247 while (bytes--) {
248 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3288_A_SHIFT)),
249 efuse->base + REG_EFUSE_CTRL);
250 writel(readl(efuse->base + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
251 efuse->base + REG_EFUSE_CTRL);
252 udelay(1);
253 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);
254 udelay(1);
255 *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
256 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);
257 udelay(1);
258 }
259
260 /* Switch to standby mode */
261 writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
262
263 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
264
265 return 0;
266 }
267
rockchip_rk3288_efuse_secure_read(void *context, unsigned int offset, void *val, size_t bytes)268 static int rockchip_rk3288_efuse_secure_read(void *context, unsigned int offset, void *val, size_t bytes)
269 {
270 struct rockchip_efuse_chip *efuse = context;
271 u8 *buf = val;
272 u32 wr_val;
273 int ret;
274
275 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
276 if (ret < 0) {
277 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
278 return ret;
279 }
280
281 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_LOAD | RK3288_PGENB);
282 udelay(1);
283 while (bytes--) {
284 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3288_A_SHIFT));
285 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
286 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);
287 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
288 udelay(1);
289 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | RK3288_STROBE;
290 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
291 udelay(1);
292 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);
293 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~RK3288_STROBE);
294 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
295 udelay(1);
296 }
297
298 /* Switch to standby mode */
299 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_PGENB | RK3288_CSB);
300
301 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
302
303 return 0;
304 }
305
rockchip_rk3328_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)306 static int rockchip_rk3328_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)
307 {
308 struct rockchip_efuse_chip *efuse = context;
309 unsigned int addr_start, addr_end, addr_offset, addr_len;
310 u32 out_value, status;
311 u8 *buf;
312 int ret, i = 0;
313
314 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
315 if (ret < 0) {
316 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
317 return ret;
318 }
319
320 /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
321 offset += RK3328_SECURE_SIZES;
322 addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
323 addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
324 addr_offset = offset % RK3399_NBYTES;
325 addr_len = addr_end - addr_start;
326
327 buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)), GFP_KERNEL);
328 if (!buf) {
329 ret = -ENOMEM;
330 goto nomem;
331 }
332
333 while (addr_len--) {
334 writel(RK3328_AUTO_RD | RK3328_AUTO_ENB | ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
335 efuse->base + RK3328_AUTO_CTRL);
336 udelay(0x4);
337 status = readl(efuse->base + RK3328_INT_STATUS);
338 if (!(status & RK3328_INT_FINISH)) {
339 ret = -EIO;
340 goto err;
341 }
342 out_value = readl(efuse->base + RK3328_DOUT);
343 writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);
344
345 memcpy(&buf[i], &out_value, RK3399_NBYTES);
346 i += RK3399_NBYTES;
347 }
348
349 memcpy(val, buf + addr_offset, bytes);
350 err:
351 kfree(buf);
352 nomem:
353 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
354
355 return ret;
356 }
357
rockchip_rk3368_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)358 static int rockchip_rk3368_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)
359 {
360 struct rockchip_efuse_chip *efuse = context;
361 u8 *buf = val;
362 u32 wr_val;
363 int ret;
364
365 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
366 if (ret < 0) {
367 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
368 return ret;
369 }
370
371 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_LOAD | RK3288_PGENB);
372 udelay(1);
373 while (bytes--) {
374 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3288_A_SHIFT));
375 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
376 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);
377 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
378 udelay(1);
379 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) | RK3288_STROBE;
380 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
381 udelay(1);
382 *buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);
383 wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) & (~RK3288_STROBE);
384 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
385 udelay(1);
386 }
387
388 /* Switch to standby mode */
389 sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_PGENB | RK3288_CSB);
390
391 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
392
393 return 0;
394 }
395
rockchip_rk3399_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)396 static int rockchip_rk3399_efuse_read(void *context, unsigned int offset, void *val, size_t bytes)
397 {
398 struct rockchip_efuse_chip *efuse = context;
399 unsigned int addr_start, addr_end, addr_offset, addr_len;
400 u32 out_value;
401 u8 *buf;
402 int ret, i = 0;
403
404 ret = clk_bulk_prepare_enable(efuse->num_clks, efuse->clks);
405 if (ret < 0) {
406 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
407 return ret;
408 }
409
410 addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES;
411 addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES;
412 addr_offset = offset % RK3399_NBYTES;
413 addr_len = addr_end - addr_start;
414
415 buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)), GFP_KERNEL);
416 if (!buf) {
417 ret = -ENOMEM;
418 goto disable_clks;
419 }
420
421 writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB, efuse->base + REG_EFUSE_CTRL);
422 udelay(1);
423 while (addr_len--) {
424 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE | ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
425 efuse->base + REG_EFUSE_CTRL);
426 udelay(1);
427 out_value = readl(efuse->base + REG_EFUSE_DOUT);
428 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE), efuse->base + REG_EFUSE_CTRL);
429 udelay(1);
430
431 memcpy(&buf[i], &out_value, RK3399_NBYTES);
432 i += RK3399_NBYTES;
433 }
434
435 /* Switch to standby mode */
436 writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);
437
438 memcpy(val, buf + addr_offset, bytes);
439
440 kfree(buf);
441
442 disable_clks:
443 clk_bulk_disable_unprepare(efuse->num_clks, efuse->clks);
444
445 return ret;
446 }
447
448 static struct nvmem_config econfig = {
449 .name = "rockchip-efuse",
450 .stride = 1,
451 .word_size = 1,
452 .read_only = true,
453 };
454
455 static const struct of_device_id rockchip_efuse_match[] = {
456 /* deprecated but kept around for dts binding compatibility */
457 {
458 .compatible = "rockchip,rk1808-efuse",
459 .data = (void *)&rockchip_rk1808_efuse_read,
460 },
461 {
462 .compatible = "rockchip,rockchip-efuse",
463 .data = (void *)&rockchip_rk3288_efuse_read,
464 },
465 {
466 .compatible = "rockchip,rk3066a-efuse",
467 .data = (void *)&rockchip_rk3288_efuse_read,
468 },
469 {
470 .compatible = "rockchip,rk3128-efuse",
471 .data = (void *)&rockchip_rk3128_efuse_read,
472 },
473 {
474 .compatible = "rockchip,rk3188-efuse",
475 .data = (void *)&rockchip_rk3288_efuse_read,
476 },
477 {
478 .compatible = "rockchip,rk3228-efuse",
479 .data = (void *)&rockchip_rk3288_efuse_read,
480 },
481 {
482 .compatible = "rockchip,rk3288-efuse",
483 .data = (void *)&rockchip_rk3288_efuse_read,
484 },
485 {
486 .compatible = "rockchip,rk3288-secure-efuse",
487 .data = (void *)&rockchip_rk3288_efuse_secure_read,
488 },
489 {
490 .compatible = "rockchip,rk3328-efuse",
491 .data = (void *)&rockchip_rk3328_efuse_read,
492 },
493 {
494 .compatible = "rockchip,rk3368-efuse",
495 .data = (void *)&rockchip_rk3368_efuse_read,
496 },
497 {
498 .compatible = "rockchip,rk3399-efuse",
499 .data = (void *)&rockchip_rk3399_efuse_read,
500 },
501 {},
502 };
503 MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
504
rockchip_efuse_probe(struct platform_device *pdev)505 static int rockchip_efuse_probe(struct platform_device *pdev)
506 {
507 struct resource *res;
508 struct nvmem_device *nvmem;
509 struct rockchip_efuse_chip *efuse;
510 const void *data;
511 struct device *dev = &pdev->dev;
512
513 data = of_device_get_match_data(dev);
514 if (!data) {
515 dev_err(dev, "failed to get match data\n");
516 return -EINVAL;
517 }
518
519 efuse = devm_kzalloc(dev, sizeof(struct rockchip_efuse_chip), GFP_KERNEL);
520 if (!efuse) {
521 return -ENOMEM;
522 }
523
524 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
525 efuse->phys = res->start;
526 efuse->base = devm_ioremap_resource(dev, res);
527 if (IS_ERR(efuse->base)) {
528 return PTR_ERR(efuse->base);
529 }
530
531 efuse->num_clks = devm_clk_bulk_get_all(dev, &efuse->clks);
532 if (efuse->num_clks < 1) {
533 return -ENODEV;
534 }
535
536 mutex_init(&efuse->mutex);
537
538 efuse->dev = dev;
539 if (of_property_read_u32(dev->of_node, "rockchip,efuse-size", &econfig.size)) {
540 econfig.size = resource_size(res);
541 }
542 econfig.reg_read = data;
543 econfig.priv = efuse;
544 econfig.dev = efuse->dev;
545 nvmem = devm_nvmem_register(dev, &econfig);
546
547 return PTR_ERR_OR_ZERO(nvmem);
548 }
549
550 static struct platform_driver rockchip_efuse_driver = {
551 .probe = rockchip_efuse_probe,
552 .driver =
553 {
554 .name = "rockchip-efuse",
555 .of_match_table = rockchip_efuse_match,
556 },
557 };
558
rockchip_efuse_init(void)559 static int __init rockchip_efuse_init(void)
560 {
561 int ret;
562
563 ret = platform_driver_register(&rockchip_efuse_driver);
564 if (ret) {
565 pr_err("failed to register efuse driver\n");
566 return ret;
567 }
568
569 return 0;
570 }
571
rockchip_efuse_exit(void)572 static void __exit rockchip_efuse_exit(void)
573 {
574 return platform_driver_unregister(&rockchip_efuse_driver);
575 }
576
577 subsys_initcall(rockchip_efuse_init);
578 module_exit(rockchip_efuse_exit);
579
580 MODULE_DESCRIPTION("rockchip_efuse driver");
581 MODULE_LICENSE("GPL v2");
582