Lines Matching refs:base

98     void __iomem *base;

105 static void rk1808_efuse_timing_init(void __iomem *base)

108     writel(readl(base + RK1808_MOD) & (~RK1808_USER_MODE), base + RK1808_MOD);

111     writel((T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P);

112     writel((T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P);

113     writel((T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P);

114     writel((T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P);

115     writel((T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P);

116     writel((T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R);

117     writel((T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R);

118     writel((T_LOAD_R_S << 16) | T_LOAD_R_L, base + T_LOAD_R);

119     writel((T_ADDR_R_S << 16) | T_ADDR_R_L, base + T_ADDR_R);

120     writel((T_STROBE_R_S << 16) | T_STROBE_R_L, base + T_STROBE_R);

123 static void rk1808_efuse_timing_deinit(void __iomem *base)

126     writel(readl(base + RK1808_MOD) | RK1808_USER_MODE, base + RK1808_MOD);

129     writel(0, base + T_CSB_P);

130     writel(0, base + T_PGENB_P);

131     writel(0, base + T_LOAD_P);

132     writel(0, base + T_ADDR_P);

133     writel(0, base + T_STROBE_P);

134     writel(0, base + T_CSB_R);

135     writel(0, base + T_PGENB_R);

136     writel(0, base + T_LOAD_R);

137     writel(0, base + T_ADDR_R);

138     writel(0, base + T_STROBE_R);

168     rk1808_efuse_timing_init(efuse->base);

172                efuse->base + RK1808_AUTO_CTRL);

174         status = readl(efuse->base + RK1808_INT_STATUS);

179         out_value = readl(efuse->base + RK1808_DOUT);

180         writel(RK1808_INT_FINISH, efuse->base + RK1808_INT_STATUS);

187     rk1808_efuse_timing_deinit(efuse->base);

190     rk1808_efuse_timing_deinit(efuse->base);

210     writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);

213         writel(readl(efuse->base + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3128_A_SHIFT)),

214                efuse->base + REG_EFUSE_CTRL);

215         writel(readl(efuse->base + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3128_A_SHIFT),

216                efuse->base + REG_EFUSE_CTRL);

218         writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);

220         *buf++ = readb(efuse->base + REG_EFUSE_DOUT);

221         writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);

226     writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);

245     writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);

248         writel(readl(efuse->base + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3288_A_SHIFT)),

249                efuse->base + REG_EFUSE_CTRL);

250         writel(readl(efuse->base + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),

251                efuse->base + REG_EFUSE_CTRL);

253         writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3288_STROBE, efuse->base + REG_EFUSE_CTRL);

255         *buf++ = readb(efuse->base + REG_EFUSE_DOUT);

256         writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL);

261     writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);

335                efuse->base + RK3328_AUTO_CTRL);

337         status = readl(efuse->base + RK3328_INT_STATUS);

342         out_value = readl(efuse->base + RK3328_DOUT);

343         writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);

421     writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB, efuse->base + REG_EFUSE_CTRL);

424         writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE | ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),

425                efuse->base + REG_EFUSE_CTRL);

427         out_value = readl(efuse->base + REG_EFUSE_DOUT);

428         writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE), efuse->base + REG_EFUSE_CTRL);

436     writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);

526     efuse->base = devm_ioremap_resource(dev, res);

527     if (IS_ERR(efuse->base)) {

528         return PTR_ERR(efuse->base);