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Searched refs:UPDATE (Results 1 - 10 of 10) sorted by relevance

/device/soc/rockchip/rk3588/kernel/include/linux/mfd/
H A Drk628.h19 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
24 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26)
26 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25)
28 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22)
30 #define SW_EDID_MODE(x) UPDATE(x, 21, 21)
32 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10)
36 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8)
38 #define SW_OUTPUT_MODE(x) UPDATE(x, 7, 3)
40 #define SW_INPUT_MODE(x) UPDATE(x, 2, 0)
45 #define GRF_GPIO_RX_CEC_SEL(x) UPDATE(
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H A Drk618.h22 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
100 #define HDMI_CLK_SEL_VIDEO_INF0_CLK UPDATE(2, 13, 12)
101 #define HDMI_CLK_SEL_SCALER_CLK UPDATE(1, 13, 12)
H A Drk630.h16 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-dsidphy.c25 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
49 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
50 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
63 #define REG_FBDIV_HI(x) UPDATE(((x) >> 8), 5, 5)
65 #define REG_PREDIV(x) UPDATE(x, 4, 0)
68 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
71 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
73 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
76 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
78 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(
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/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-inno-hdmi-phy.c34 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
55 #define AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
57 #define AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
81 #define TMDS_DRIVER_ENABLE UPDATE(0xf, 3, 0)
86 #define PRE_PLL_FB_DIV_8(x) UPDATE(x, 7, 7)
89 #define PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
91 #define PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
93 #define PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
97 #define PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
100 #define PRE_PLL_PCLK_DIV_A(x) UPDATE(
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/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi-phy.c34 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
55 #define AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
57 #define AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
81 #define TMDS_DRIVER_ENABLE UPDATE(0xf, 3, 0)
86 #define PRE_PLL_FB_DIV_8(x) UPDATE(x, 7, 7)
89 #define PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
91 #define PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
93 #define PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
97 #define PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
100 #define PRE_PLL_PCLK_DIV_A(x) UPDATE(
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H A Dphy-rockchip-samsung-dcphy.c20 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
28 #define I_MUX_SEL(x) UPDATE(x, 6, 5)
33 #define S(x) UPDATE(x, 10, 8)
35 #define P(x) UPDATE(x, 5, 0)
39 #define M(x) UPDATE(x, 9, 0)
42 #define MRR(x) UPDATE(x, 13, 8)
44 #define MFR(x) UPDATE(x, 7, 0)
52 #define PLL_LOCK_CNT(x) UPDATE(x, 15, 0)
54 #define PLL_STB_CNT(x) UPDATE(x, 15, 0)
62 #define T_PHY_READY(x) UPDATE(
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H A Dphy-rockchip-samsung-hdptx-hdmi.c26 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
48 #define LCPLL_EN(x) UPDATE(x, 4, 4)
50 #define LCPLL_LCVCO_MODE_EN(x) UPDATE(x, 4, 4)
74 #define LCPLL_PI_EN(x) UPDATE(x, 5, 5)
76 #define LCPLL_100M_CLK_EN(x) UPDATE(x, 0, 0)
96 #define LCPLL_SDC_N(x) UPDATE(x, 3, 1)
99 #define LCPLL_SDC_NUMBERATOR(x) UPDATE(x, 5, 0)
102 #define LCPLL_SDC_DENOMINATOR(x) UPDATE(x, 7, 2)
155 #define ROPLL_SDM_EN(x) UPDATE(x, 6, 6)
167 #define ROPLL_SDM_NUM_SIGN_RBR(x) UPDATE(
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/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Ddw-mipi-dsi2-rockchip.c41 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) macro
46 #define CMD_TX_MODE(x) UPDATE((x), 24, 24)
68 #define TO_HSTX(x) UPDATE((x), 15, 0)
70 #define TO_HSTXRDY(x) UPDATE((x), 15, 0)
72 #define TO_LPRXRDY(x) UPDATE((x), 15, 0)
74 #define TO_LPTXRDY(x) UPDATE((x), 15, 0)
76 #define TO_LPTXTRIG(x) UPDATE((x), 15, 0)
78 #define TO_LPTXULPS(x) UPDATE((x), 15, 0)
80 #define TO_BTA(x) UPDATE((x), 15, 0)
83 #define PPI_WIDTH(x) UPDATE((
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/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
H A Ddw-mipi-dsi2-rockchip.c41 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) macro
46 #define CMD_TX_MODE(x) UPDATE(x, 24, 24)
68 #define TO_HSTX(x) UPDATE(x, 15, 0)
70 #define TO_HSTXRDY(x) UPDATE(x, 15, 0)
72 #define TO_LPRXRDY(x) UPDATE(x, 15, 0)
74 #define TO_LPTXRDY(x) UPDATE(x, 15, 0)
76 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0)
78 #define TO_LPTXULPS(x) UPDATE(x, 15, 0)
80 #define TO_BTA(x) UPDATE(x, 15, 0)
83 #define PPI_WIDTH(x) UPDATE(
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