Lines Matching refs:UPDATE
34 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
55 #define AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
57 #define AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
81 #define TMDS_DRIVER_ENABLE UPDATE(0xf, 3, 0)
86 #define PRE_PLL_FB_DIV_8(x) UPDATE(x, 7, 7)
89 #define PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
91 #define PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
93 #define PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
97 #define PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
100 #define PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
104 #define PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
107 #define PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)
110 #define PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4)
112 #define PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2)
114 #define PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0)
119 #define POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6)
122 #define POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
124 #define POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
127 #define POST_PLL_FB_DIV_8(x) UPDATE(x, 7, 7)
129 #define POST_PLL_POST_DIV(x) UPDATE(x, 5, 4)
133 #define TMDS_CH_TA_ENABLE UPDATE(0xf, 7, 4)
136 #define TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6)
137 #define TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4)
138 #define TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2)
139 #define TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0)
142 #define TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4)
144 #define TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2)
146 #define TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0)
148 #define TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4)
149 #define TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0)
151 #define TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4)
152 #define TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0)