Lines Matching refs:UPDATE
19 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
24 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26)
26 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25)
28 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22)
30 #define SW_EDID_MODE(x) UPDATE(x, 21, 21)
32 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10)
36 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8)
38 #define SW_OUTPUT_MODE(x) UPDATE(x, 7, 3)
40 #define SW_INPUT_MODE(x) UPDATE(x, 2, 0)
45 #define GRF_GPIO_RX_CEC_SEL(x) UPDATE(x, 7, 7)
47 #define GRF_GPIO_RXDDC_SDA_SEL(x) UPDATE(x, 6, 6)
49 #define GRF_GPIO_RXDDC_SCL_SEL(x) UPDATE(x, 5, 5)
58 #define SCL_V_FACTOR(x) UPDATE(x, 31, 16)
59 #define SCL_H_FACTOR(x) UPDATE(x, 15, 0)
61 #define DSP_FRAME_VST(x) UPDATE(x, 28, 16)
62 #define DSP_FRAME_HST(x) UPDATE(x, 12, 0)
64 #define DSP_HS_END(x) UPDATE(x, 23, 16)
65 #define DSP_HTOTAL(x) UPDATE(x, 12, 0)
67 #define DSP_HACT_ST(x) UPDATE(x, 28, 16)
68 #define DSP_HACT_END(x) UPDATE(x, 12, 0)
70 #define DSP_VS_END(x) UPDATE(x, 23, 16)
71 #define DSP_VTOTAL(x) UPDATE(x, 12, 0)
73 #define DSP_VACT_ST(x) UPDATE(x, 28, 16)
74 #define DSP_VACT_END(x) UPDATE(x, 12, 0)
76 #define DSP_HBOR_ST(x) UPDATE(x, 28, 16)
77 #define DSP_HBOR_END(x) UPDATE(x, 12, 0)
79 #define DSP_VBOR_ST(x) UPDATE(x, 28, 16)
80 #define DSP_VBOR_END(x) UPDATE(x, 12, 0)
85 #define SW_TXPHY_REFCLK_SEL(x) UPDATE(x, 6, 5)
87 #define SW_HDMITX_VCLK_PLLREF_SEL(x) UPDATE(x, 4, 4)
89 #define SW_SPLIT_MODE(x) UPDATE(x, 1, 1)
110 #define SW_HRES(x) UPDATE(x, 28, 16)
137 #define FORCETXSTOPMODE(x) UPDATE(x, 19, 16)
139 #define FORCERXMODE(x) UPDATE(x, 15, 12)
144 #define PHY_TESTDIN(x) UPDATE(x, 7, 0)