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Searched refs:MFLAGS (Results 1 - 14 of 14) sorted by relevance

/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk-rk3588.c514 #define MFLAGS CLK_MUX_HIWORD_MASK macro
520 RK3588_CLKSEL_CON(26), 0, 2, MFLAGS);
524 RK3588_CLKSEL_CON(28), 0, 2, MFLAGS);
528 RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS);
532 RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS);
536 RK3588_CLKSEL_CON(30), 0, 2, MFLAGS);
540 RK3588_CLKSEL_CON(32), 0, 2, MFLAGS);
544 RK3588_CLKSEL_CON(120), 0, 2, MFLAGS);
548 RK3588_CLKSEL_CON(142), 0, 2, MFLAGS);
552 RK3588_CLKSEL_CON(146), 0, 2, MFLAGS);
[all...]
/device/soc/rockchip/rk3566/vendor/drivers/clk/
H A Dclk-rk3568.c319 #define MFLAGS CLK_MUX_HIWORD_MASK macro
324 CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(11), 10, 2, MFLAGS);
327 CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(13), 10, 2, MFLAGS);
330 CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(15), 10, 2, MFLAGS);
333 CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(17), 10, 2, MFLAGS);
336 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(19), 10, 2, MFLAGS);
339 CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(21), 10, 2, MFLAGS);
342 CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(83), 10, 2, MFLAGS);
345 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(23), 15, 1, MFLAGS);
348 MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(25), 15, 1, MFLAGS);
[all...]
/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-rk1808.c190 #define MFLAGS CLK_MUX_HIWORD_MASK macro
195 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(39), 14, 2, MFLAGS);
198 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(42), 14, 2, MFLAGS);
201 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(45), 14, 2, MFLAGS);
204 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(48), 14, 2, MFLAGS);
207 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(51), 14, 2, MFLAGS);
210 MUX(0, "clk_uart6_mux", mux_uart6_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(54), 14, 2, MFLAGS);
213 MUX(0, "clk_uart7_mux", mux_uart7_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(57), 14, 2, MFLAGS);
216 MUX(0, "dclk_vopraw_mux", mux_dclk_vopraw_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(5), 14, 2, MFLAGS);
219 MUX(0, "dclk_voplite_mux", mux_dclk_voplite_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(7), 14, 2, MFLAGS);
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-rk3308.c168 #define MFLAGS CLK_MUX_HIWORD_MASK macro
173 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(11), 14, 2, MFLAGS);
176 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(14), 14, 2, MFLAGS);
179 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(17), 14, 2, MFLAGS);
182 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(20), 14, 2, MFLAGS);
185 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(23), 14, 2, MFLAGS);
188 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(8), 14, 2, MFLAGS);
191 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(2), 8, 2, MFLAGS);
194 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(46), 15, 1, MFLAGS);
198 2, MFLAGS);
[all...]
H A Dclk-rk3328.c185 #define MFLAGS CLK_MUX_HIWORD_MASK macro
190 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(6), 8, 2, MFLAGS);
193 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(8), 8, 2, MFLAGS);
196 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(10), 8, 2, MFLAGS);
199 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(12), 8, 2, MFLAGS);
202 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(14), 8, 2, MFLAGS);
205 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(16), 8, 2, MFLAGS);
208 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(18), 8, 2, MFLAGS);
216 COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0, RK3328_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 14, DFLAGS,
220 MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, RK3328_MISC_CON, 13, 1, MFLAGS),
[all...]
H A Dclk-rv1108.c152 #define MFLAGS CLK_MUX_HIWORD_MASK macro
158 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(13), 8, 2, MFLAGS);
161 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(14), 8, 2, MFLAGS);
164 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(15), 8, 2, MFLAGS);
167 MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(5), 12, 2, MFLAGS);
170 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(6), 12, 2, MFLAGS);
173 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(7), 12, 2, MFLAGS);
176 MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT, RV1108_MISC_CON, 13, 1, MFLAGS),
177 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT, RV1108_MISC_CON, 15, 1, MFLAGS),
194 COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0, RV1108_CLKSEL_CON(37), 6, 2, MFLAGS,
[all...]
H A Dclk-px30.c168 #define MFLAGS CLK_MUX_HIWORD_MASK macro
173 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(26), 15, 1, MFLAGS);
176 MUX(SCLK_I2S0_TX_MUX, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(28), 10, 2, MFLAGS);
179 MUX(SCLK_I2S0_RX_MUX, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(58), 10, 2, MFLAGS);
182 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(30), 10, 2, MFLAGS);
185 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(32), 10, 2, MFLAGS);
188 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(35), 14, 2, MFLAGS);
191 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(38), 14, 2, MFLAGS);
194 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(41), 14, 2, MFLAGS);
197 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(44), 14, 2, MFLAGS);
[all...]
H A Dclk-rk3036.c148 #define MFLAGS CLK_MUX_HIWORD_MASK macro
153 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
156 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
159 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
162 MUX(SCLK_I2S_PRE, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
165 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0, RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
182 COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2,
193 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, CLK_IS_CRITICAL, RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5,
201 COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, CLK_IS_CRITICAL, RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5,
212 COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(2), 4, 1, MFLAGS,
[all...]
H A Dclk-rk3368.c165 #define MFLAGS CLK_MUX_HIWORD_MASK macro
248 MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
251 MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
254 MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
257 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
260 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
263 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
266 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(41), 8, 2, MFLAGS);
275 MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(13), 8, 1, MFLAGS),
294 COMPOSITE_NOGATE(0, "sclk_cs_pre", mux_cs_src_p, CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(4), 6, 2, MFLAGS,
[all...]
H A Dclk-rk3399.c239 #define MFLAGS CLK_MUX_HIWORD_MASK macro
245 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
248 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
251 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
254 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
257 SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(33), 8, 2, MFLAGS, uart_mux_idx);
260 SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(34), 8, 2, MFLAGS, uart_mux_idx);
263 SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(35), 8, 2, MFLAGS, uart_mux_idx);
266 SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(36), 8, 2, MFLAGS, uart_mux_idx);
270 MFLAGS, uart_mux_id
[all...]
H A Dclk-rk3228.c170 #define MFLAGS CLK_MUX_HIWORD_MASK macro
175 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
178 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
181 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
184 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
187 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
190 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
193 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
206 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3,
221 MUX(SCLK_HDMI_PHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, RK2928_MISC_CON, 13, 1, MFLAGS),
[all...]
H A Dclk-rk3128.c162 #define MFLAGS CLK_MUX_HIWORD_MASK macro
167 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
170 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
173 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
176 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
179 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
182 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
197 COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2,
211 MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, RK2928_MISC_CON, 15, 1, MFLAGS),
214 COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IS_CRITICAL, RK2928_CLKSEL_CON(0), 13, 2, MFLAGS,
[all...]
H A Dclk-rk3288.c193 #define MFLAGS CLK_MUX_HIWORD_MASK macro
199 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(4), 8, 2, MFLAGS);
202 MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(5), 8, 2, MFLAGS);
205 MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(40), 8, 2, MFLAGS);
208 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
211 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
214 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
217 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
220 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(3), 8, 2, MFLAGS);
254 COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED, RK3288_CLKSEL_CON(26), 2, 1, MFLAGS,
[all...]
H A Dclk-rk3188.c229 #define MFLAGS CLK_MUX_HIWORD_MASK macro
240 MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0, RK2928_CLKSEL_CON(22), 4, 2, MFLAGS);
243 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
246 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
249 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
252 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
255 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0, RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
268 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
271 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
276 COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(26), 8, 1, MFLAGS,
[all...]

Completed in 11 milliseconds