Lines Matching refs:MFLAGS
319 #define MFLAGS CLK_MUX_HIWORD_MASK
324 CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(11), 10, 2, MFLAGS);
327 CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(13), 10, 2, MFLAGS);
330 CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(15), 10, 2, MFLAGS);
333 CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(17), 10, 2, MFLAGS);
336 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(19), 10, 2, MFLAGS);
339 CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(21), 10, 2, MFLAGS);
342 CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(83), 10, 2, MFLAGS);
345 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(23), 15, 1, MFLAGS);
348 MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(25), 15, 1, MFLAGS);
351 MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(52), 12, 2, MFLAGS);
354 MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(54), 12, 2, MFLAGS);
357 MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(56), 12, 2, MFLAGS);
360 MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(58), 12, 2, MFLAGS);
363 MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(60), 12, 2, MFLAGS);
366 MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(62), 12, 2, MFLAGS);
369 MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(64), 12, 2, MFLAGS);
372 MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(66), 12, 2, MFLAGS);
375 MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(68), 12, 2, MFLAGS);
378 MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
382 RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS);
385 COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", npll_gpll_p, 0, RK3568_CLKSEL_CON(7), 7, 1, MFLAGS, 4, 2, DFLAGS,
427 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, RK3568_MODE_CON0, 14, 2, MFLAGS),
430 COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IS_CRITICAL, RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4,
432 COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IS_CRITICAL, RK3568_CLKSEL_CON(2), 15, 1, MFLAGS,
451 RK3568_CLKSEL_CON(5), 14, 2, MFLAGS, RK3568_CLKGATE_CON(1), 2, GFLAGS),
460 MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(2), 0, GFLAGS),
462 MFLAGS | CLK_MUX_READ_ONLY),
473 COMPOSITE_BROTHER(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0, RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS,
476 RK3568_CLKSEL_CON(7), 8, 1, MFLAGS),
477 MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(7), 15, 1, MFLAGS),
493 MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(4), 0, GFLAGS),
494 MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(9), 15, 1, MFLAGS),
502 RK3568_CLKSEL_CON(10), 8, 2, MFLAGS, RK3568_CLKGATE_CON(5), 0, GFLAGS),
504 RK3568_CLKSEL_CON(10), 10, 2, MFLAGS, RK3568_CLKGATE_CON(5), 1, GFLAGS),
507 MFLAGS, RK3568_CLKGATE_CON(5), 9, GFLAGS),
515 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0,
522 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 3, GFLAGS),
524 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0,
531 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 7, GFLAGS),
533 COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0,
540 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 11, GFLAGS),
542 COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0,
549 15, 1, MFLAGS, RK3568_CLKGATE_CON(6), 15, GFLAGS),
551 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7,
558 MFLAGS, RK3568_CLKGATE_CON(7), 3, GFLAGS),
560 COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0,
567 15, 1, MFLAGS, RK3568_CLKGATE_CON(7), 7, GFLAGS),
569 COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0,
576 15, 1, MFLAGS, RK3568_CLKGATE_CON(7), 11, GFLAGS),
579 RK3568_GRF_SOC_CON1, 5, 1, MFLAGS),
581 RK3568_GRF_SOC_CON2, 15, 1, MFLAGS),
582 MUXGRF(I2S1_MCLK_RX_IOE, "i2s1_mclk_rx_ioe", i2s1_mclk_rx_ioe_p, 0, RK3568_GRF_SOC_CON2, 0, 1, MFLAGS),
583 MUXGRF(I2S1_MCLK_TX_IOE, "i2s1_mclk_tx_ioe", i2s1_mclk_tx_ioe_p, 0, RK3568_GRF_SOC_CON2, 1, 1, MFLAGS),
584 MUXGRF(I2S2_MCLK_IOE, "i2s2_mclk_ioe", i2s2_mclk_ioe_p, 0, RK3568_GRF_SOC_CON2, 2, 1, MFLAGS),
585 MUXGRF(I2S3_MCLK_IOE, "i2s3_mclk_ioe", i2s3_mclk_ioe_p, 0, RK3568_GRF_SOC_CON2, 3, 1, MFLAGS),
588 COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0, RK3568_CLKSEL_CON(23), 8, 2, MFLAGS, RK3568_CLKGATE_CON(5), 15,
593 COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0, RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7,
600 COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0, RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS,
607 COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0, RK3568_CLKSEL_CON(23), 10, 2, MFLAGS,
614 RK3568_CLKSEL_CON(27), 0, 2, MFLAGS, RK3568_CLKGATE_CON(8), 7, GFLAGS),
616 RK3568_CLKSEL_CON(27), 2, 2, MFLAGS, RK3568_CLKGATE_CON(8), 8, GFLAGS),
620 MFLAGS, RK3568_CLKGATE_CON(8), 13, GFLAGS),
622 MFLAGS, RK3568_CLKGATE_CON(8), 14, GFLAGS),
630 COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0, RK3568_CLKSEL_CON(28), 0, 2, MFLAGS,
634 COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0, RK3568_CLKSEL_CON(28), 4, 3, MFLAGS, RK3568_CLKGATE_CON(9), 4,
638 COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0, RK3568_CLKSEL_CON(28), 8, 2, MFLAGS,
640 COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0, RK3568_CLKSEL_CON(28), 12, 3, MFLAGS, RK3568_CLKGATE_CON(9),
647 COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0, RK3568_CLKSEL_CON(29), 0, 2, MFLAGS, RK3568_CLKGATE_CON(10),
677 COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0, RK3568_CLKSEL_CON(29), 8, 1, MFLAGS,
681 COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0, RK3568_CLKSEL_CON(29), 9, 1, MFLAGS,
683 COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0, RK3568_CLKSEL_CON(29), 13, 1, MFLAGS,
688 COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0, RK3568_CLKSEL_CON(30), 0, 2, MFLAGS,
691 MFLAGS, RK3568_CLKGATE_CON(14), 9, GFLAGS),
695 COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0, RK3568_CLKSEL_CON(30), 8, 3, MFLAGS,
701 COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0, RK3568_CLKSEL_CON(30), 12, 3, MFLAGS,
706 COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0, RK3568_CLKSEL_CON(31), 8, 2, MFLAGS,
709 MFLAGS, RK3568_CLKGATE_CON(15), 8, GFLAGS),
713 COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0, RK3568_CLKSEL_CON(32), 0, 2, MFLAGS,
716 MFLAGS, RK3568_CLKGATE_CON(16), 1, GFLAGS),
724 COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0, RK3568_CLKSEL_CON(32), 8, 3, MFLAGS,
731 COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0, RK3568_CLKSEL_CON(33), 8, 2, MFLAGS,
734 MFLAGS, RK3568_CLKGATE_CON(17), 6, GFLAGS),
736 COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0, RK3568_CLKSEL_CON(33), 12, 2, MFLAGS,
739 1, MFLAGS),
745 MFLAGS),
746 MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0, RK3568_CLKSEL_CON(33), 3, 1, MFLAGS),
748 MFLAGS),
752 RK3568_CLKSEL_CON(10), 4, 2, MFLAGS, RK3568_CLKGATE_CON(14), 0, GFLAGS),
754 RK3568_CLKSEL_CON(10), 6, 2, MFLAGS, RK3568_CLKGATE_CON(14), 1, GFLAGS),
757 COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0, RK3568_CLKSEL_CON(34), 0, 2, MFLAGS,
765 COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0, RK3568_CLKSEL_CON(34), 14, 2, MFLAGS,
770 COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0, RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
773 COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0, RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS,
775 COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0, RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS,
777 COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0, RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6,
781 COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0, RK3568_CLKSEL_CON(37), 0, 2, MFLAGS,
787 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0, RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
792 RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 10, GFLAGS),
794 RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 11, GFLAGS,
796 COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
808 COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0, RK3568_CLKSEL_CON(38), 8, 2, MFLAGS,
812 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0, RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS,
821 MFLAGS, RK3568_CLKGATE_CON(23), 0, GFLAGS),
828 COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0, RK3568_CLKSEL_CON(43), 2, 2, MFLAGS,
832 COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0, RK3568_CLKSEL_CON(43), 4, 2, MFLAGS,
835 COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0, RK3568_CLKSEL_CON(43), 6, 2, MFLAGS,
845 COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0, RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5,
851 COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0, RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5,
854 1, MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(25), 0, GFLAGS),
859 COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0, RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5,
862 14, 2, MFLAGS, 8, 5, DFLAGS, RK3568_CLKGATE_CON(25), 7, GFLAGS),
863 COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0, RK3568_CLKSEL_CON(49), 6, 2, MFLAGS,
868 2, MFLAGS, RK3568_CLKGATE_CON(26), 0, GFLAGS),
870 MFLAGS, RK3568_CLKGATE_CON(26), 1, GFLAGS),
872 COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0, RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3,
886 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
894 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
902 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
910 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
918 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
926 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
934 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
942 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
950 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
958 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS,
961 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS,
964 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS,
966 COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0, RK3568_CLKSEL_CON(71), 8, 2, MFLAGS, RK3568_CLKGATE_CON(32), 10,
979 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 0, 1, MFLAGS,
982 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 2, 1, MFLAGS,
985 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 4, 1, MFLAGS,
988 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 6, 1, MFLAGS,
991 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 8, 1, MFLAGS,
995 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 10, 1, MFLAGS,
999 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0, RK3568_CLKSEL_CON(72), 12, 1, MFLAGS,
1002 COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0, RK3568_CLKSEL_CON(72), 14, 1, MFLAGS,
1022 RK3568_CLKSEL_CON(73), 0, 2, MFLAGS, RK3568_CLKGATE_CON(33), 0, GFLAGS),
1024 RK3568_CLKSEL_CON(73), 4, 2, MFLAGS, RK3568_CLKGATE_CON(33), 1, GFLAGS),
1026 MFLAGS, RK3568_CLKGATE_CON(33), 2, GFLAGS),
1028 MFLAGS, RK3568_CLKGATE_CON(33), 3, GFLAGS),
1031 MFLAGS, RK3568_CLKGATE_CON(33), 9, GFLAGS),
1050 MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS),
1066 COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0, RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0,
1074 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0, RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS,
1077 COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0, RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
1086 MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS),
1088 MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS),
1090 MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS),
1092 MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS),
1096 MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS),
1101 MFLAGS),
1106 MFLAGS),
1111 MFLAGS),
1115 MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
1117 MUXPMUGRF(SCLK_32K_IOE, "clk_32k_ioe", clk_32k_ioe_p, 0, RK3568_PMU_GRF_SOC_CON0, 0, 1, MFLAGS)};