xref: /device/soc/rockchip/common/vendor/drivers/clk/clk-rk1808.c

190 #define MFLAGS CLK_MUX_HIWORD_MASK
195     MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(39), 14, 2, MFLAGS);
198     MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(42), 14, 2, MFLAGS);
201     MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(45), 14, 2, MFLAGS);
204     MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(48), 14, 2, MFLAGS);
207     MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(51), 14, 2, MFLAGS);
210     MUX(0, "clk_uart6_mux", mux_uart6_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(54), 14, 2, MFLAGS);
213     MUX(0, "clk_uart7_mux", mux_uart7_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(57), 14, 2, MFLAGS);
216     MUX(0, "dclk_vopraw_mux", mux_dclk_vopraw_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(5), 14, 2, MFLAGS);
219     MUX(0, "dclk_voplite_mux", mux_dclk_voplite_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(7), 14, 2, MFLAGS);
222     MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(30), 15, 1, MFLAGS);
226         2, MFLAGS);
230         2, MFLAGS);
233     MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(36), 10, 2, MFLAGS);
236     SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT, RK1808_PMU_CLKSEL_CON(0), 14, 2, MFLAGS);
239     MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT, RK1808_PMU_CLKSEL_CON(4), 14, 2, MFLAGS);
246     MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, RK1808_MODE_CON, 10, 2, MFLAGS),
272     COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL, RK1808_CLKSEL_CON(15), 11, 1, MFLAGS, 12,
280     COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 5, DFLAGS,
292     COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_OPS_PARENT_ENABLE, RK1808_CLKSEL_CON(1), 8, 2, MFLAGS, 0, 4,
295                              MFLAGS, 4, 4, DFLAGS),
296     MUX(0, "clk_npu_pre", mux_npu_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(1), 15, 1, MFLAGS),
300     COMPOSITE(0, "aclk_npu_pre", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(2), 14, 1, MFLAGS, 0, 4, DFLAGS,
302     COMPOSITE(0, "hclk_npu_pre", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 4, DFLAGS,
313     COMPOSITE(ACLK_IMEM_PRE, "aclk_imem_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL, RK1808_CLKSEL_CON(17), 7, 1, MFLAGS, 0,
324     COMPOSITE(HSCLK_IMEM, "hsclk_imem", mux_gpll_cpll_p, CLK_IS_CRITICAL, RK1808_CLKSEL_CON(17), 15, 1, MFLAGS, 8, 5,
343     COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddr_p, CLK_IGNORE_UNUSED, RK1808_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5,
360     COMPOSITE(HSCLK_VIO, "hsclk_vio", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(4), 7, 1, MFLAGS, 0, 5, DFLAGS,
380     COMPOSITE(0, "dclk_vopraw_src", mux_cpll_gpll_npll_p, 0, RK1808_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 8, DFLAGS,
386     COMPOSITE(0, "dclk_voplite_src", mux_cpll_gpll_npll_p, 0, RK1808_CLKSEL_CON(7), 10, 2, MFLAGS, 0, 8, DFLAGS,
395     COMPOSITE(SCLK_RGA, "clk_rga", mux_gpll_cpll_npll_p, 0, RK1808_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
398     COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0, RK1808_CLKSEL_CON(10), 14, 2, MFLAGS, 8, 5, DFLAGS,
401     COMPOSITE(DCLK_CIF, "dclk_cif", mux_cpll_gpll_npll_p, 0, RK1808_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
404     COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_24m_npll_gpll_usb480m_p, 0, RK1808_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6,
412     COMPOSITE_NODIV(0, "clk_pcie_src", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(12), 15, 1, MFLAGS, RK1808_CLKGATE_CON(5),
423     COMPOSITE(ACLK_PCIE, "aclk_pcie", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(15), 8, 1, MFLAGS, 0, 4, DFLAGS,
433     COMPOSITE(0, "clk_pcie_aux_src", mux_cpll_gpll_npll_p, 0, RK1808_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
436                     MFLAGS, RK1808_CLKGATE_CON(5), 4, GFLAGS),
441               MFLAGS, 0, 10, DFLAGS, RK1808_CLKGATE_CON(5), 2, GFLAGS),
449     COMPOSITE_NODIV(0, "clk_peri_src", mux_gpll_cpll_p, CLK_IS_CRITICAL, RK1808_CLKSEL_CON(19), 15, 1, MFLAGS,
466               MFLAGS, 0, 8, DFLAGS, RK1808_CLKGATE_CON(9), 1, GFLAGS),
468                          RK1808_CLKSEL_CON(22), 14, 2, MFLAGS, RK1808_CLKSEL_CON(23), 0, 8, DFLAGS,
471                     RK1808_CLKSEL_CON(23), 15, 1, MFLAGS, RK1808_CLKGATE_CON(9), 3, GFLAGS),
477               MFLAGS, 0, 8, DFLAGS, RK1808_CLKGATE_CON(9), 4, GFLAGS),
479                          RK1808_CLKSEL_CON(24), 14, 2, MFLAGS, RK1808_CLKSEL_CON(25), 0, 8, DFLAGS,
482                     RK1808_CLKSEL_CON(25), 15, 1, MFLAGS, RK1808_CLKGATE_CON(9), 6, GFLAGS),
487               2, MFLAGS, 0, 8, DFLAGS, RK1808_CLKGATE_CON(9), 7, GFLAGS),
489                          RK1808_CLKSEL_CON(20), 14, 2, MFLAGS, RK1808_CLKSEL_CON(21), 0, 8, DFLAGS,
492                     RK1808_CLKSEL_CON(21), 15, 1, MFLAGS, RK1808_CLKGATE_CON(9), 9, GFLAGS),
496     COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 7, DFLAGS,
512     COMPOSITE(SCLK_GMAC_OUT, "clk_gmac_out", mux_cpll_npll_ppll_p, 0, RK1808_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5,
515     COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_cpll_npll_ppll_p, 0, RK1808_CLKSEL_CON(26), 14, 2, MFLAGS, 8, 5,
518         MFLAGS),
528         RK1808_CLKSEL_CON(27), 2, 2, MFLAGS),
530         1, 1, MFLAGS),
531     MUX(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", mux_gmac_rx_tx_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(27), 4, 1, MFLAGS),
539     COMPOSITE_NODIV(0, "clk_bus_src", mux_gpll_cpll_p, CLK_IS_CRITICAL, RK1808_CLKSEL_CON(27), 15, 1, MFLAGS,
589     COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 5, DFLAGS,
591     COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(29), 15, 1, MFLAGS, 8, 5, DFLAGS,
594     COMPOSITE(0, "clk_uart1_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 7, DFLAGS,
602     COMPOSITE(0, "clk_uart2_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(41), 14, 2, MFLAGS, 0, 7, DFLAGS,
610     COMPOSITE(0, "clk_uart3_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(44), 14, 2, MFLAGS, 0, 7, DFLAGS,
618     COMPOSITE(0, "clk_uart4_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(47), 14, 2, MFLAGS, 0, 7, DFLAGS,
626     COMPOSITE(0, "clk_uart5_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(50), 14, 2, MFLAGS, 0, 7, DFLAGS,
634     COMPOSITE(0, "clk_uart6_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(53), 14, 2, MFLAGS, 0, 7, DFLAGS,
642     COMPOSITE(0, "clk_uart7_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 7, DFLAGS,
650     COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
652     COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
654     COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
656     COMPOSITE(SCLK_I2C4, "clk_i2c4", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 7, DFLAGS,
658     COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(71), 15, 1, MFLAGS, 8, 7, DFLAGS,
661     COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
663     COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
665     COMPOSITE(SCLK_SPI2, "clk_spi2", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
673     COMPOSITE(SCLK_EFUSE_S, "clk_efuse_s", mux_gpll_cpll_xin24m_p, 0, RK1808_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 6, DFLAGS,
675     COMPOSITE(SCLK_EFUSE_NS, "clk_efuse_ns", mux_gpll_cpll_xin24m_p, 0, RK1808_CLKSEL_CON(64), 14, 2, MFLAGS, 8, 6,
678     COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(65), 15, 1, MFLAGS, 0, 11, DFLAGS,
680     COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(66), 15, 1, MFLAGS, 0, 11, DFLAGS,
682     COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(67), 15, 1, MFLAGS, 0, 11, DFLAGS,
684     COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(68), 15, 1, MFLAGS, 0, 11, DFLAGS,
687     COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(69), 7, 1, MFLAGS, 0, 7, DFLAGS,
689     COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(69), 15, 1, MFLAGS, 8, 7, DFLAGS,
691     COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 7, DFLAGS,
713     COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_cpll_npll_p, 0, RK1808_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 7, DFLAGS,
719     COMPOSITE(SCLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_gpll_cpll_npll_p, 0, RK1808_CLKSEL_CON(32), 8, 2, MFLAGS,
724                     RK1808_CLKSEL_CON(32), 12, 1, MFLAGS, RK1808_CLKGATE_CON(17), 14, GFLAGS),
726                     RK1808_CLKSEL_CON(32), 14, 2, MFLAGS, RK1808_CLKGATE_CON(17), 15, GFLAGS),
728     COMPOSITE(SCLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_gpll_cpll_npll_p, 0, RK1808_CLKSEL_CON(34), 8, 2, MFLAGS,
733                     RK1808_CLKSEL_CON(34), 12, 1, MFLAGS, RK1808_CLKGATE_CON(18), 2, GFLAGS),
735                     RK1808_CLKSEL_CON(34), 14, 2, MFLAGS, RK1808_CLKGATE_CON(18), 3, GFLAGS),
737     COMPOSITE(SCLK_I2S1_2CH_SRC, "clk_i2s1_2ch_src", mux_gpll_cpll_npll_p, 0, RK1808_CLKSEL_CON(36), 8, 2, MFLAGS, 0, 7,
743                     RK1808_CLKSEL_CON(36), 15, 1, MFLAGS, RK1808_CLKGATE_CON(18), 7, GFLAGS),
776                     MFLAGS, RK1808_PMU_CLKGATE_CON(0), 15, GFLAGS),
778     COMPOSITE(0, "clk_uart0_pmu_src", mux_gpll_usb480m_cpll_ppll_p, 0, RK1808_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7,
789     COMPOSITE(SCLK_PMU_I2C0, "clk_pmu_i2c0", mux_ppll_xin24m_p, 0, RK1808_PMU_CLKSEL_CON(7), 15, 1, MFLAGS, 8, 7,
792     COMPOSITE(DBCLK_PMU_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0, RK1808_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 11,
798                     6, 1, MFLAGS, RK1808_PMU_CLKGATE_CON(1), 9, GFLAGS),
800                     RK1808_PMU_CLKSEL_CON(2), 7, 1, MFLAGS, RK1808_PMU_CLKGATE_CON(1), 10, GFLAGS),
806                     RK1808_PMU_CLKSEL_CON(7), 4, 1, MFLAGS, RK1808_PMU_CLKGATE_CON(1), 12, GFLAGS),
821     MUXPMUGRF(SCLK_32K_IOE, "clk_32k_ioe", mux_clk_32k_ioe_p, 0, RK1808_PMUGRF_SOC_CON0, 0, 1, MFLAGS)};

Indexes created Thu Nov 07 10:32:03 CST 2024