1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
4 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/io.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <dt-bindings/clock/rk3399-cru.h>
16 #include "clk.h"
17
18 #define RK3399_I2S_FRAC_MAX_PRATE 800000000
19 #define RK3399_UART_FRAC_MAX_PRATE 800000000
20 #define RK3399_SPDIF_FRAC_MAX_PRATE 600000000
21 #define RK3399_VOP_FRAC_MAX_PRATE 600000000
22 #define RK3399_WIFI_FRAC_MAX_PRATE 600000000
23
24 enum rk3399_plls {
25 lpll,
26 bpll,
27 dpll,
28 cpll,
29 gpll,
30 npll,
31 vpll,
32 };
33
34 enum rk3399_pmu_plls {
35 ppll,
36 };
37
38 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
39 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
40 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
41 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
42 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
43 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
44 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
58 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
59 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
60 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
61 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
62 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
63 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
64 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
65 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
66 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
67 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
68 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), RK3036_PLL_RATE(800000000, 1, 100, 3, 1, 1, 0),
69 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
70 RK3036_PLL_RATE(676000000, 3, 169, 2, 1, 1, 0), RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
71 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), RK3036_PLL_RATE(533250000, 8, 711, 4, 1, 1, 0),
72 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
73 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
74 RK3036_PLL_RATE(297000000, 1, 99, 4, 2, 1, 0), RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
75 RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), RK3036_PLL_RATE(106500000, 1, 71, 4, 4, 1, 0),
76 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
77 RK3036_PLL_RATE(65000000, 1, 65, 6, 4, 1, 0), RK3036_PLL_RATE(54000000, 1, 54, 6, 4, 1, 0),
78 RK3036_PLL_RATE(27000000, 1, 27, 6, 4, 1, 0), {},
79 };
80
81 static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
82 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
83 RK3036_PLL_RATE(594000000, 1, 123, 5, 1, 0, 12582912), /* vco = 2970000000 */
84 RK3036_PLL_RATE(593406593, 1, 123, 5, 1, 0, 10508804), /* vco = 2967032965 */
85 RK3036_PLL_RATE(297000000, 1, 123, 5, 2, 0, 12582912), /* vco = 2970000000 */
86 RK3036_PLL_RATE(296703297, 1, 123, 5, 2, 0, 10508807), /* vco = 2967032970 */
87 RK3036_PLL_RATE(148500000, 1, 129, 7, 3, 0, 15728640), /* vco = 3118500000 */
88 RK3036_PLL_RATE(148351648, 1, 123, 5, 4, 0, 10508800), /* vco = 2967032960 */
89 RK3036_PLL_RATE(106500000, 1, 124, 7, 4, 0, 4194304), /* vco = 2982000000 */
90 RK3036_PLL_RATE(74250000, 1, 129, 7, 6, 0, 15728640), /* vco = 3118500000 */
91 RK3036_PLL_RATE(74175824, 1, 129, 7, 6, 0, 13550823), /* vco = 3115384608 */
92 RK3036_PLL_RATE(65000000, 1, 113, 7, 6, 0, 12582912), /* vco = 2730000000 */
93 RK3036_PLL_RATE(59340659, 1, 121, 7, 7, 0, 2581098), /* vco = 2907692291 */
94 RK3036_PLL_RATE(54000000, 1, 110, 7, 7, 0, 4194304), /* vco = 2646000000 */
95 RK3036_PLL_RATE(27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 */
96 RK3036_PLL_RATE(26973027, 1, 55, 7, 7, 0, 1173232), /* vco = 1321678323 */
97 {},
98 };
99
100 /* CRU parents */
101 PNAME(mux_pll_p) = {"xin24m", "xin32k"};
102
103 PNAME(mux_ddrclk_p) = {"clk_ddrc_lpll_src", "clk_ddrc_bpll_src", "clk_ddrc_dpll_src", "clk_ddrc_gpll_src"};
104
105 PNAME(mux_pll_src_vpll_cpll_gpll_p) = {"vpll", "cpll", "gpll"};
106 PNAME(mux_pll_src_dmyvpll_cpll_gpll_p) = {"dummy_vpll", "cpll", "gpll"};
107
108 #ifdef RK3399_TWO_PLL_FOR_VOP
109 PNAME(mux_aclk_cci_p) = {"dummy_cpll", "gpll_aclk_cci_src", "npll_aclk_cci_src", "dummy_vpll"};
110 PNAME(mux_cci_trace_p) = {"dummy_cpll", "gpll_cci_trace"};
111 PNAME(mux_cs_p) = {"dummy_cpll", "gpll_cs", "npll_cs"};
112 PNAME(mux_aclk_perihp_p) = {"dummy_cpll", "gpll_aclk_perihp_src"};
113
114 PNAME(mux_pll_src_cpll_gpll_p) = {"dummy_cpll", "gpll"};
115 PNAME(mux_pll_src_cpll_gpll_npll_p) = {"dummy_cpll", "gpll", "npll"};
116 PNAME(mux_pll_src_cpll_gpll_ppll_p) = {"dummy_cpll", "gpll", "ppll"};
117 PNAME(mux_pll_src_cpll_gpll_upll_p) = {"dummy_cpll", "gpll", "upll"};
118 PNAME(mux_pll_src_npll_cpll_gpll_p) = {"npll", "dummy_cpll", "gpll"};
119 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = {"dummy_cpll", "gpll", "npll", "ppll"};
120 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = {"dummy_cpll", "gpll", "npll", "xin24m"};
121 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = {"dummy_cpll", "gpll", "npll", "clk_usbphy_480m"};
122 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = {"ppll", "dummy_cpll", "gpll", "npll", "upll"};
123 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = {"dummy_cpll", "gpll", "npll", "upll", "xin24m"};
124 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = {"dummy_cpll", "gpll", "npll", "ppll", "upll", "xin24m"};
125 /*
126 * We hope to be able to HDMI/DP can obtain better signal quality,
127 * therefore, we move VOP pwm and aclk clocks to other PLLs, let
128 * HDMI/DP phyclock can monopolize VPLL.
129 */
130 PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = {"dummy_vpll", "dummy_cpll", "gpll", "npll"};
131 PNAME(mux_pll_src_dmyvpll_cpll_gpll_gpll_p) = {"dummy_vpll", "dummy_cpll", "gpll", "gpll"};
132 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = {"xin24m", "xin32k", "dummy_cpll", "gpll"};
133
134 PNAME(mux_aclk_emmc_p) = {"dummy_cpll", "gpll_aclk_emmc_src"};
135
136 PNAME(mux_aclk_perilp0_p) = {"dummy_cpll", "gpll_aclk_perilp0_src"};
137
138 PNAME(mux_fclk_cm0s_p) = {"dummy_cpll", "gpll_fclk_cm0s_src"};
139
140 PNAME(mux_hclk_perilp1_p) = {"dummy_cpll", "gpll_hclk_perilp1_src"};
141 PNAME(mux_aclk_gmac_p) = {"dummy_cpll", "gpll_aclk_gmac_src"};
142 #else
143 PNAME(mux_aclk_cci_p) = {"cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", "dummy_vpll"};
144 PNAME(mux_cci_trace_p) = {"cpll_cci_trace", "gpll_cci_trace"};
145 PNAME(mux_cs_p) = {"cpll_cs", "gpll_cs", "npll_cs"};
146 PNAME(mux_aclk_perihp_p) = {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src"};
147
148 PNAME(mux_pll_src_cpll_gpll_p) = {"cpll", "gpll"};
149 PNAME(mux_pll_src_cpll_gpll_npll_p) = {"cpll", "gpll", "npll"};
150 PNAME(mux_pll_src_cpll_gpll_ppll_p) = {"cpll", "gpll", "ppll"};
151 PNAME(mux_pll_src_cpll_gpll_upll_p) = {"cpll", "gpll", "upll"};
152 PNAME(mux_pll_src_npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};
153 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = {"cpll", "gpll", "npll", "ppll"};
154 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = {"cpll", "gpll", "npll", "xin24m"};
155 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = {"cpll", "gpll", "npll", "clk_usbphy_480m"};
156 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = {"ppll", "cpll", "gpll", "npll", "upll"};
157 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = {"cpll", "gpll", "npll", "upll", "xin24m"};
158 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = {"cpll", "gpll", "npll", "ppll", "upll", "xin24m"};
159 /*
160 * We hope to be able to HDMI/DP can obtain better signal quality,
161 * therefore, we move VOP pwm and aclk clocks to other PLLs, let
162 * HDMI/DP phyclock can monopolize VPLL.
163 */
164 PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = {"dummy_vpll", "cpll", "gpll", "npll"};
165 PNAME(mux_pll_src_dmyvpll_cpll_gpll_gpll_p) = {"dummy_vpll", "cpll", "gpll", "gpll"};
166 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = {"xin24m", "xin32k", "cpll", "gpll"};
167
168 PNAME(mux_aclk_emmc_p) = {"cpll_aclk_emmc_src", "gpll_aclk_emmc_src"};
169
170 PNAME(mux_aclk_perilp0_p) = {"cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src"};
171
172 PNAME(mux_fclk_cm0s_p) = {"cpll_fclk_cm0s_src", "gpll_fclk_cm0s_src"};
173
174 PNAME(mux_hclk_perilp1_p) = {"cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src"};
175 PNAME(mux_aclk_gmac_p) = {"cpll_aclk_gmac_src", "gpll_aclk_gmac_src"};
176 #endif
177
178 PNAME(mux_dclk_vop0_p) = {"dclk_vop0_div", "dummy_dclk_vop0_frac"};
179 PNAME(mux_dclk_vop1_p) = {"dclk_vop1_div", "dummy_dclk_vop1_frac"};
180
181 PNAME(mux_clk_cif_p) = {"clk_cifout_src", "xin24m"};
182
183 PNAME(mux_pll_src_24m_usbphy480m_p) = {"xin24m", "clk_usbphy_480m"};
184 PNAME(mux_pll_src_24m_pciephy_p) = {"xin24m", "clk_pciephy_ref100m"};
185 PNAME(mux_pciecore_cru_phy_p) = {"clk_pcie_core_cru", "clk_pcie_core_phy"};
186 PNAME(mux_clk_testout1_p) = {"clk_testout1_pll_src", "xin24m"};
187 PNAME(mux_clk_testout2_p) = {"clk_testout2_pll_src", "xin24m"};
188
189 PNAME(mux_usbphy_480m_p) = {"clk_usbphy0_480m_src", "clk_usbphy1_480m_src"};
190 PNAME(mux_rmii_p) = {"clk_gmac", "clkin_gmac"};
191 PNAME(mux_spdif_p) = {"clk_spdif_div", "clk_spdif_frac", "clkin_i2s", "xin12m"};
192 PNAME(mux_i2s0_p) = {"clk_i2s0_div", "clk_i2s0_frac", "clkin_i2s", "xin12m"};
193 PNAME(mux_i2s1_p) = {"clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s", "xin12m"};
194 PNAME(mux_i2s2_p) = {"clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s", "xin12m"};
195 PNAME(mux_i2sch_p) = {"clk_i2s0", "clk_i2s1", "clk_i2s2"};
196 PNAME(mux_i2sout_p) = {"clk_i2sout_src", "xin12m"};
197
198 PNAME(mux_uart0_p) = {"xin24m", "clk_uart0_div", "clk_uart0_frac"};
199 PNAME(mux_uart1_p) = {"xin24m", "clk_uart1_div", "clk_uart1_frac"};
200 PNAME(mux_uart2_p) = {"xin24m", "clk_uart2_div", "clk_uart2_frac"};
201 PNAME(mux_uart3_p) = {"xin24m", "clk_uart3_div", "clk_uart3_frac"};
202
203 /* PMU CRU parents */
204 PNAME(mux_ppll_24m_p) = {"ppll", "xin24m"};
205 PNAME(mux_24m_ppll_p) = {"xin24m", "ppll"};
206 PNAME(mux_fclk_cm0s_pmu_ppll_p) = {"fclk_cm0s_pmu_ppll_src", "xin24m"};
207 PNAME(mux_wifi_pmu_p) = {"clk_wifi_div", "clk_wifi_frac"};
208 PNAME(mux_uart4_pmu_p) = {"xin24m", "clk_uart4_div", "clk_uart4_frac"};
209 PNAME(mux_clk_testout2_2io_p) = {"clk_testout2", "clk_32k_suspend_pmu"};
210
211 static u32 uart_mux_idx[] = {2, 0, 1};
212
213 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
214 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0), RK3399_PLL_CON(3), 8, 31, 0,
215 rk3399_pll_rates),
216 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8), RK3399_PLL_CON(11), 8, 31, 0,
217 rk3399_pll_rates),
218 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16), RK3399_PLL_CON(19), 8, 31, 0, NULL),
219 #ifdef RK3399_TWO_PLL_FOR_VOP
220 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), RK3399_PLL_CON(27), 8, 31, 0,
221 rk3399_pll_rates),
222 #else
223 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), RK3399_PLL_CON(27), 8, 31,
224 ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
225 #endif
226 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32), RK3399_PLL_CON(35), 8, 31, 0,
227 rk3399_pll_rates),
228 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), RK3399_PLL_CON(43), 8, 31,
229 ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
230 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), RK3399_PLL_CON(51), 8, 31, 0,
231 rk3399_vpll_rates),
232 };
233
234 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
235 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, CLK_IS_CRITICAL, RK3399_PMU_PLL_CON(0), RK3399_PMU_PLL_CON(3),
236 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
237 };
238
239 #define MFLAGS CLK_MUX_HIWORD_MASK
240 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
241 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
242 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
243
244 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
245 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
246
247 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
248 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
249
250 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
251 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
252
253 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
254 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
255
256 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata = MUXTBL(
257 SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(33), 8, 2, MFLAGS, uart_mux_idx);
258
259 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata = MUXTBL(
260 SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(34), 8, 2, MFLAGS, uart_mux_idx);
261
262 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata = MUXTBL(
263 SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(35), 8, 2, MFLAGS, uart_mux_idx);
264
265 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata = MUXTBL(
266 SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(36), 8, 2, MFLAGS, uart_mux_idx);
267
268 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
269 MUXTBL(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT, RK3399_PMU_CLKSEL_CON(5), 8, 2,
270 MFLAGS, uart_mux_idx);
271
272 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
273 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
274
275 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
276 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
277
278 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
279 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
280
281 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
282 .core_reg[0] = RK3399_CLKSEL_CON(0),
283 .div_core_shift[0] = 0,
284 .div_core_mask[0] = 0x1f,
285 .num_cores = 1,
286 .mux_core_alt = 3,
287 .mux_core_main = 0,
288 .mux_core_shift = 6,
289 .mux_core_mask = 0x3,
290 };
291
292 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
293 .core_reg[0] = RK3399_CLKSEL_CON(2),
294 .div_core_shift[0] = 0,
295 .div_core_mask[0] = 0x1f,
296 .num_cores = 1,
297 .mux_core_alt = 3,
298 .mux_core_main = 1,
299 .mux_core_shift = 6,
300 .mux_core_mask = 0x3,
301 };
302
303 #define RK3399_DIV_ACLKM_MASK 0x1f
304 #define RK3399_DIV_ACLKM_SHIFT 8
305 #define RK3399_DIV_ATCLK_MASK 0x1f
306 #define RK3399_DIV_ATCLK_SHIFT 0
307 #define RK3399_DIV_PCLK_DBG_MASK 0x1f
308 #define RK3399_DIV_PCLK_DBG_SHIFT 8
309
310 #define RK3399_CLKSEL0(_offs, _aclkm) \
311 { \
312 .reg = RK3399_CLKSEL_CON(0 + (_offs)), \
313 .val = HIWORD_UPDATE((_aclkm), RK3399_DIV_ACLKM_MASK, RK3399_DIV_ACLKM_SHIFT), \
314 }
315 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
316 { \
317 .reg = RK3399_CLKSEL_CON(1 + (_offs)), \
318 .val = HIWORD_UPDATE((_atclk), RK3399_DIV_ATCLK_MASK, RK3399_DIV_ATCLK_SHIFT) | \
319 HIWORD_UPDATE((_pdbg), RK3399_DIV_PCLK_DBG_MASK, RK3399_DIV_PCLK_DBG_SHIFT), \
320 }
321
322 /* cluster_l: aclkm in clksel0, rest in clksel1 */
323 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
324 { \
325 .prate = _prate##U, \
326 .divs = { \
327 RK3399_CLKSEL0(0, (_aclkm)), \
328 RK3399_CLKSEL1(0, (_atclk), (_pdbg)), \
329 }, \
330 }
331
332 /* cluster_b: aclkm in clksel2, rest in clksel3 */
333 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
334 { \
335 .prate = _prate##U, \
336 .divs = { \
337 RK3399_CLKSEL0(2, (_aclkm)), \
338 RK3399_CLKSEL1(2, (_atclk), (_pdbg)), \
339 }, \
340 }
341
342 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
343 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8), RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
344 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7), RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
345 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6), RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
346 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5), RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
347 RK3399_CPUCLKL_RATE(816000000, 1, 4, 4), RK3399_CPUCLKL_RATE(696000000, 1, 3, 3),
348 RK3399_CPUCLKL_RATE(600000000, 1, 3, 3), RK3399_CPUCLKL_RATE(408000000, 1, 2, 2),
349 RK3399_CPUCLKL_RATE(312000000, 1, 1, 1), RK3399_CPUCLKL_RATE(216000000, 1, 1, 1),
350 RK3399_CPUCLKL_RATE(96000000, 1, 1, 1),
351 };
352
353 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
354 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11), RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
355 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10), RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
356 RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9), RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
357 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9), RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
358 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8), RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
359 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7), RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
360 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6), RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
361 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5), RK3399_CPUCLKB_RATE(816000000, 1, 4, 4),
362 RK3399_CPUCLKB_RATE(696000000, 1, 3, 3), RK3399_CPUCLKB_RATE(600000000, 1, 3, 3),
363 RK3399_CPUCLKB_RATE(408000000, 1, 2, 2), RK3399_CPUCLKB_RATE(312000000, 1, 1, 1),
364 RK3399_CPUCLKB_RATE(216000000, 1, 1, 1), RK3399_CPUCLKB_RATE(96000000, 1, 1, 1),
365 };
366
367 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
368 /*
369 * CRU Clock-Architecture
370 */
371
372 /* usbphy */
373 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(6), 5, GFLAGS),
374 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(6), 6, GFLAGS),
375
376 GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(13),
377 12, GFLAGS),
378 GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(13),
379 12, GFLAGS),
380 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0, RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
381
382 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0, RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
383
384 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0, RK3399_CLKSEL_CON(19), 0,
385 2, MFLAGS, RK3399_CLKGATE_CON(6), 4, GFLAGS),
386
387 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5,
388 DFLAGS, RK3399_CLKGATE_CON(12), 0, GFLAGS),
389 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(30), 0, GFLAGS),
390 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0, RK3399_CLKGATE_CON(30), 1, GFLAGS),
391 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0, RK3399_CLKGATE_CON(30), 2, GFLAGS),
392 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0, RK3399_CLKGATE_CON(30), 3, GFLAGS),
393 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0, RK3399_CLKGATE_CON(30), 4, GFLAGS),
394
395 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, RK3399_CLKGATE_CON(12), 1, GFLAGS),
396 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, RK3399_CLKGATE_CON(12), 2, GFLAGS),
397
398 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0, RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10,
399 DFLAGS, RK3399_CLKGATE_CON(12), 3, GFLAGS),
400
401 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0, RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10,
402 DFLAGS, RK3399_CLKGATE_CON(12), 4, GFLAGS),
403
404 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0, RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5,
405 DFLAGS, RK3399_CLKGATE_CON(13), 4, GFLAGS),
406
407 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, RK3399_CLKSEL_CON(64), 6,
408 2, MFLAGS, 0, 5, DFLAGS, RK3399_CLKGATE_CON(13), 5, GFLAGS),
409
410 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0, RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5,
411 DFLAGS, RK3399_CLKGATE_CON(13), 6, GFLAGS),
412
413 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, RK3399_CLKSEL_CON(65), 6,
414 2, MFLAGS, 0, 5, DFLAGS, RK3399_CLKGATE_CON(13), 7, GFLAGS),
415
416 /* little core */
417 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(0), 0, GFLAGS),
418 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(0), 1, GFLAGS),
419 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(0), 2, GFLAGS),
420 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(0), 3, GFLAGS),
421
422 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(0), 8, 5,
423 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3399_CLKGATE_CON(0), 4, GFLAGS),
424 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(1), 0, 5,
425 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3399_CLKGATE_CON(0), 5, GFLAGS),
426 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(1), 8, 5,
427 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3399_CLKGATE_CON(0), 6, GFLAGS),
428
429 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
430 RK3399_CLKGATE_CON(14), 12, GFLAGS),
431 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(14), 13, GFLAGS),
432
433 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(14), 9, GFLAGS),
434 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
435 RK3399_CLKGATE_CON(14), 10, GFLAGS),
436 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
437 RK3399_CLKGATE_CON(14), 11, GFLAGS),
438 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, RK3399_CLKGATE_CON(0), 7, GFLAGS),
439
440 /* big core */
441 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 0, GFLAGS),
442 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 1, GFLAGS),
443 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 2, GFLAGS),
444 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 3, GFLAGS),
445
446 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(2), 8, 5,
447 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3399_CLKGATE_CON(1), 4, GFLAGS),
448 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(3), 0, 5,
449 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3399_CLKGATE_CON(1), 5, GFLAGS),
450 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(3), 8, 5,
451 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3399_CLKGATE_CON(1), 6, GFLAGS),
452
453 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
454 RK3399_CLKGATE_CON(14), 5, GFLAGS),
455 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(14), 6, GFLAGS),
456
457 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(14), 1, GFLAGS),
458 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
459 RK3399_CLKGATE_CON(14), 3, GFLAGS),
460 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
461 RK3399_CLKGATE_CON(14), 4, GFLAGS),
462
463 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(3), 13, 2,
464 DFLAGS | CLK_DIVIDER_READ_ONLY),
465
466 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(14), 2, GFLAGS),
467
468 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0, RK3399_CLKGATE_CON(1), 7, GFLAGS),
469
470 /* gmac */
471 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(6), 9, GFLAGS),
472 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(6), 8, GFLAGS),
473 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0, RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
474 RK3399_CLKGATE_CON(6), 10, GFLAGS),
475
476 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0, RK3399_CLKGATE_CON(32), 0, GFLAGS),
477 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(32), 1, GFLAGS),
478 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0, RK3399_CLKGATE_CON(32), 4, GFLAGS),
479
480 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, RK3399_CLKSEL_CON(19), 8, 3, DFLAGS, RK3399_CLKGATE_CON(6),
481 11, GFLAGS),
482 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0, RK3399_CLKGATE_CON(32), 2, GFLAGS),
483 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(32), 3, GFLAGS),
484
485 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
486 RK3399_CLKGATE_CON(5), 5, GFLAGS),
487
488 MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
489 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0, RK3399_CLKGATE_CON(5), 6, GFLAGS),
490 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0, RK3399_CLKGATE_CON(5), 7, GFLAGS),
491 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0, RK3399_CLKGATE_CON(5), 8, GFLAGS),
492 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0, RK3399_CLKGATE_CON(5), 9, GFLAGS),
493
494 /* spdif */
495 COMPOSITE(SCLK_SPDIF_DIV, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7,
496 DFLAGS, RK3399_CLKGATE_CON(8), 13, GFLAGS),
497 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(99), 0,
498 RK3399_CLKGATE_CON(8), 14, GFLAGS, &rk3399_spdif_fracmux, RK3399_SPDIF_FRAC_MAX_PRATE),
499 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT, RK3399_CLKGATE_CON(8), 15, GFLAGS),
500
501 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(32), 15, 1,
502 MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(10), 6, GFLAGS),
503 /* i2s */
504 COMPOSITE(SCLK_I2S0_DIV, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7,
505 DFLAGS, RK3399_CLKGATE_CON(8), 3, GFLAGS),
506 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(96), 0,
507 RK3399_CLKGATE_CON(8), 4, GFLAGS, &rk3399_i2s0_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
508 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT, RK3399_CLKGATE_CON(8), 5, GFLAGS),
509
510 COMPOSITE(SCLK_I2S1_DIV, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7,
511 DFLAGS, RK3399_CLKGATE_CON(8), 6, GFLAGS),
512 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(97), 0,
513 RK3399_CLKGATE_CON(8), 7, GFLAGS, &rk3399_i2s1_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
514 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, RK3399_CLKGATE_CON(8), 8, GFLAGS),
515
516 COMPOSITE(SCLK_I2S2_DIV, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7,
517 DFLAGS, RK3399_CLKGATE_CON(8), 9, GFLAGS),
518 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(98), 0,
519 RK3399_CLKGATE_CON(8), 10, GFLAGS, &rk3399_i2s2_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
520 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, RK3399_CLKGATE_CON(8), 11, GFLAGS),
521
522 MUX(SCLK_I2SOUT_SRC, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
523 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(31), 2, 1,
524 MFLAGS, RK3399_CLKGATE_CON(8), 12, GFLAGS),
525
526 /* uart */
527 MUX(SCLK_UART0_SRC, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0, RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
528 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0, RK3399_CLKSEL_CON(33), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9),
529 0, GFLAGS),
530 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(100), 0,
531 RK3399_CLKGATE_CON(9), 1, GFLAGS, &rk3399_uart0_fracmux, RK3399_UART_FRAC_MAX_PRATE),
532
533 MUX(SCLK_UART_SRC, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
534 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0, RK3399_CLKSEL_CON(34), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9),
535 2, GFLAGS),
536 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(101), 0,
537 RK3399_CLKGATE_CON(9), 3, GFLAGS, &rk3399_uart1_fracmux, RK3399_UART_FRAC_MAX_PRATE),
538
539 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0, RK3399_CLKSEL_CON(35), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9),
540 4, GFLAGS),
541 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(102), 0,
542 RK3399_CLKGATE_CON(9), 5, GFLAGS, &rk3399_uart2_fracmux, RK3399_UART_FRAC_MAX_PRATE),
543
544 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0, RK3399_CLKSEL_CON(36), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9),
545 6, GFLAGS),
546 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(103), 0,
547 RK3399_CLKGATE_CON(9), 7, GFLAGS, &rk3399_uart3_fracmux, RK3399_UART_FRAC_MAX_PRATE),
548
549 COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL, RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5,
550 DFLAGS, RK3399_CLKGATE_CON(3), 4, GFLAGS),
551
552 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(18), 10, GFLAGS),
553 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0, RK3399_CLKGATE_CON(18), 12, GFLAGS),
554 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(18), 15, GFLAGS),
555 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(19), 2, GFLAGS),
556
557 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0, RK3399_CLKGATE_CON(4), 11, GFLAGS),
558 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0, RK3399_CLKGATE_CON(3), 5, GFLAGS),
559 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0, RK3399_CLKGATE_CON(3), 6, GFLAGS),
560
561 /* cci */
562 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(2), 0, GFLAGS),
563 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(2), 1, GFLAGS),
564 GATE(0, "npll_aclk_cci_src", "npll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(2), 2, GFLAGS),
565 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(2), 3, GFLAGS),
566
567 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IS_CRITICAL, RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
568 RK3399_CLKGATE_CON(2), 4, GFLAGS),
569
570 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(15), 0,
571 GFLAGS),
572 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(15), 1,
573 GFLAGS),
574 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(15), 2, GFLAGS),
575 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(15), 3, GFLAGS),
576 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(15), 4, GFLAGS),
577 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(15), 7, GFLAGS),
578
579 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(2), 5, GFLAGS),
580 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(2), 6, GFLAGS),
581 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(5), 15, 1, MFLAGS,
582 8, 5, DFLAGS, RK3399_CLKGATE_CON(2), 7, GFLAGS),
583
584 GATE(0, "cpll_cs", "cpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(2), 8, GFLAGS),
585 GATE(0, "gpll_cs", "gpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(2), 9, GFLAGS),
586 GATE(0, "npll_cs", "npll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(2), 10, GFLAGS),
587 COMPOSITE_NOGATE(SCLK_CS, "clk_cs", mux_cs_p, CLK_IS_CRITICAL, RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
588 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(15), 5, GFLAGS),
589 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(15), 6, GFLAGS),
590
591 /* vcodec */
592 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5,
593 DFLAGS, RK3399_CLKGATE_CON(4), 0, GFLAGS),
594 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
595 RK3399_CLKGATE_CON(4), 1, GFLAGS),
596 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, RK3399_CLKGATE_CON(17), 2, GFLAGS),
597 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(17), 3, GFLAGS),
598
599 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0, RK3399_CLKGATE_CON(17), 0, GFLAGS),
600 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(17), 1, GFLAGS),
601
602 /* vdu */
603 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5,
604 DFLAGS, RK3399_CLKGATE_CON(4), 4, GFLAGS),
605 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5,
606 DFLAGS, RK3399_CLKGATE_CON(4), 5, GFLAGS),
607
608 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
609 RK3399_CLKGATE_CON(4), 2, GFLAGS),
610 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0, RK3399_CLKSEL_CON(8), 8, 5, DFLAGS, RK3399_CLKGATE_CON(4), 3,
611 GFLAGS),
612 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0, RK3399_CLKGATE_CON(17), 10, GFLAGS),
613 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(17), 11, GFLAGS),
614
615 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0, RK3399_CLKGATE_CON(17), 8, GFLAGS),
616 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(17), 9, GFLAGS),
617
618 /* iep */
619 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5,
620 DFLAGS, RK3399_CLKGATE_CON(4), 6, GFLAGS),
621 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0, RK3399_CLKSEL_CON(10), 8, 5, DFLAGS, RK3399_CLKGATE_CON(4), 7,
622 GFLAGS),
623 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0, RK3399_CLKGATE_CON(16), 2, GFLAGS),
624 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(16), 3, GFLAGS),
625
626 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK3399_CLKGATE_CON(16), 0, GFLAGS),
627 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(16), 1, GFLAGS),
628
629 /* rga */
630 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0, RK3399_CLKSEL_CON(12), 6, 2, MFLAGS,
631 0, 5, DFLAGS, RK3399_CLKGATE_CON(4), 10, GFLAGS),
632
633 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5,
634 DFLAGS, RK3399_CLKGATE_CON(4), 8, GFLAGS),
635 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0, RK3399_CLKSEL_CON(11), 8, 5, DFLAGS, RK3399_CLKGATE_CON(4), 9,
636 GFLAGS),
637 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, RK3399_CLKGATE_CON(16), 10, GFLAGS),
638 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(16), 11, GFLAGS),
639
640 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3399_CLKGATE_CON(16), 8, GFLAGS),
641 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(16), 9, GFLAGS),
642
643 /* center */
644 COMPOSITE(ACLK_CENTER, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IS_CRITICAL, RK3399_CLKSEL_CON(12), 14, 2,
645 MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(3), 7, GFLAGS),
646 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(19), 0,
647 GFLAGS),
648 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(19), 1,
649 GFLAGS),
650
651 /* gpu */
652 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(13), 5, 3,
653 MFLAGS, 0, 5, DFLAGS, RK3399_CLKGATE_CON(13), 0, GFLAGS),
654 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK3399_CLKGATE_CON(30), 8, GFLAGS),
655 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0, RK3399_CLKGATE_CON(30), 10, GFLAGS),
656 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0, RK3399_CLKGATE_CON(30), 11, GFLAGS),
657 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0, RK3399_CLKGATE_CON(13), 1, GFLAGS),
658
659 /* perihp */
660 GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(5), 1, GFLAGS),
661 GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(5), 0, GFLAGS),
662 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IS_CRITICAL, RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5,
663 DFLAGS, RK3399_CLKGATE_CON(5), 2, GFLAGS),
664 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IS_CRITICAL, RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
665 RK3399_CLKGATE_CON(5), 3, GFLAGS),
666 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IS_CRITICAL, RK3399_CLKSEL_CON(14), 12, 3, DFLAGS,
667 RK3399_CLKGATE_CON(5), 4, GFLAGS),
668
669 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0, RK3399_CLKGATE_CON(20), 2, GFLAGS),
670 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0, RK3399_CLKGATE_CON(20), 10, GFLAGS),
671 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(20), 12, GFLAGS),
672
673 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0, RK3399_CLKGATE_CON(20), 5, GFLAGS),
674 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0, RK3399_CLKGATE_CON(20), 6, GFLAGS),
675 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0, RK3399_CLKGATE_CON(20), 7, GFLAGS),
676 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0, RK3399_CLKGATE_CON(20), 8, GFLAGS),
677 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0, RK3399_CLKGATE_CON(20), 9, GFLAGS),
678 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(20), 13, GFLAGS),
679 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(20), 15, GFLAGS),
680
681 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(20), 4, GFLAGS),
682 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0, RK3399_CLKGATE_CON(20), 11, GFLAGS),
683 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(20), 14, GFLAGS),
684 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0, RK3399_CLKGATE_CON(31), 8, GFLAGS),
685
686 /* sdio & sdmmc */
687 COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
688 RK3399_CLKGATE_CON(12), 13, GFLAGS),
689 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0, RK3399_CLKGATE_CON(33), 8, GFLAGS),
690 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(33), 9, GFLAGS),
691
692 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, RK3399_CLKSEL_CON(15), 8, 3, MFLAGS,
693 0, 7, DFLAGS, RK3399_CLKGATE_CON(6), 0, GFLAGS),
694
695 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, RK3399_CLKSEL_CON(16), 8, 3,
696 MFLAGS, 0, 7, DFLAGS, RK3399_CLKGATE_CON(6), 1, GFLAGS),
697
698 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
699 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
700
701 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
702 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
703
704 /* pcie */
705 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0, RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0,
706 7, DFLAGS, RK3399_CLKGATE_CON(6), 2, GFLAGS),
707
708 COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0, RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
709 RK3399_CLKGATE_CON(12), 6, GFLAGS),
710 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(18), 10,
711 1, MFLAGS),
712
713 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
714 DFLAGS, RK3399_CLKGATE_CON(6), 3, GFLAGS),
715 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(18), 7, 1,
716 MFLAGS),
717
718 /* emmc */
719 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0, RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0,
720 7, DFLAGS, RK3399_CLKGATE_CON(6), 14, GFLAGS),
721
722 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(6), 13, GFLAGS),
723 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(6), 12, GFLAGS),
724 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0,
725 5, DFLAGS),
726 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(32), 8, GFLAGS),
727 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(32), 9, GFLAGS),
728 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(32), 10, GFLAGS),
729
730 /* perilp0 */
731 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(7), 1, GFLAGS),
732 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(7), 0, GFLAGS),
733 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IS_CRITICAL, RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0,
734 5, DFLAGS, RK3399_CLKGATE_CON(7), 2, GFLAGS),
735 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
736 RK3399_CLKGATE_CON(7), 3, GFLAGS),
737 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
738 RK3399_CLKGATE_CON(7), 4, GFLAGS),
739
740 /* aclk_perilp0 gates */
741 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
742 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
743 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
744 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
745 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
746 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
747 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
748 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
749 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
750 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
751 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 6, GFLAGS),
752 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 7, GFLAGS),
753
754 /* hclk_perilp0 gates */
755 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
756 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
757 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
758 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
759 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
760 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 8, GFLAGS),
761
762 /* pclk_perilp0 gates */
763 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
764
765 /* crypto */
766 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0, RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5,
767 DFLAGS, RK3399_CLKGATE_CON(7), 7, GFLAGS),
768
769 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0, RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5,
770 DFLAGS, RK3399_CLKGATE_CON(7), 8, GFLAGS),
771
772 /* cm0s_perilp */
773 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0, RK3399_CLKGATE_CON(7), 6, GFLAGS),
774 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0, RK3399_CLKGATE_CON(7), 5, GFLAGS),
775 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0, RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
776 RK3399_CLKGATE_CON(7), 9, GFLAGS),
777
778 /* fclk_cm0s gates */
779 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
780 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
781 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
782 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
783 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 11, GFLAGS),
784
785 /* perilp1 */
786 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(8), 1, GFLAGS),
787 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(8), 0, GFLAGS),
788 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IS_CRITICAL, RK3399_CLKSEL_CON(25), 7, 1,
789 MFLAGS, 0, 5, DFLAGS),
790 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
791 RK3399_CLKGATE_CON(8), 2, GFLAGS),
792
793 /* hclk_perilp1 gates */
794 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 9, GFLAGS),
795 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 12, GFLAGS),
796 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
797 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
798 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
799 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
800 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
801 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
802 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(34), 6, GFLAGS),
803
804 /* pclk_perilp1 gates */
805 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
806 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
807 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
808 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
809 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
810 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
811 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
812 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
813 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
814 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
815 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
816 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
817 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
818 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
819 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
820 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
821 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
822 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
823 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
824 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
825 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 10, GFLAGS),
826
827 /* saradc */
828 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, RK3399_CLKSEL_CON(26), 8, 8, DFLAGS, RK3399_CLKGATE_CON(9),
829 11, GFLAGS),
830
831 /* tsadc */
832 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0, RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
833 RK3399_CLKGATE_CON(9), 10, GFLAGS),
834
835 /* cif_testout */
836 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
837 COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1", mux_clk_testout1_p, 0, RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5,
838 DFLAGS, RK3399_CLKGATE_CON(13), 14, GFLAGS),
839
840 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
841 COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2", mux_clk_testout2_p, 0, RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5,
842 DFLAGS, RK3399_CLKGATE_CON(13), 15, GFLAGS),
843
844 /* vio */
845 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(42), 6, 2,
846 MFLAGS, 0, 5, DFLAGS, RK3399_CLKGATE_CON(11), 0, GFLAGS),
847 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", CLK_IS_CRITICAL, RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
848 RK3399_CLKGATE_CON(11), 1, GFLAGS),
849
850 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(29), 0, GFLAGS),
851
852 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0, RK3399_CLKGATE_CON(29), 1, GFLAGS),
853 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0, RK3399_CLKGATE_CON(29), 2, GFLAGS),
854 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(29), 12, GFLAGS),
855
856 /* hdcp */
857 COMPOSITE_NOGATE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0, RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8,
858 5, DFLAGS),
859 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0, RK3399_CLKSEL_CON(43), 5, 5, DFLAGS, RK3399_CLKGATE_CON(11),
860 3, GFLAGS),
861 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0, RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
862 RK3399_CLKGATE_CON(11), 10, GFLAGS),
863
864 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(29), 4, GFLAGS),
865 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0, RK3399_CLKGATE_CON(29), 10, GFLAGS),
866
867 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(29), 5, GFLAGS),
868 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0, RK3399_CLKGATE_CON(29), 9, GFLAGS),
869
870 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(29), 3, GFLAGS),
871 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0, RK3399_CLKGATE_CON(29), 6, GFLAGS),
872 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0, RK3399_CLKGATE_CON(29), 7, GFLAGS),
873 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0, RK3399_CLKGATE_CON(29), 8, GFLAGS),
874 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0, RK3399_CLKGATE_CON(29), 11, GFLAGS),
875
876 /* edp */
877 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0, RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5,
878 DFLAGS, RK3399_CLKGATE_CON(11), 8, GFLAGS),
879
880 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
881 RK3399_CLKGATE_CON(11), 11, GFLAGS),
882 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(32), 12, GFLAGS),
883 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0, RK3399_CLKGATE_CON(32), 13, GFLAGS),
884
885 /* hdmi */
886 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, RK3399_CLKGATE_CON(11), 6, GFLAGS),
887
888 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0, RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
889 RK3399_CLKGATE_CON(11), 7, GFLAGS),
890
891 /* vop0 */
892 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(47), 6, 2,
893 MFLAGS, 0, 5, DFLAGS, RK3399_CLKGATE_CON(10), 8, GFLAGS),
894 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0, RK3399_CLKSEL_CON(47), 8, 5, DFLAGS, RK3399_CLKGATE_CON(10),
895 9, GFLAGS),
896
897 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0, RK3399_CLKGATE_CON(28), 3, GFLAGS),
898 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(28), 1, GFLAGS),
899
900 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0, RK3399_CLKGATE_CON(28), 2, GFLAGS),
901 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(28), 0, GFLAGS),
902
903 #ifdef RK3399_TWO_PLL_FOR_VOP
904 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p,
905 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
906 RK3399_CLKGATE_CON(10), 12, GFLAGS),
907 #else
908 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(49),
909 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 12, GFLAGS),
910 #endif
911
912 /* The VOP0 is main screen, it is able to re-set parent rate. */
913 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(106), 0,
914 &rk3399_dclk_vop0_fracmux, RK3399_VOP_FRAC_MAX_PRATE),
915
916 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0, RK3399_CLKSEL_CON(51), 6, 2,
917 MFLAGS, 0, 5, DFLAGS, RK3399_CLKGATE_CON(10), 14, GFLAGS),
918
919 /* vop1 */
920 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(48), 6, 2,
921 MFLAGS, 0, 5, DFLAGS, RK3399_CLKGATE_CON(10), 10, GFLAGS),
922 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0, RK3399_CLKSEL_CON(48), 8, 5, DFLAGS, RK3399_CLKGATE_CON(10),
923 11, GFLAGS),
924
925 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0, RK3399_CLKGATE_CON(28), 7, GFLAGS),
926 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(28), 5, GFLAGS),
927
928 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0, RK3399_CLKGATE_CON(28), 6, GFLAGS),
929 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(28), 4, GFLAGS),
930
931 /* The VOP1 is sub screen, it is note able to re-set parent rate. */
932 #ifdef RK3399_TWO_PLL_FOR_VOP
933 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p,
934 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
935 RK3399_CLKGATE_CON(10), 13, GFLAGS),
936 #else
937 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_dmyvpll_cpll_gpll_p, 0, RK3399_CLKSEL_CON(50), 8, 2, MFLAGS,
938 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 13, GFLAGS),
939 #endif
940
941 COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0, RK3399_CLKSEL_CON(107), 0,
942 &rk3399_dclk_vop1_fracmux, RK3399_VOP_FRAC_MAX_PRATE),
943
944 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0, RK3399_CLKSEL_CON(52), 6, 2,
945 MFLAGS, 0, 5, DFLAGS, RK3399_CLKGATE_CON(10), 15, GFLAGS),
946
947 /* isp */
948 COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0, RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5,
949 DFLAGS, RK3399_CLKGATE_CON(12), 8, GFLAGS),
950 COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0, RK3399_CLKSEL_CON(53), 8, 5, DFLAGS, RK3399_CLKGATE_CON(12),
951 9, GFLAGS),
952
953 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(27), 1, GFLAGS),
954 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0, RK3399_CLKGATE_CON(27), 5, GFLAGS),
955
956 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(27), 0, GFLAGS),
957 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0, RK3399_CLKGATE_CON(27), 4, GFLAGS),
958
959 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
960 RK3399_CLKGATE_CON(11), 4, GFLAGS),
961
962 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0, RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5,
963 DFLAGS, RK3399_CLKGATE_CON(12), 10, GFLAGS),
964 COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0, RK3399_CLKSEL_CON(54), 8, 5, DFLAGS, RK3399_CLKGATE_CON(12),
965 11, GFLAGS),
966
967 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(27), 3, GFLAGS),
968 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "aclk_isp1", 0, RK3399_CLKGATE_CON(27), 8, GFLAGS),
969
970 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(27), 2, GFLAGS),
971 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "hclk_isp1", 0, RK3399_CLKGATE_CON(27), 7, GFLAGS),
972
973 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5,
974 DFLAGS, RK3399_CLKGATE_CON(11), 5, GFLAGS),
975
976 /*
977 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
978 * so we ignore the mux and make clocks nodes as following,
979 *
980 * pclkin_cifinv --|-------\
981 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
982 * pclkin_cif --|-------/
983 */
984 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0, RK3399_CLKGATE_CON(27), 6, GFLAGS),
985
986 /* cif */
987 COMPOSITE_NODIV(SCLK_CIF_OUT_SRC, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0, RK3399_CLKSEL_CON(56), 6, 2,
988 MFLAGS, RK3399_CLKGATE_CON(10), 7, GFLAGS),
989
990 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0, RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
991
992 /* gic */
993 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL, RK3399_CLKSEL_CON(56), 15, 1,
994 MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(12), 12, GFLAGS),
995
996 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(33), 0, GFLAGS),
997 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(33), 1, GFLAGS),
998 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED,
999 RK3399_CLKGATE_CON(33), 2, GFLAGS),
1000 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED,
1001 RK3399_CLKGATE_CON(33), 3, GFLAGS),
1002 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED,
1003 RK3399_CLKGATE_CON(33), 4, GFLAGS),
1004 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED,
1005 RK3399_CLKGATE_CON(33), 5, GFLAGS),
1006
1007 /* alive */
1008 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1009 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0, RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1010
1011 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1012 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1013 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1014 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1015 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1016
1017 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1018 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1019 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1020 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1021 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1022 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1023 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1024 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1025 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1026
1027 /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1028 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"),
1029
1030 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1031 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 0, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1032
1033 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1034 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1035 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1036 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1037
1038 /* testout */
1039 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1040 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0, RK3399_CLKSEL_CON(105), 0, RK3399_CLKGATE_CON(13), 9, GFLAGS,
1041 0),
1042
1043 DIV(0, "clk_test_24m", "xin24m", 0, RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1044
1045 /* spi */
1046 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1047 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1048
1049 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1050 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1051
1052 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1053 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1054
1055 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1056 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1057
1058 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1059 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1060
1061 /* i2c */
1062 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1063 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1064
1065 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1066 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1067
1068 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1069 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1070
1071 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1072 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1073
1074 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1075 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1076
1077 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1078 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1079
1080 /* timer */
1081 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1082 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1083 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1084 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1085 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1086 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1087 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1088 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1089 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1090 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1091 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1092 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1093
1094 /* clk_test */
1095 /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1096 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(58), 0, 5, DFLAGS,
1097 RK3399_CLKGATE_CON(13), 11, GFLAGS),
1098
1099 /* ddrc */
1100 GATE(0, "clk_ddrc_lpll_src", "lpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3), 0, GFLAGS),
1101 GATE(0, "clk_ddrc_bpll_src", "bpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3), 1, GFLAGS),
1102 GATE(0, "clk_ddrc_dpll_src", "dpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3), 2, GFLAGS),
1103 GATE(0, "clk_ddrc_gpll_src", "gpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3), 3, GFLAGS),
1104 COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0, RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
1105 };
1106
1107 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1108 /*
1109 * PMU CRU Clock-Architecture
1110 */
1111
1112 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1113
1114 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, CLK_IS_CRITICAL,
1115 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1116
1117 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0, RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1118 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1119
1120 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED, RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5,
1121 DFLAGS, RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1122
1123 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT, RK3399_PMU_CLKSEL_CON(7), 0,
1124 &rk3399_pmuclk_wifi_fracmux, RK3399_WIFI_FRAC_MAX_PRATE),
1125
1126 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED, RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1127
1128 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0, RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1129 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1130
1131 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0, RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1132 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1133
1134 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0, RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1135 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1136
1137 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1138 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED, RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1139
1140 MUX(SCLK_UART4_SRC, "clk_uart4_src", mux_24m_ppll_p, CLK_SET_RATE_NO_REPARENT, RK3399_PMU_CLKSEL_CON(5), 10, 1,
1141 MFLAGS),
1142
1143 COMPOSITE_NOMUX(0, "clk_uart4_div", "clk_uart4_src", CLK_SET_RATE_PARENT, RK3399_PMU_CLKSEL_CON(5), 0, 7, DFLAGS,
1144 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1145
1146 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT, RK3399_PMU_CLKSEL_CON(6), 0,
1147 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS, &rk3399_uart4_pmu_fracmux, RK3399_UART_FRAC_MAX_PRATE),
1148
1149 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IS_CRITICAL, RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1150
1151 /* pmu clock gates */
1152 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1153 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1154
1155 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1156
1157 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1158 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1159 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1160 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1161 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1162 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1163 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1164 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1165 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1166 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1167 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1168 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1169 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1170 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1171 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1172 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1173
1174 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1175 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1176 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1177 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1178 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1179 };
1180
1181 static void __iomem *rk3399_cru_base;
1182 static void __iomem *rk3399_pmucru_base;
1183
rk3399_dump_cru(void)1184 void rk3399_dump_cru(void)
1185 {
1186 if (rk3399_cru_base) {
1187 pr_warn("CRU:\n");
1188 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 0x20, 0x4, rk3399_cru_base, 0x594, false);
1189 }
1190 if (rk3399_pmucru_base) {
1191 pr_warn("PMU CRU:\n");
1192 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 0x20, 0x4, rk3399_pmucru_base, 0x134, false);
1193 }
1194 }
1195 EXPORT_SYMBOL_GPL(rk3399_dump_cru);
1196
rk3399_clk_panic(struct notifier_block *this, unsigned long ev, void *ptr)1197 static int rk3399_clk_panic(struct notifier_block *this, unsigned long ev, void *ptr)
1198 {
1199 rk3399_dump_cru();
1200 return NOTIFY_DONE;
1201 }
1202
1203 static struct notifier_block rk3399_clk_panic_block = {
1204 .notifier_call = rk3399_clk_panic,
1205 };
1206
rk3399_clk_init(struct device_node *np)1207 static void __init rk3399_clk_init(struct device_node *np)
1208 {
1209 struct rockchip_clk_provider *ctx;
1210 void __iomem *reg_base;
1211 struct clk **clks;
1212
1213 reg_base = of_iomap(np, 0);
1214 if (!reg_base) {
1215 pr_err("%s: could not map cru region\n", __func__);
1216 return;
1217 }
1218
1219 rk3399_cru_base = reg_base;
1220
1221 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1222 if (IS_ERR(ctx)) {
1223 pr_err("%s: rockchip clk init failed\n", __func__);
1224 iounmap(reg_base);
1225 return;
1226 }
1227 clks = ctx->clk_data.clks;
1228
1229 rockchip_clk_register_plls(ctx, rk3399_pll_clks, ARRAY_SIZE(rk3399_pll_clks), -1);
1230
1231 rockchip_clk_register_branches(ctx, rk3399_clk_branches, ARRAY_SIZE(rk3399_clk_branches));
1232
1233 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", 4, clks[PLL_APLLL], clks[PLL_GPLL], &rk3399_cpuclkl_data,
1234 rk3399_cpuclkl_rates, ARRAY_SIZE(rk3399_cpuclkl_rates));
1235
1236 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", 4, clks[PLL_APLLB], clks[PLL_GPLL], &rk3399_cpuclkb_data,
1237 rk3399_cpuclkb_rates, ARRAY_SIZE(rk3399_cpuclkb_rates));
1238
1239 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK);
1240
1241 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1242
1243 rockchip_clk_of_add_provider(np, ctx);
1244 }
1245 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1246
rk3399_pmu_clk_init(struct device_node *np)1247 static void __init rk3399_pmu_clk_init(struct device_node *np)
1248 {
1249 struct rockchip_clk_provider *ctx;
1250 void __iomem *reg_base;
1251
1252 reg_base = of_iomap(np, 0);
1253 if (!reg_base) {
1254 pr_err("%s: could not map cru pmu region\n", __func__);
1255 return;
1256 }
1257
1258 rk3399_pmucru_base = reg_base;
1259
1260 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1261 if (IS_ERR(ctx)) {
1262 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1263 iounmap(reg_base);
1264 return;
1265 }
1266
1267 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks, ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1268
1269 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches, ARRAY_SIZE(rk3399_clk_pmu_branches));
1270
1271 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK);
1272
1273 rockchip_clk_of_add_provider(np, ctx);
1274
1275 atomic_notifier_chain_register(&panic_notifier_list, &rk3399_clk_panic_block);
1276 }
1277 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
1278
1279 struct clk_rk3399_inits {
1280 void (*inits)(struct device_node *np);
1281 };
1282
1283 static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
1284 .inits = rk3399_pmu_clk_init,
1285 };
1286
1287 static const struct clk_rk3399_inits clk_rk3399_cru_init = {
1288 .inits = rk3399_clk_init,
1289 };
1290
1291 static const struct of_device_id clk_rk3399_match_table[] = {
1292 {
1293 .compatible = "rockchip,rk3399-cru",
1294 .data = &clk_rk3399_cru_init,
1295 },
1296 {
1297 .compatible = "rockchip,rk3399-pmucru",
1298 .data = &clk_rk3399_pmucru_init,
1299 },
1300 {}
1301 };
1302 MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
1303
clk_rk3399_probe(struct platform_device *pdev)1304 static int __init clk_rk3399_probe(struct platform_device *pdev)
1305 {
1306 struct device_node *np = pdev->dev.of_node;
1307 const struct of_device_id *match;
1308 const struct clk_rk3399_inits *init_data;
1309
1310 match = of_match_device(clk_rk3399_match_table, &pdev->dev);
1311 if (!match || !match->data) {
1312 return -EINVAL;
1313 }
1314
1315 init_data = match->data;
1316 if (init_data->inits) {
1317 init_data->inits(np);
1318 }
1319
1320 return 0;
1321 }
1322
1323 static struct platform_driver clk_rk3399_driver = {
1324 .driver =
1325 {
1326 .name = "clk-rk3399",
1327 .of_match_table = clk_rk3399_match_table,
1328 .suppress_bind_attrs = true,
1329 },
1330 };
1331 builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
1332
1333 MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
1334 MODULE_LICENSE("GPL");
1335 MODULE_ALIAS("platform:clk-rk3399");
1336