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Searched refs:DFLAGS (Results 1 - 14 of 14) sorted by relevance

/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-rk1808.c191 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
257 DFLAGS | CLK_DIVIDER_READ_ONLY, RK1808_CLKGATE_CON(0), 3, GFLAGS),
259 DFLAGS | CLK_DIVIDER_READ_ONLY, RK1808_CLKGATE_CON(0), 2, GFLAGS),
265 COMPOSITE_NOMUX(MSCLK_CORE_NIU, "msclk_core_niu", "gpll", CLK_IS_CRITICAL, RK1808_CLKSEL_CON(18), 0, 5, DFLAGS,
273 4, DFLAGS, RK1808_CLKGATE_CON(1), 0, GFLAGS),
280 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 5, DFLAGS,
282 COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, RK1808_CLKSEL_CON(16), 8, 4, DFLAGS, RK1808_CLKGATE_CON(8), 9,
293 DFLAGS),
295 MFLAGS, 4, 4, DFLAGS),
300 COMPOSITE(0, "aclk_npu_pre", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(2), 14, 1, MFLAGS, 0, 4, DFLAGS,
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-rk3328.c186 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
215 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, RK3328_CLKSEL_CON(2), 8, 5, DFLAGS),
216 COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0, RK3328_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 14, DFLAGS,
233 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3328_CLKGATE_CON(7), 0, GFLAGS),
235 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3328_CLKGATE_CON(7), 1, GFLAGS),
242 COMPOSITE(0, "aclk_gpu_pre", mux_4plls_p, 0, RK3328_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
249 DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK3328_CLKGATE_CON(0), 4, GFLAGS),
256 DFLAGS, RK3328_CLKGATE_CON(7), 4, GFLAGS),
269 8, 5, DFLAGS, RK3328_CLKGATE_CON(8), 0, GFLAGS),
270 COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL, RK3328_CLKSEL_CON(1), 8, 2, DFLAGS,
[all...]
H A Dclk-rv1108.c153 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
187 DFLAGS | CLK_DIVIDER_READ_ONLY, RV1108_CLKGATE_CON(0), 5, GFLAGS),
189 DFLAGS | CLK_DIVIDER_READ_ONLY, RV1108_CLKGATE_CON(0), 4, GFLAGS),
194 COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0, RV1108_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
198 DFLAGS, RV1108_CLKGATE_CON(8), 9, GFLAGS),
206 DFLAGS, RV1108_CLKGATE_CON(8), 2, GFLAGS),
209 DFLAGS, RV1108_CLKGATE_CON(8), 1, GFLAGS),
211 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, RV1108_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
213 COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, RV1108_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
224 COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IS_CRITICAL, RV1108_CLKSEL_CON(38), 0, 5, DFLAGS,
[all...]
H A Dclk-rk3368.c166 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
283 DIV(0, "aclkm_core_b", "armclkb", 0, RK3368_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
284 DIV(0, "atclk_core_b", "armclkb", 0, RK3368_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
285 DIV(0, "pclk_dbg_b", "armclkb", 0, RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
287 DIV(0, "aclkm_core_l", "armclkl", 0, RK3368_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
288 DIV(0, "atclk_core_l", "armclkl", 0, RK3368_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
289 DIV(0, "pclk_dbg_l", "armclkl", 0, RK3368_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
295 DFLAGS),
296 COMPOSITE_NOMUX(0, "clkin_trace", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
300 6, 2, MFLAGS, 0, 5, DFLAGS, RK3368_CLKGATE_CO
[all...]
H A Dclk-rk3399.c240 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
388 DFLAGS, RK3399_CLKGATE_CON(12), 0, GFLAGS),
399 DFLAGS, RK3399_CLKGATE_CON(12), 3, GFLAGS),
402 DFLAGS, RK3399_CLKGATE_CON(12), 4, GFLAGS),
405 DFLAGS, RK3399_CLKGATE_CON(13), 4, GFLAGS),
408 2, MFLAGS, 0, 5, DFLAGS, RK3399_CLKGATE_CON(13), 5, GFLAGS),
411 DFLAGS, RK3399_CLKGATE_CON(13), 6, GFLAGS),
414 2, MFLAGS, 0, 5, DFLAGS, RK3399_CLKGATE_CON(13), 7, GFLAGS),
423 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3399_CLKGATE_CON(0), 4, GFLAGS),
425 DFLAGS | CLK_DIVIDER_READ_ONL
[all...]
H A Dclk-px30.c169 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
230 DFLAGS | CLK_DIVIDER_READ_ONLY, PX30_CLKGATE_CON(0), 2, GFLAGS),
232 DFLAGS | CLK_DIVIDER_READ_ONLY, PX30_CLKGATE_CON(0), 1, GFLAGS),
244 COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(1), 13, 2, DFLAGS,
258 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
260 DFLAGS),
274 COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 8, 5, DFLAGS,
288 COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
290 COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0, PX30_CLKSEL_CON(11), 8, 4, DFLAGS,
292 COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0, PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
[all...]
H A Dclk-rk3128.c163 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
192 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
198 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
206 DFLAGS | CLK_DIVIDER_READ_ONLY, RK2928_CLKGATE_CON(0), 0, GFLAGS),
208 DFLAGS | CLK_DIVIDER_READ_ONLY, RK2928_CLKGATE_CON(0), 7, GFLAGS),
214 COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IS_CRITICAL, RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
217 COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL, RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
219 COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL, RK2928_CLKSEL_CON(1), 12, 2, DFLAGS,
221 COMPOSITE_NOMUX(SCLK_CRYPTO, "clk_crypto", "aclk_cpu_src", 0, RK2928_CLKSEL_CON(24), 0, 2, DFLAGS,
225 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_5plls_p, 0, RK2928_CLKSEL_CON(32), 5, 3, MFLAGS, 0, 5, DFLAGS,
[all...]
H A Dclk-rk3188.c230 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
266 DFLAGS | CLK_DIVIDER_READ_ONLY, div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
268 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
271 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
277 DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(0), 2, GFLAGS),
286 5, DFLAGS, RK2928_CLKGATE_CON(3), 0, GFLAGS),
287 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
292 DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(2), 2, GFLAGS),
294 DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(2), 3, GFLAGS),
297 COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0, RK2928_CLKSEL_CON(29), 1, 5, DFLAGS, RK2928_CLKGATE_CO
[all...]
H A Dclk-rk3036.c149 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
183 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
187 DFLAGS | CLK_DIVIDER_READ_ONLY, RK2928_CLKGATE_CON(0), 7, GFLAGS),
189 DFLAGS | CLK_DIVIDER_READ_ONLY, RK2928_CLKGATE_CON(0), 7, GFLAGS),
194 DFLAGS),
197 DFLAGS | CLK_DIVIDER_READ_ONLY, RK2928_CLKGATE_CON(0), 5, GFLAGS),
199 DFLAGS | CLK_DIVIDER_READ_ONLY, RK2928_CLKGATE_CON(0), 4, GFLAGS),
202 DFLAGS, RK2928_CLKGATE_CON(2), 0, GFLAGS),
206 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
209 DFLAGS | CLK_DIVIDER_POWER_OF_TW
[all...]
H A Dclk-rk3288.c194 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
231 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3288_CLKGATE_CON(12), 0, GFLAGS),
233 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3288_CLKGATE_CON(12), 1, GFLAGS),
235 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3288_CLKGATE_CON(12), 2, GFLAGS),
237 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3288_CLKGATE_CON(12), 3, GFLAGS),
239 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3288_CLKGATE_CON(12), 4, GFLAGS),
241 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3288_CLKGATE_CON(12), 5, GFLAGS),
243 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3288_CLKGATE_CON(12), 6, GFLAGS),
244 COMPOSITE_NOMUX(0, "atclk", "armclk", 0, RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
247 DFLAGS | CLK_DIVIDER_READ_ONL
[all...]
H A Dclk-rk3308.c169 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
256 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3308_CLKGATE_CON(0), 2, GFLAGS),
258 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3308_CLKGATE_CON(0), 1, GFLAGS),
270 COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", CLK_IS_CRITICAL, RK3308_CLKSEL_CON(6), 8, 5, DFLAGS,
273 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", CLK_IS_CRITICAL, RK3308_CLKSEL_CON(6), 0, 5, DFLAGS,
275 COMPOSITE_NOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", CLK_IS_CRITICAL, RK3308_CLKSEL_CON(5), 0, 5, DFLAGS,
279 5, DFLAGS, RK3308_CLKGATE_CON(1), 9, GFLAGS),
285 5, DFLAGS, RK3308_CLKGATE_CON(1), 13, GFLAGS),
291 5, DFLAGS, RK3308_CLKGATE_CON(2), 1, GFLAGS),
297 5, DFLAGS, RK3308_CLKGATE_CO
[all...]
H A Dclk-rk3228.c171 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
200 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
207 DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(7), 1, GFLAGS),
216 DFLAGS | CLK_DIVIDER_READ_ONLY, RK2928_CLKGATE_CON(4), 1, GFLAGS),
218 DFLAGS | CLK_DIVIDER_READ_ONLY, RK2928_CLKGATE_CON(4), 0, GFLAGS),
230 DFLAGS),
232 COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL, RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
234 COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", CLK_IS_CRITICAL, RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
241 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
246 DFLAGS, RK2928_CLKGATE_CO
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk-rk3588.c515 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
681 RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
684 RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
687 RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
690 RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
693 RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
696 RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
699 RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS,
702 RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
705 RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS,
[all...]
/device/soc/rockchip/rk3566/vendor/drivers/clk/
H A Dclk-rk3568.c320 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
385 COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", npll_gpll_p, 0, RK3568_CLKSEL_CON(7), 7, 1, MFLAGS, 4, 2, DFLAGS,
393 COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(75), 0, 5, DFLAGS,
395 COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(75), 8, 5, DFLAGS,
397 COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(76), 0, 5, DFLAGS,
399 COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(76), 8, 5, DFLAGS,
401 COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(77), 0, 5, DFLAGS,
403 COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(77), 8, 5, DFLAGS,
405 COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(78), 0, 6, DFLAGS,
407 COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(78), 8, 5, DFLAGS,
[all...]

Completed in 12 milliseconds