Lines Matching refs:DFLAGS
320 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
385 COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", npll_gpll_p, 0, RK3568_CLKSEL_CON(7), 7, 1, MFLAGS, 4, 2, DFLAGS,
393 COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(75), 0, 5, DFLAGS,
395 COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(75), 8, 5, DFLAGS,
397 COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(76), 0, 5, DFLAGS,
399 COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(76), 8, 5, DFLAGS,
401 COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(77), 0, 5, DFLAGS,
403 COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(77), 8, 5, DFLAGS,
405 COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(78), 0, 6, DFLAGS,
407 COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(78), 8, 5, DFLAGS,
409 COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(79), 0, 5, DFLAGS,
411 COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(79), 8, 5, DFLAGS,
413 COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
415 COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
417 COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
419 COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
421 COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
423 COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,
431 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 5, GFLAGS),
436 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 8, GFLAGS),
438 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 9, GFLAGS),
440 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 10, GFLAGS),
442 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 11, GFLAGS),
444 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 14, GFLAGS),
446 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(0), 15, GFLAGS),
448 DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(1), 0, GFLAGS),
460 MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, RK3568_CLKGATE_CON(2), 0, GFLAGS),
463 DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0, RK3568_CLKSEL_CON(6), 8, 2, DFLAGS),
464 DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0, RK3568_CLKSEL_CON(6), 12, 4, DFLAGS),
473 COMPOSITE_BROTHER(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0, RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS,
478 COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0, RK3568_CLKSEL_CON(8), 0, 4, DFLAGS,
480 COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0, RK3568_CLKSEL_CON(8), 4, 4, DFLAGS,
493 MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(4), 0, GFLAGS),
496 COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(10), 0, 2, DFLAGS,
516 7, DFLAGS, RK3568_CLKGATE_CON(6), 0, GFLAGS),
525 7, DFLAGS, RK3568_CLKGATE_CON(6), 4, GFLAGS),
534 7, DFLAGS, RK3568_CLKGATE_CON(6), 8, GFLAGS),
543 7, DFLAGS, RK3568_CLKGATE_CON(6), 12, GFLAGS),
552 DFLAGS, RK3568_CLKGATE_CON(7), 0, GFLAGS),
561 7, DFLAGS, RK3568_CLKGATE_CON(7), 4, GFLAGS),
570 7, DFLAGS, RK3568_CLKGATE_CON(7), 8, GFLAGS),
594 DFLAGS, RK3568_CLKGATE_CON(7), 14, GFLAGS),
600 COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0, RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS,
649 COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0, RK3568_CLKSEL_CON(29), 4, 4, DFLAGS, RK3568_CLKGATE_CON(10),
692 COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", CLK_IS_CRITICAL, RK3568_CLKSEL_CON(30), 4, 4, DFLAGS,
717 COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0, RK3568_CLKSEL_CON(32), 4, 4, DFLAGS, RK3568_CLKGATE_CON(16), 2,
759 COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0, RK3568_CLKSEL_CON(34), 4, 4, DFLAGS, RK3568_CLKGATE_CON(18), 1,
761 COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0, RK3568_CLKSEL_CON(34), 8, 4, DFLAGS, RK3568_CLKGATE_CON(18), 2,
770 COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0, RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
773 COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0, RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS,
775 COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0, RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS,
778 DFLAGS, RK3568_CLKGATE_CON(19), 10, GFLAGS),
783 COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0, RK3568_CLKSEL_CON(37), 8, 4, DFLAGS, RK3568_CLKGATE_CON(20), 1,
785 COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0, RK3568_CLKSEL_CON(37), 12, 4, DFLAGS, RK3568_CLKGATE_CON(20), 2,
787 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0, RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
792 RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 10, GFLAGS),
794 RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 11, GFLAGS,
796 COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
812 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0, RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS,
814 COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, RK3568_CLKSEL_CON(42), 8, 4, DFLAGS,
822 COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0, RK3568_CLKSEL_CON(43), 8, 4, DFLAGS,
824 COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0, RK3568_CLKSEL_CON(43), 12, 4, DFLAGS,
846 DFLAGS, RK3568_CLKGATE_CON(24), 0, GFLAGS),
847 COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, RK3568_CLKSEL_CON(44), 8, 4, DFLAGS,
852 DFLAGS, RK3568_CLKGATE_CON(24), 8, GFLAGS),
854 1, MFLAGS, 0, 5, DFLAGS, RK3568_CLKGATE_CON(25), 0, GFLAGS),
855 COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, RK3568_CLKSEL_CON(47), 8, 4, DFLAGS,
860 DFLAGS, RK3568_CLKGATE_CON(25), 6, GFLAGS),
862 14, 2, MFLAGS, 8, 5, DFLAGS, RK3568_CLKGATE_CON(25), 7, GFLAGS),
864 0, 5, DFLAGS, RK3568_CLKGATE_CON(25), 8, GFLAGS),
873 DFLAGS, RK3568_CLKGATE_CON(26), 5, GFLAGS),
874 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0, RK3568_CLKSEL_CON(51), 8, 7, DFLAGS,
886 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
894 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
902 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
910 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
918 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
926 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
934 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
942 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
950 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0, RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
958 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS,
961 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS,
964 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS,
1051 COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", CLK_IS_CRITICAL, RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS,
1056 COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0, RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1063 COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED, RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
1067 7, DFLAGS, RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS),
1077 COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0, RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
1083 COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0, RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
1093 COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0, RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS,
1097 COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0, RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS,
1102 COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0, RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS,
1107 COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0, RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS,