Lines Matching refs:DFLAGS
191 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
257 DFLAGS | CLK_DIVIDER_READ_ONLY, RK1808_CLKGATE_CON(0), 3, GFLAGS),
259 DFLAGS | CLK_DIVIDER_READ_ONLY, RK1808_CLKGATE_CON(0), 2, GFLAGS),
265 COMPOSITE_NOMUX(MSCLK_CORE_NIU, "msclk_core_niu", "gpll", CLK_IS_CRITICAL, RK1808_CLKSEL_CON(18), 0, 5, DFLAGS,
273 4, DFLAGS, RK1808_CLKGATE_CON(1), 0, GFLAGS),
280 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 5, DFLAGS,
282 COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, RK1808_CLKSEL_CON(16), 8, 4, DFLAGS, RK1808_CLKGATE_CON(8), 9,
293 DFLAGS),
295 MFLAGS, 4, 4, DFLAGS),
300 COMPOSITE(0, "aclk_npu_pre", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(2), 14, 1, MFLAGS, 0, 4, DFLAGS,
302 COMPOSITE(0, "hclk_npu_pre", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 4, DFLAGS,
306 COMPOSITE_NOMUX(0, "aclk_npu2mem", "aclk_npu_pre", CLK_IGNORE_UNUSED, RK1808_CLKSEL_CON(2), 4, 4, DFLAGS,
314 5, DFLAGS, RK1808_CLKGATE_CON(7), 0, GFLAGS),
325 DFLAGS, RK1808_CLKGATE_CON(7), 5, GFLAGS),
344 DFLAGS),
347 COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IS_CRITICAL, RK1808_CLKSEL_CON(3), 8, 5, DFLAGS,
360 COMPOSITE(HSCLK_VIO, "hsclk_vio", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(4), 7, 1, MFLAGS, 0, 5, DFLAGS,
362 COMPOSITE_NOMUX(LSCLK_VIO, "lsclk_vio", "hsclk_vio", 0, RK1808_CLKSEL_CON(4), 8, 4, DFLAGS, RK1808_CLKGATE_CON(3),
380 COMPOSITE(0, "dclk_vopraw_src", mux_cpll_gpll_npll_p, 0, RK1808_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 8, DFLAGS,
386 COMPOSITE(0, "dclk_voplite_src", mux_cpll_gpll_npll_p, 0, RK1808_CLKSEL_CON(7), 10, 2, MFLAGS, 0, 8, DFLAGS,
392 COMPOSITE_NOMUX(SCLK_TXESC, "clk_txesc", "gpll", 0, RK1808_CLKSEL_CON(9), 0, 12, DFLAGS, RK1808_CLKGATE_CON(3), 7,
395 COMPOSITE(SCLK_RGA, "clk_rga", mux_gpll_cpll_npll_p, 0, RK1808_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
398 COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0, RK1808_CLKSEL_CON(10), 14, 2, MFLAGS, 8, 5, DFLAGS,
401 COMPOSITE(DCLK_CIF, "dclk_cif", mux_cpll_gpll_npll_p, 0, RK1808_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
405 DFLAGS, RK1808_CLKGATE_CON(3), 9, GFLAGS),
414 DIV(HSCLK_PCIE, "hsclk_pcie", "clk_pcie_src", 0, RK1808_CLKSEL_CON(12), 0, 5, DFLAGS),
415 DIV(LSCLK_PCIE, "lsclk_pcie", "clk_pcie_src", 0, RK1808_CLKSEL_CON(12), 8, 5, DFLAGS),
423 COMPOSITE(ACLK_PCIE, "aclk_pcie", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(15), 8, 1, MFLAGS, 0, 4, DFLAGS,
425 DIV(0, "pclk_pcie_pre", "aclk_pcie", 0, RK1808_CLKSEL_CON(15), 4, 4, DFLAGS),
433 COMPOSITE(0, "clk_pcie_aux_src", mux_cpll_gpll_npll_p, 0, RK1808_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
441 MFLAGS, 0, 10, DFLAGS, RK1808_CLKGATE_CON(5), 2, GFLAGS),
451 COMPOSITE_NOMUX(MSCLK_PERI, "msclk_peri", "clk_peri_src", CLK_IS_CRITICAL, RK1808_CLKSEL_CON(19), 0, 5, DFLAGS,
453 COMPOSITE_NOMUX(LSCLK_PERI, "lsclk_peri", "clk_peri_src", CLK_IS_CRITICAL, RK1808_CLKSEL_CON(19), 8, 5, DFLAGS,
466 MFLAGS, 0, 8, DFLAGS, RK1808_CLKGATE_CON(9), 1, GFLAGS),
468 RK1808_CLKSEL_CON(22), 14, 2, MFLAGS, RK1808_CLKSEL_CON(23), 0, 8, DFLAGS,
477 MFLAGS, 0, 8, DFLAGS, RK1808_CLKGATE_CON(9), 4, GFLAGS),
479 RK1808_CLKSEL_CON(24), 14, 2, MFLAGS, RK1808_CLKSEL_CON(25), 0, 8, DFLAGS,
487 2, MFLAGS, 0, 8, DFLAGS, RK1808_CLKGATE_CON(9), 7, GFLAGS),
489 RK1808_CLKSEL_CON(20), 14, 2, MFLAGS, RK1808_CLKSEL_CON(21), 0, 8, DFLAGS,
496 COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 7, DFLAGS,
513 DFLAGS, RK1808_CLKGATE_CON(10), 15, GFLAGS),
516 DFLAGS, RK1808_CLKGATE_CON(10), 3, GFLAGS),
541 COMPOSITE_NOMUX(HSCLK_BUS_PRE, "hsclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL, RK1808_CLKSEL_CON(27), 8, 5, DFLAGS,
543 COMPOSITE_NOMUX(MSCLK_BUS_PRE, "msclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL, RK1808_CLKSEL_CON(28), 0, 5, DFLAGS,
545 COMPOSITE_NOMUX(LSCLK_BUS_PRE, "lsclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL, RK1808_CLKSEL_CON(28), 8, 5, DFLAGS,
589 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 5, DFLAGS,
591 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_p, 0, RK1808_CLKSEL_CON(29), 15, 1, MFLAGS, 8, 5, DFLAGS,
594 COMPOSITE(0, "clk_uart1_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 7, DFLAGS,
596 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0, RK1808_CLKSEL_CON(39), 0, 7, DFLAGS,
602 COMPOSITE(0, "clk_uart2_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(41), 14, 2, MFLAGS, 0, 7, DFLAGS,
604 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0, RK1808_CLKSEL_CON(42), 0, 7, DFLAGS,
610 COMPOSITE(0, "clk_uart3_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(44), 14, 2, MFLAGS, 0, 7, DFLAGS,
612 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0, RK1808_CLKSEL_CON(45), 0, 7, DFLAGS,
618 COMPOSITE(0, "clk_uart4_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(47), 14, 2, MFLAGS, 0, 7, DFLAGS,
620 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0, RK1808_CLKSEL_CON(48), 0, 7, DFLAGS,
626 COMPOSITE(0, "clk_uart5_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(50), 14, 2, MFLAGS, 0, 7, DFLAGS,
628 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0, RK1808_CLKSEL_CON(51), 0, 7, DFLAGS,
634 COMPOSITE(0, "clk_uart6_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(53), 14, 2, MFLAGS, 0, 7, DFLAGS,
636 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart6_np5", "clk_uart6_src", 0, RK1808_CLKSEL_CON(54), 0, 7, DFLAGS,
642 COMPOSITE(0, "clk_uart7_src", mux_gpll_usb480m_cpll_npll_p, 0, RK1808_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 7, DFLAGS,
644 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart7_np5", "clk_uart7_src", 0, RK1808_CLKSEL_CON(57), 0, 7, DFLAGS,
650 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
652 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
654 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
656 COMPOSITE(SCLK_I2C4, "clk_i2c4", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 7, DFLAGS,
658 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(71), 15, 1, MFLAGS, 8, 7, DFLAGS,
661 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
663 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
665 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
668 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0, RK1808_CLKSEL_CON(62), 0, 11, DFLAGS, RK1808_CLKGATE_CON(13),
670 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, RK1808_CLKSEL_CON(63), 0, 11, DFLAGS,
673 COMPOSITE(SCLK_EFUSE_S, "clk_efuse_s", mux_gpll_cpll_xin24m_p, 0, RK1808_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 6, DFLAGS,
676 DFLAGS, RK1808_CLKGATE_CON(14), 1, GFLAGS),
678 COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(65), 15, 1, MFLAGS, 0, 11, DFLAGS,
680 COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(66), 15, 1, MFLAGS, 0, 11, DFLAGS,
682 COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(67), 15, 1, MFLAGS, 0, 11, DFLAGS,
684 COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0, RK1808_CLKSEL_CON(68), 15, 1, MFLAGS, 0, 11, DFLAGS,
687 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(69), 7, 1, MFLAGS, 0, 7, DFLAGS,
689 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(69), 15, 1, MFLAGS, 8, 7, DFLAGS,
691 COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 7, DFLAGS,
713 COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_cpll_npll_p, 0, RK1808_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 7, DFLAGS,
720 0, 7, DFLAGS, RK1808_CLKGATE_CON(17), 12, GFLAGS),
729 0, 7, DFLAGS, RK1808_CLKGATE_CON(18), 0, GFLAGS),
738 DFLAGS, RK1808_CLKGATE_CON(18), 4, GFLAGS),
770 COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED, RK1808_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
773 COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "ppll", 0, RK1808_PMU_CLKSEL_CON(2), 8, 6, DFLAGS, RK1808_PMU_CLKGATE_CON(0),
779 DFLAGS, RK1808_PMU_CLKGATE_CON(1), 0, GFLAGS),
780 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0, RK1808_PMU_CLKSEL_CON(4), 0, 7, DFLAGS,
790 DFLAGS, RK1808_PMU_CLKGATE_CON(1), 5, GFLAGS),
793 DFLAGS, RK1808_PMU_CLKGATE_CON(1), 6, GFLAGS),
795 COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "ppll", 0, RK1808_PMU_CLKSEL_CON(2), 0, 6, DFLAGS,
803 COMPOSITE_NOMUX(0, "clk_pciephy_src", "clk_ppll_ph0", 0, RK1808_PMU_CLKSEL_CON(7), 0, 2, DFLAGS,
808 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "ppll", CLK_IS_CRITICAL, RK1808_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,