H A D | assembler-riscv64.cc | 1147 VRegister vs1, VRegister vs2, MaskType mask) { in GenInstrV() 1151 ((vs1.code() & 0x1F) << kRvvVs1Shift) | in GenInstrV() 1157 int8_t vs1, VRegister vs2, MaskType mask) { in GenInstrV() 1161 ((vs1 & 0x1F) << kRvvVs1Shift) | in GenInstrV() 1167 VRegister vs1, VRegister vs2, MaskType mask) { in GenInstrV() 1171 ((vs1.code() & 0x1F) << kRvvVs1Shift) | in GenInstrV() 1178 VRegister vs1, VRegister vs2, MaskType mask) { in GenInstrV() 1182 ((vs1.code() & 0x1F) << kRvvVs1Shift) | in GenInstrV() 1275 uint8_t vs1, VRegister vs2, MaskType mask) { in GenInstrV() 1279 ((vs1 in GenInstrV() 1146 GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, VRegister vs1, VRegister vs2, MaskType mask) GenInstrV() argument 1156 GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, int8_t vs1, VRegister vs2, MaskType mask) GenInstrV() argument 1166 GenInstrV(uint8_t funct6, Opcode opcode, Register rd, VRegister vs1, VRegister vs2, MaskType mask) GenInstrV() argument 1177 GenInstrV(uint8_t funct6, Opcode opcode, FPURegister fd, VRegister vs1, VRegister vs2, MaskType mask) GenInstrV() argument 1274 GenInstrV(uint8_t funct6, Opcode opcode, Register rd, uint8_t vs1, VRegister vs2, MaskType mask) GenInstrV() argument 2476 vredmaxu_vs(VRegister vd, VRegister vs2, VRegister vs1, MaskType mask) vredmaxu_vs() argument 2481 vredmax_vs(VRegister vd, VRegister vs2, VRegister vs1, MaskType mask) vredmax_vs() argument 2486 vredmin_vs(VRegister vd, VRegister vs2, VRegister vs1, MaskType mask) vredmin_vs() argument 2491 vredminu_vs(VRegister vd, VRegister vs2, VRegister vs1, MaskType mask) vredminu_vs() argument 2496 vmv_vv(VRegister vd, VRegister vs1) vmv_vv() argument 2516 vmerge_vv(VRegister vd, VRegister vs1, VRegister vs2) vmerge_vv() argument 2528 vadc_vv(VRegister vd, VRegister vs1, VRegister vs2) vadc_vv() argument 2540 vmadc_vv(VRegister vd, VRegister vs1, VRegister vs2) vmadc_vv() argument 2552 vrgather_vv(VRegister vd, VRegister vs2, VRegister vs1, MaskType mask) vrgather_vv() argument [all...] |