Lines Matching refs:vs1
1147 VRegister vs1, VRegister vs2, MaskType mask) {
1151 ((vs1.code() & 0x1F) << kRvvVs1Shift) |
1157 int8_t vs1, VRegister vs2, MaskType mask) {
1161 ((vs1 & 0x1F) << kRvvVs1Shift) |
1167 VRegister vs1, VRegister vs2, MaskType mask) {
1171 ((vs1.code() & 0x1F) << kRvvVs1Shift) |
1178 VRegister vs1, VRegister vs2, MaskType mask) {
1182 ((vs1.code() & 0x1F) << kRvvVs1Shift) |
1275 uint8_t vs1, VRegister vs2, MaskType mask) {
1279 ((vs1 & 0x1F) << kRvvVs1Shift) |
2476 void Assembler::vredmaxu_vs(VRegister vd, VRegister vs2, VRegister vs1,
2478 GenInstrV(VREDMAXU_FUNCT6, OP_MVV, vd, vs1, vs2, mask);
2481 void Assembler::vredmax_vs(VRegister vd, VRegister vs2, VRegister vs1,
2483 GenInstrV(VREDMAX_FUNCT6, OP_MVV, vd, vs1, vs2, mask);
2486 void Assembler::vredmin_vs(VRegister vd, VRegister vs2, VRegister vs1,
2488 GenInstrV(VREDMIN_FUNCT6, OP_MVV, vd, vs1, vs2, mask);
2491 void Assembler::vredminu_vs(VRegister vd, VRegister vs2, VRegister vs1,
2493 GenInstrV(VREDMINU_FUNCT6, OP_MVV, vd, vs1, vs2, mask);
2496 void Assembler::vmv_vv(VRegister vd, VRegister vs1) {
2497 GenInstrV(VMV_FUNCT6, OP_IVV, vd, vs1, v0, NoMask);
2516 void Assembler::vmerge_vv(VRegister vd, VRegister vs1, VRegister vs2) {
2517 GenInstrV(VMV_FUNCT6, OP_IVV, vd, vs1, vs2, Mask);
2528 void Assembler::vadc_vv(VRegister vd, VRegister vs1, VRegister vs2) {
2529 GenInstrV(VADC_FUNCT6, OP_IVV, vd, vs1, vs2, Mask);
2540 void Assembler::vmadc_vv(VRegister vd, VRegister vs1, VRegister vs2) {
2541 GenInstrV(VMADC_FUNCT6, OP_IVV, vd, vs1, vs2, Mask);
2552 void Assembler::vrgather_vv(VRegister vd, VRegister vs2, VRegister vs1,
2554 DCHECK_NE(vd, vs1);
2556 GenInstrV(VRGATHER_FUNCT6, OP_IVV, vd, vs1, vs2, mask);
2581 void Assembler::name##_vv(VRegister vd, VRegister vs2, VRegister vs1, \
2583 GenInstrV(funct6, OP_IVV, vd, vs1, vs2, mask); \
2587 void Assembler::name##_vv(VRegister vd, VRegister vs2, VRegister vs1, \
2589 GenInstrV(funct6, OP_FVV, vd, vs1, vs2, mask); \
2593 void Assembler::name##_wv(VRegister vd, VRegister vs2, VRegister vs1, \
2595 GenInstrV(funct6, OP_FVV, vd, vs1, vs2, mask); \
2599 void Assembler::name##_vs(VRegister vd, VRegister vs2, VRegister vs1, \
2601 GenInstrV(funct6, OP_FVV, vd, vs1, vs2, mask); \
2617 void Assembler::name##_vv(VRegister vd, VRegister vs2, VRegister vs1, \
2619 GenInstrV(funct6, OP_MVV, vd, vs1, vs2, mask); \
2643 void Assembler::name##_vv(VRegister vd, VRegister vs1, VRegister vs2, \
2645 GenInstrV(funct6, OP_FVV, vd, vs1, vs2, mask); \
2655 #define DEFINE_OPMVV_VIE(name, vs1) \
2657 GenInstrV(VXUNARY0_FUNCT6, OP_MVV, vd, vs1, vs2, mask); \