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Searched refs:util_logbase2 (Results 1 - 25 of 119) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_state_binning.c343 const unsigned fragmentsLog2 = util_logbase2(num_fragments); in gfx10_get_bin_sizes()
344 const unsigned samplesLog2 = util_logbase2(num_samples); in gfx10_get_bin_sizes()
358 const unsigned colorLog2Pixels = util_logbase2(colorBinSizeTagPart / cColor); in gfx10_get_bin_sizes()
368 const unsigned fmaskLog2Pixels = util_logbase2(fmaskBinSizeTagPart / cFmask); in gfx10_get_bin_sizes()
396 const unsigned depthLog2Pixels = util_logbase2(depthBinSizeTagPart / MAX2(cDepth, 1u)); in gfx10_get_bin_sizes()
417 bin_size_extend.x = util_logbase2(bin_size.x) - 5; in si_emit_dpbb_disable()
419 bin_size_extend.y = util_logbase2(bin_size.y) - 5; in si_emit_dpbb_disable()
505 bin_size_extend.x = util_logbase2(bin_size.x) - 5; in si_emit_dpbb_state()
507 bin_size_extend.y = util_logbase2(bin_size.y) - 5; in si_emit_dpbb_state()
H A Dsi_test_dma_perf.c259 struct si_result *r = &results[util_logbase2(size)][placement][method]; in si_test_dma_perf()
326 struct si_result *r = &results[util_logbase2(size)][placement][i]; in si_test_dma_perf()
386 &results[util_logbase2(size)][placement][prev->index]; in si_test_dma_perf()
H A Dsi_sdma_copy_image.c61 return util_logbase2(tex->surface.bpe) | in encode_legacy_tile_info()
65 ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) | in encode_legacy_tile_info()
188 radeon_emit(util_logbase2(bpp) | in si_sdma_v4_v5_copy_texture()
270 (util_logbase2(bpp) << 29)); in cik_sdma_copy_texture()
H A Dsi_compute_blit.c846 unsigned bpe_log2 = util_logbase2(tex->surface.bpe); in gfx9_clear_dcc_msaa()
847 unsigned log2_samples = util_logbase2(tex->buffer.b.b.nr_samples); in gfx9_clear_dcc_msaa()
878 unsigned log_fragments = util_logbase2(tex->nr_storage_samples); in si_compute_expand_fmask()
879 unsigned log_samples = util_logbase2(tex->nr_samples); in si_compute_expand_fmask()
/third_party/mesa3d/src/panfrost/lib/
H A Dpan_tiler.c210 #define MIN_TILE_SHIFT util_logbase2(MIN_TILE_SIZE)
211 #define MAX_TILE_SHIFT util_logbase2(MAX_TILE_SIZE)
346 unsigned exp_w = util_logbase2(best_w / 16); in panfrost_choose_tile_size()
347 unsigned exp_h = util_logbase2(best_h / 16); in panfrost_choose_tile_size()
H A Dpan_attributes.c100 unsigned shift = util_logbase2(hw_divisor); in panfrost_compute_magic_divisor()
/third_party/mesa3d/src/amd/common/
H A Dac_surface_meta_address_test.c72 unsigned meta_block_width_log2 = util_logbase2(meta_block_width); in gfx9_meta_addr_from_coord()
73 unsigned meta_block_height_log2 = util_logbase2(meta_block_height); in gfx9_meta_addr_from_coord()
74 unsigned meta_block_depth_log2 = util_logbase2(meta_block_depth); in gfx9_meta_addr_from_coord()
133 unsigned meta_block_width_log2 = util_logbase2(meta_block_width); in gfx10_meta_addr_from_coord()
134 unsigned meta_block_height_log2 = util_logbase2(meta_block_height); in gfx10_meta_addr_from_coord()
183 unsigned bpp_log2 = util_logbase2(bpp >> 3); in gfx10_dcc_addr_from_coord()
184 unsigned meta_block_width_log2 = util_logbase2(meta_block_width); in gfx10_dcc_addr_from_coord()
185 unsigned meta_block_height_log2 = util_logbase2(meta_block_height); in gfx10_dcc_addr_from_coord()
242 xin.format = format[util_logbase2(bpp / 8)]; in one_dcc_address_test()
409 unsigned meta_block_width_log2 = util_logbase2(meta_block_widt in gfx10_htile_addr_from_coord()
[all...]
H A Dac_surface.c756 surf->meta_alignment_log2 = MAX2(surf->meta_alignment_log2, util_logbase2(AddrDccOut->dccRamBaseAlign)); in gfx6_compute_level()
834 surf->meta_alignment_log2 = util_logbase2(AddrHtileOut->baseAlign); in gfx6_compute_level()
908 surf->surf_alignment_log2 = util_logbase2(csio->baseAlign); in gfx6_surface_settings()
1009 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in ac_compute_cmask()
1327 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign); in gfx6_compute_surface()
1744 surf->surf_alignment_log2 = MAX2(surf->surf_alignment_log2, util_logbase2(out.baseAlign)); in gfx9_compute_miptree()
1765 surf->surf_alignment_log2 = util_logbase2(out.baseAlign); in gfx9_compute_miptree()
1830 surf->meta_alignment_log2 = util_logbase2(hout.baseAlign); in gfx9_compute_miptree()
1935 surf->meta_alignment_log2 = util_logbase2(dout.dccRamBaseAlign); in gfx9_compute_miptree()
2013 surf->u.gfx9.color.display_dcc_alignment_log2 = util_logbase2(dou in gfx9_compute_miptree()
[all...]
/third_party/mesa3d/src/gallium/drivers/nouveau/nv30/
H A Dnv30_clear.c143 rt_format |= util_logbase2(sf->width) << 16; in nv30_clear_render_target()
144 rt_format |= util_logbase2(sf->height) << 24; in nv30_clear_render_target()
204 rt_format |= util_logbase2(sf->width) << 16; in nv30_clear_depth_stencil()
205 rt_format |= util_logbase2(sf->height) << 24; in nv30_clear_depth_stencil()
H A Dnv30_texture.c299 so->fmt |= util_logbase2(pt->width0) << 20; in nv30_sampler_view_create()
300 so->fmt |= util_logbase2(pt->height0) << 24; in nv30_sampler_view_create()
301 so->fmt |= util_logbase2(pt->depth0) << 28; in nv30_sampler_view_create()
H A Dnv30_transfer.c190 format |= util_logbase2(dst->w) << 16; in nv30_transfer_rect_blit()
191 format |= util_logbase2(dst->h) << 24; in nv30_transfer_rect_blit()
453 PUSH_DATA (push, ss_fmt | (util_logbase2(dst->w) << 16) | in nv30_transfer_rect_sifm()
454 (util_logbase2(dst->h) << 24)); in nv30_transfer_rect_sifm()
571 unsigned k = util_logbase2(MIN2(rect->w, rect->h)); in swizzle2d_ptr()
/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_nir_lower_multiview.c34 *mask = BIT(util_logbase2(old_mask) + 1) - 1; in lower_multiview_mask()
87 unsigned num_views = util_logbase2(mask) + 1; in tu_nir_lower_multiview()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c191 surf_ws->surf_alignment_log2 = util_logbase2(surf_drm->bo_alignment); in surf_drm_to_winsys()
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
341 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
403 surf_ws->fmask_alignment_log2 = util_logbase2(MAX2(256, 1 << fmask.surf_alignment_log2)); in radeon_winsys_surface_init()
/third_party/mesa3d/src/imagination/vulkan/
H A Dpvr_limits.h61 util_logbase2(__ret) + 1; \
H A Dpvr_tex_state.c97 word0.smpcnt = util_logbase2(info->sample_count); in pvr_pack_tex_state()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dcayman_msaa.c235 unsigned log_samples = util_logbase2(setup_samples); in cayman_emit_msaa_state()
237 util_logbase2(util_next_power_of_two(ps_iter_samples)); in cayman_emit_msaa_state()
/third_party/mesa3d/src/freedreno/fdl/
H A Dfd6_view.c248 A6XX_TEX_CONST_0_SAMPLES(util_logbase2(layout->nr_samples)) | in fdl6_view_init()
334 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(util_logbase2(layout->nr_samples)) | in fdl6_view_init()
424 A6XX_RB_BLIT_DST_INFO_SAMPLES(util_logbase2(layout->nr_samples)) | in fdl6_view_init()
/third_party/mesa3d/src/gallium/frontends/lavapipe/
H A Dlvp_formats.c235 maxMipLevels = util_logbase2(max_2d_ext) + 1; in lvp_get_image_format_properties()
242 maxMipLevels = util_logbase2(max_2d_ext) + 1; in lvp_get_image_format_properties()
254 maxMipLevels = util_logbase2(max_2d_ext) + 1; in lvp_get_image_format_properties()
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_emit_gv100.cpp222 emitField(84, 2, util_logbase2(typeSizeof(insn->sType))); in emitF2F()
225 emitField(75, 2, util_logbase2(typeSizeof(insn->dType))); in emitF2F()
236 emitField(84, 2, util_logbase2(typeSizeof(insn->sType))); in emitF2I()
240 emitField(75, 2, util_logbase2(typeSizeof(insn->dType))); in emitF2I()
273 emitField(84, 2, util_logbase2(typeSizeof(insn->sType))); in emitFRND()
276 emitField(75, 2, util_logbase2(typeSizeof(insn->dType))); in emitFRND()
286 emitField(84, 2, util_logbase2(typeSizeof(insn->sType))); in emitI2F()
288 emitField(75, 2, util_logbase2(typeSizeof(insn->dType))); in emitI2F()
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_ir_fs.h300 const int delta = util_logbase2(type_sz(reg.type)) -
301 util_logbase2(type_sz(type));
/third_party/mesa3d/src/util/
H A Du_math.h393 util_logbase2(unsigned n) in util_logbase2() function
435 return 1 + util_logbase2(n - 1); in util_logbase2_ceil()
H A Dvl_vlc.h67 unsigned i, bits = util_logbase2(dst_size); in vl_vlc_init_table()
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c911 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw)); in radv_amdgpu_winsys_bo_set_metadata()
912 tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->u.legacy.bankh)); in radv_amdgpu_winsys_bo_set_metadata()
916 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea)); in radv_amdgpu_winsys_bo_set_metadata()
917 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks) - 1); in radv_amdgpu_winsys_bo_set_metadata()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_sdma_copy_image.c150 util_logbase2(bpp) | image->planes[0].surface.u.gfx9.swizzle_mode << 3 | in radv_sdma_v4_v5_copy_image_to_buffer()
/third_party/mesa3d/src/gallium/auxiliary/pipebuffer/
H A Dpb_bufmgr_mm.c196 mm_buf->base.alignment_log2 = util_logbase2(desc->alignment); in mm_bufmgr_create_buffer()

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