Lines Matching refs:util_logbase2
756 surf->meta_alignment_log2 = MAX2(surf->meta_alignment_log2, util_logbase2(AddrDccOut->dccRamBaseAlign));
834 surf->meta_alignment_log2 = util_logbase2(AddrHtileOut->baseAlign);
908 surf->surf_alignment_log2 = util_logbase2(csio->baseAlign);
1009 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align));
1327 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign);
1744 surf->surf_alignment_log2 = MAX2(surf->surf_alignment_log2, util_logbase2(out.baseAlign));
1765 surf->surf_alignment_log2 = util_logbase2(out.baseAlign);
1830 surf->meta_alignment_log2 = util_logbase2(hout.baseAlign);
1935 surf->meta_alignment_log2 = util_logbase2(dout.dccRamBaseAlign);
2013 surf->u.gfx9.color.display_dcc_alignment_log2 = util_logbase2(dout.dccRamBaseAlign);
2049 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign);
2120 surf->cmask_alignment_log2 = util_logbase2(cout.baseAlign);
2691 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(surf->u.legacy.bankw));
2692 *tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(surf->u.legacy.bankh));
2696 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(surf->u.legacy.mtilea));
2697 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(surf->u.legacy.num_banks) - 1);
2745 unsigned log_samples = util_logbase2(MAX2(1, num_storage_samples));
2871 unsigned bpe_shift = util_logbase2(surf->bpe) / 2;
3136 unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width);
3137 unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height);
3191 unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width);
3192 unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height);
3193 unsigned meta_block_depth_log2 = util_logbase2(equation->meta_block_depth);
3255 unsigned bpp_log2 = util_logbase2(bpe);