Searched refs:RASR (Results 1 - 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A D	armv7m_mpu.h	183 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR member 219 MPU->RASR = 0U; in ARM_MPU_ClrRegion() 224 * \param rasr Value for RASR register. 229 MPU->RASR = rasr; in ARM_MPU_SetRegion() 235 * \param rasr Value for RASR register. 241 MPU->RASR = rasr; in ARM_MPU_SetRegionEx()
/third_party/cmsis/CMSIS/Core/Include/
H A D	core_sc000.h	547 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ member 587 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 588 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 590 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 591 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 593 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 594 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 596 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 597 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 599 #define MPU_RASR_S_Pos 18U /*!< MPU RASR [all...]
H A D	core_cm0plus.h	531 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ member 571 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 572 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 574 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 575 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 577 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 578 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 580 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 581 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 583 #define MPU_RASR_S_Pos 18U /*!< MPU RASR [all...]
H A D	core_cm4.h	1216 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ member 1262 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 1263 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 1265 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 1266 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 1268 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 1269 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 1271 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 1272 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 1274 #define MPU_RASR_S_Pos 18U /*!< MPU RASR [all...]
H A D	core_sc300.h	1134 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ member 1180 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 1181 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 1183 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 1184 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 1186 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 1187 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 1189 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 1190 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 1192 #define MPU_RASR_S_Pos 18U /*!< MPU RASR [all...]
H A D	core_cm3.h	1151 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ member 1197 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 1198 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 1200 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 1201 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 1203 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 1204 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 1206 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 1207 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 1209 #define MPU_RASR_S_Pos 18U /*!< MPU RASR [all...]
H A D	core_cm7.h	1435 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ member 1481 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 1482 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 1484 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 1485 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 1487 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 1488 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 1490 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 1491 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 1493 #define MPU_RASR_S_Pos 18U /*!< MPU RASR [all...]

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Indexes created Thu Nov 07 10:32:03 CST 2024