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Searched refs:PIPE_CONTROL (Results 1 - 9 of 9) sorted by relevance

/third_party/mesa3d/src/intel/vulkan/
H A DgenX_query.c619 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_ps_depth_count()
646 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_query_pc_availability()
666 /* These queries are written with a PIPE_CONTROL so clear them using the in emit_zero_queries()
667 * PIPE_CONTROL as well so we don't have to synchronize between 2 types in emit_zero_queries()
749 /* Add a CS stall here to make sure the PIPE_CONTROL above has in CmdResetQueryPool()
751 * commands might race with the PIPE_CONTROL in the loop above. in CmdResetQueryPool()
936 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in CmdBeginQueryIndexedEXT()
946 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in CmdBeginQueryIndexedEXT()
962 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in CmdBeginQueryIndexedEXT()
1020 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), p in CmdBeginQueryIndexedEXT()
[all...]
H A DgenX_cmd_buffer.c60 convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) { in convert_pc_to_bits()
109 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in cmd_buffer_emit_state_base_address()
128 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in cmd_buffer_emit_state_base_address()
258 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit in cmd_buffer_emit_state_base_address()
259 * which, according the PIPE_CONTROL instruction documentation in the in cmd_buffer_emit_state_base_address()
267 * invalidation through a PIPE_CONTROL does nothing whatsoever in in cmd_buffer_emit_state_base_address()
283 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in cmd_buffer_emit_state_base_address()
291 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL", in cmd_buffer_emit_state_base_address()
293 * "Workaround : “CS Stall” bit in PIPE_CONTROL command must be in cmd_buffer_emit_state_base_address()
1139 * In order to work around this issue, we emit a PIPE_CONTROL wit in copy_fast_clear_dwords()
[all...]
H A Dgfx8_cmd_buffer.c43 /* According to the Broadwell PIPE_CONTROL documentation, software should in cmd_buffer_enable_pma_fix()
44 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set in cmd_buffer_enable_pma_fix()
52 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in cmd_buffer_enable_pma_fix()
59 /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must in cmd_buffer_enable_pma_fix()
60 * be set with any PIPE_CONTROL with Depth Flush Enable bit set. in cmd_buffer_enable_pma_fix()
92 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache in cmd_buffer_enable_pma_fix()
99 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in cmd_buffer_enable_pma_fix()
H A DgenX_state.c860 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) { in emit_shading_rate()
/third_party/FreeBSD/sys/compat/linuxkpi/common/include/linux/
H A Dusb.h176 #define PIPE_CONTROL 0x00 /* UE_CONTROL */ macro
191 usb_find_host_endpoint(dev, PIPE_CONTROL, (endpoint) | USB_DIR_OUT)
194 usb_find_host_endpoint(dev, PIPE_CONTROL, (endpoint) | USB_DIR_IN)
/third_party/mesa3d/src/intel/blorp/
H A Dblorp_genX_exec.h248 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall in emit_urb_config()
251 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL in emit_urb_config()
254 blorp_emit(batch, GENX(PIPE_CONTROL), pc) { in emit_urb_config()
1379 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL in blorp_emit_pipeline()
1658 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { in blorp_setup_binding_table()
1784 blorp_emit(batch, GENX(PIPE_CONTROL), pc) { in blorp_emit_depth_stencil_config()
1892 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set in blorp_emit_gfx8_hiz_op()
1895 blorp_emit(batch, GENX(PIPE_CONTROL), pc) { in blorp_emit_gfx8_hiz_op()
1913 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { in blorp_update_clear_color()
1947 blorp_emit(batch, GENX(PIPE_CONTROL), pip in blorp_update_clear_color()
[all...]
/third_party/mesa3d/src/intel/common/
H A Dmi_builder.h1173 mi_builder_emit(b, GENX(PIPE_CONTROL), pc) { in mi_self_mod_barrier()
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_state.c438 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit in flush_after_state_base_change()
439 * which, according the PIPE_CONTROL instruction documentation in the in flush_after_state_base_change()
447 * invalidation through a PIPE_CONTROL does nothing whatsoever in in flush_after_state_base_change()
648 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL in emit_pipeline_select()
1764 /* According to the Broadwell PIPE_CONTROL documentation, software should in update_pma_fix()
1765 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set in update_pma_fix()
1784 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache in update_pma_fix()
6070 /* The PIPE_CONTROL command description says: in iris_upload_dirty_render_state()
6240 * SW must insert a PIPE_CONTROL cm in iris_upload_dirty_render_state()
[all...]
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_state.c461 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit in flush_after_state_base_change()
462 * which, according the PIPE_CONTROL instruction documentation in the in flush_after_state_base_change()
470 * invalidation through a PIPE_CONTROL does nothing whatsoever in in flush_after_state_base_change()
1080 * which involves a first PIPE_CONTROL flush which stalls the pipeline... in setup_l3_config()
1086 /* ...followed by a second pipelined PIPE_CONTROL that initiates in setup_l3_config()
1088 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL in setup_l3_config()
1207 * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
1245 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL in emit_pipeline_select()
1271 * MI_FLUSH or PIPE_CONTROL prio in emit_pipeline_select()
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